(cherry picked from commit 9bcf6ccdd87c3be48fe7d75150c6e403c5c0a42d) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit db7a99c423dea0ead19d6a18053d898a762a3b48) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 8ba64ba5cb301bca777ba7f0d2a2a72f49af5ff2) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 6e03c7e28e2d929a420809a24b0379305a9fb86a) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The Quality-of-Service (QsS) node stores/restores specific
register contents when the power domains is turned off/on.
Add QoS node so that they can connect to the power domain.
(cherry picked from commit 9ee90dfd6957fcc42ea94c43d195b01d1b286713) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:37 +0000 (22:46 +0000)]
arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528
Add pinctrl and gpio nodes for RK3528 and import rk3528-pinctrl.dtsi
from vendor linux-6.1-stan-rkr5 kernel with the hdmi-pins-idle node
removed due to missing label reference to pcfg_output_low_pull_down.
(cherry picked from commit 89a24fa2e923b68a42ccc8cc9cb2d5bdf291ac40) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 12f69f638472dc9cf1b62816c7d4407de1846d12) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Yao Zi [Mon, 7 Apr 2025 22:46:35 +0000 (22:46 +0000)]
arm64: dts: rockchip: Add clock generators for RK3528 SoC
Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is
generated by internal Ethernet phy, a fixed clock node is added as a
placeholder to avoid orphans.
(cherry picked from commit 60741472b42e92d2393327cb70669ab90e3b382f) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Yao Zi [Mon, 7 Apr 2025 22:46:34 +0000 (22:46 +0000)]
dt-bindings: clock: Document clock and reset unit of RK3528
There are two types of clocks in RK3528 SoC, CRU-managed and
SCMI-managed. Independent IDs are assigned to them.
For the reset part, differing from previous Rockchip SoCs and
downstream bindings which embeds register offsets into the IDs, gapless
numbers starting from zero are used.
(cherry picked from commit 8768d063e732e64892e4d1d09aa583d1394c8388) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 8 Apr 2025 22:11:45 +0000 (22:11 +0000)]
rng: rockchip_rng: Update compatible for RK3588
Linux commit 6ee0b9ad3995 ("arm64: dts: rockchip: Add rng node to
RK3588") merged for v6.15-rc1 add a proper rng node to the device tree.
The compatible used differs compared to what U-Boot is currently using.
Replace the old trngv1 compatible with the dts/upstream compatible in
the rng driver and remove the old rng node compatible override from SoC
u-boot.dtsi to keep rng working after the driver change.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 4800c4aaad00ffdc053850f130e8504a04dd110d) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 8 Apr 2025 22:11:43 +0000 (22:11 +0000)]
rockchip: rk356x: Remove rng node from u-boot.dtsi
Linux commit afeccc408496 ("arm64: dts: rockchip: add DT entry for RNG
to RK356x") merged for v6.12-rc1 add a proper rng node to the SoC DT.
Remove the rng node from SoC u-boot.dtsi now that the rng driver support
the compatible used in dts/upstream DT. Ensure the rng node is enabled
to support rng on RK3566 variants.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 8 Apr 2025 22:11:42 +0000 (22:11 +0000)]
rng: rockchip_rng: Add compatible for RK3568
Linux commit afeccc408496 ("arm64: dts: rockchip: add DT entry for RNG
to RK356x") merged for v6.12-rc1 add a proper rng node to the SoC DT.
The compatible used differs compared to what U-Boot is currently using.
Add support for the rk3568-rng used in upstream Linux. Support for the
cryptov2-rng compatible is still kept because PX30/RK3326 and RK3308 are
still using it.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Thu, 20 Feb 2025 21:56:58 +0000 (21:56 +0000)]
rockchip: Move imply ROCKCHIP_COMMON_STACK_ADDR under SoC Kconfig symbol
The ROCKCHIP_COMMON_STACK_ADDR Kconfig option was originally enabled
in the SoC specific Kconfig files to ease during the initial migration
to use common stack addresses.
All boards for the affected SoCs have been migrated to use common stack
addresses. Migrate to use an imply under the SoC symbol instead of
re-define the symbol in each SoC specific Kconfig file.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Thu, 20 Feb 2025 21:56:57 +0000 (21:56 +0000)]
rockchip: Improve ARMv7 support for ROCKCHIP_COMMON_STACK_ADDR
A few Rockchip ARMv7 SoCs use 0x60000000 as DRAM base address instead of
the more common 0x0 DRAM base address used on AArch64 SoCs.
Add default options that should work for these ARMv7 SoCs. Same offsets
as before are used, just below 64 MiB. Hex values have also been padded
to improve alignment.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Thu, 20 Feb 2025 21:56:56 +0000 (21:56 +0000)]
rockchip: Make ROCKCHIP_COMMON_STACK_ADDR depend on TPL
The stack-pointer addresses used with ROCKCHIP_COMMON_STACK_ADDR expect
that DRAM is initialized by TPL or ROCKCHIP_EXTERNAL_TPL, that SPL has
access to full DRAM and SPL is loaded to/executed from start of DRAM.
Add depends on to ensure use of the ROCKCHIP_COMMON_STACK_ADDR symbol
does not cause problem for any board not using TPL and back-to-BROM
loading of SPL.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Thu, 20 Feb 2025 21:56:55 +0000 (21:56 +0000)]
rockchip: Move imply TPL_ROCKCHIP_COMMON_BOARD under SoC Kconfig symbol
The Kconfig symbol ROCKCHIP_COMMON_STACK_ADDR currently imply the
TPL_ROCKCHIP_COMMON_BOARD option when TPL=y. This is inconvenient for a
SoC with very limited SRAM to use a custom tpl.c together with the
common stack addresses.
Move any imply TPL_ROCKCHIP_COMMON_BOARD to under the SoC symbol, where
it belongs. Add the missing imply to RK3328 and PX30 use a SoC specific
tpl.c and only expect imply TPL_LIBGENERIC_SUPPORT.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Wed, 29 Jan 2025 10:43:34 +0000 (11:43 +0100)]
rockchip: ringneck-px30: enable DT overlay support
Haikou carrierboard allows multiple adapter boards to be connected, for
now there exists the following adapter boards compatible with PX30
Ringneck:
- Haikou Video Demo on the Video Connector,
- Haikou LVDS 9904379 on the Video Connector,
So support DT overlays so we can use this mechanism instead of full DTB
containing both the carrierboard and the adapter.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Wed, 29 Jan 2025 10:43:32 +0000 (11:43 +0100)]
rockchip: px30: enable RNG for all boards
I don't see a reason why this should only be enabled on a per-board
basis. The rng IP is inside the SoC and doesn't seem to rely on anything
external to it, therefore let's enable it on the SoC DTSI and remove the
now empty px30-evb-u-boot.dtsi.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Wed, 29 Jan 2025 15:24:23 +0000 (16:24 +0100)]
rockchip: theobroma-systems: use HAVE_VENDOR_COMMON_LIB to simplify Makefile
The build system uses HAVE_VENDOR_COMMON_LIB to automatically include
board/$(VENDOR)/common/Makefile, therefore let's use that to implicitly
include board/theobroma-systems/common/Makefile and compile the common.c
file when building proper.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The default value of 0x800000 (8 MB) is somewhat limiting for us, as our
compressed kernel may grow up to around 4 MB. By choosing the commonly
used value of 0x2000000 (32 MB), we are definitely on the safe side.
This rather large amount should be fine, as we have 128 MB of RAM.
Signed-off-by: Ezra Buehler <ezra.buehler@husqvarnagroup.com> Reviewed-by: Stefan Roese <sr@denx.de>
Tom Rini [Tue, 22 Apr 2025 21:13:21 +0000 (15:13 -0600)]
Merge patch series "MIPS: Boston: Various enhancements"
Jiaxun Yang <jiaxun.yang@flygoat.com> says:
This is a huge series which promoted MIPS/Boston target into a
usable state, with fixes to drivers and general framework issues
I found in this process.
I also converted the target to OF_UPSTREAM.
This target is covered by QEMU, to test on QEMU:
```
make boston64r6el_defconfig
make
qemu-system-mips64el -M boston -cpu I6500 -bios ./u-boot.bin -nographic
```
Jiaxun Yang [Fri, 17 May 2024 18:14:53 +0000 (19:14 +0100)]
ahci: dwc_ahsata: Generalize the driver
Remove hard dependencies to arch headers, get clock from clk
subsystem if arch clock function is not available, align
compatible strings with devicetree binding.
No functional change on existing platforms, just get it build
on other platforms.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Jiaxun Yang [Fri, 17 May 2024 18:14:52 +0000 (19:14 +0100)]
ahci: DMA addressing fixes
Ensure that we are using correct physical/virtual address for
DMA buffer write and hardware register settings.
The convention is: in ahci_ioports all pointers are virtual,
that will be converted to physical address when writing to
hardware registers or into sg/cmd_tbl.
Also fixed 64bit physical address support for dwc_ahsata, ensure
higher bits are written into registers/sg properly.
Use memalign for allocating aligned buffer in dwc_ahsata so we
don't have to do our own alignment in driver.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Jiaxun Yang [Fri, 17 May 2024 18:14:49 +0000 (19:14 +0100)]
pci: xilinx: Handle size of ecam region properly
Probe size of ecam from devicetree properly and cap accessible
bus number accorading to ecam region size to ensure we don't go
beyond hardware address space.
Also disable all interrupts to ensure errors are handled silently.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
There is a bug in the print_guid() unit test in test/common/print.c when
PARTITION_TYPE_GUID is not enabled but either CMD_EFIDEBUG or EFI are.
The first patch fixes the issue and the second one enables UNIT_TEST in
the qemu_arm64 defconfig so that the unit tests are run in CI (this
platform has CMD_EFIDEBUG so the bug applies).
lib/uuid.c: use unique name for PARTITION_SYSTEM_GUID
The name defined for PARTITION_SYSTEM_GUID in list_guid[] depends on
configuration options. It is "system" if CONFIG_PARTITION_TYPE_GUID is
enabled or "System Partition" if CONFIG_CMD_EFIDEBUG or CONFIG_EFI are
enabled. In addition, the unit test in test/common/print.c is incorrect
because it expects only "system" (or a hex GUID).
Make things more consistent by using a clear and unique name: "EFI
System Partition" whatever the configuration, and update the unit test
accordingly.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
configs: enable CONFIG_UNIT_TEST for all qemu* generic targets
The qemu* "generic" targets (i.e. not those emulating a particular
board) are typically used for testing as many features as possible,
especially in CI so it makes sense to have UNIT_TEST enabled for
all of the defconfigs for these targets.
Not enabling UNIT_TEST in qemu-x86_defconfig due to:
Tom Rini [Tue, 22 Apr 2025 13:59:38 +0000 (07:59 -0600)]
Merge tag 'u-boot-socfpga-next-20250422' of https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request contains updates for the SoCFPGA platform, targeting
the 2025.07 release cycle. Highlights include enhancements to Agilex5
support, improvements in DDR error handling, and bridge reset handling
for SoC64 devices.
Key updates:
Agilex5 platform enhancements:
* New MMU region mappings and memory layout updates using
LMB_ARCH_MEM_MAP.
* Fixes for bloblist configuration, kernel FIT image generation, and
VAB flow enablement.
* GPIO pin control added for SDIO selection.
* Marvell PHY driver enabled in defconfig.
SoC64 improvements:
* Enhanced mailbox communication with the SDM to reflect various
boot stage transitions.
* Implemented F2S bridge reset support and updated related reset
manager registers.
* Expanded SoC64 CPU info reporting.
General maintenance:
* Additional peripherals released from reset for Arria10.
* Cleanup of legacy or incorrect Kconfig implications.
This patch set has been tested on Agilex 5 devkit.
Passing all pipeline tests at:
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/25867
Add a Kconfig option to disable sending Stop conditions between multiple
i2c_msgs within a single xfer. Enable this config by default for ARCH_K3
platforms.
i2c: omap24xx_i2c: support CONFIG for repeated start in DM_I2C xfer
Repeated Start Condition (Sr) can be used to transfer multiple i2c msgs
without sending a Stop condition (P). So far, the driver default was to
always send a Stop condition after every i2c msg.
Add support for a config option (CONFIG_SYS_I2C_OMAP24XX_REPEATED_START)
to disable sending the Stop condition by default. If this config is
enabled, Stop condition will be sent only if explicitly requested in the
msg flags OR if it is the last msg in the transfer.
Consequently, handle the Repeated Start condition (Sr) in the next msg
by not calling the wait_for_bb() check since it will simply timeout in
the absence of a stop condition (BB will be 1 until Stop is programmed)
i2c: omap24xx_i2c: Use new function __omap24_i2c_xfer_msg()
Remove __omap24_i2c_read/write() usage from omap_i2c_xfer() in favour of
the more flexible __omap24_i2c_xfer_msg().
Consequently, these are also no longer needed when DM_I2C is enabled.
New function __omap24_i2c_xfer_msg() will take care of individual read
OR write transfers with a target device. It goes through below sequence:
- Program the provided Target Chip address (OMAP_I2C_SA_REG)
- Program the provided Data len (OMAP_I2C_CNT_REG)
- Program the provided Control register flags (OMAP_I2C_CON_REG)
- Read from or Write to the provided Data buffer (OMAP_I2C_DATA_REG)
For a detailed programming guide, refer to the TRM[0] (12.1.3.4 I2C
Programming Guide).
This patch by itself should be a transparent change. However this is
needed for implementing a proper Repeated Start (Sr) functionality for
i2c_msgs.
Previous implementation for omap_i2c_xfer called __omap24_i2c_read/write
functions, with hardcoded addr=0 and alen=0 for each i2c_msg. Each of
these calls would program the registers always with a Stop bit set, not
allowing for a repeated start between i2c_msgs in the same xfer().
In-line ECC support was added for LPDDR by reserving the last one-eighth
of the memory space for ECC data. Full memory initialization using the
BIST MEM INIT mailbox command, based on address and size, is required to
correctly generate ECC data and enable proper ECC logic verification.
LMB_ARCH_MEM_MAP is enabled, and lmb_arch_add_memory() is introduced to
correctly handle memory reservations for the second and third DDR
memory banks.
CONFIG_BLOBLIST_FIXED and CONFIG_BLOBLIST_ADDR options were
unintentionally removed during recent external updates to the defconfig.
This patch restores the missing entries to ensure proper board
functionality. No new features are introduced.
Fixes: d6a53f523afe ("spl: Add an SPL_HAVE_INIT_STACK option") Signed-off-by: Tingting Meng <tingting.meng@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Tom Rini [Sat, 15 Mar 2025 01:29:00 +0000 (19:29 -0600)]
ARM: socfpga: Drop incorrect imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION*
The use of both "imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION" and
"imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE" here is wrong as
those are both part of the same choice statement. Furthermore you cannot
select/imply something from a choice statement, it must be a "default ...
if ..." construct within the choice statement in question.
configs: Enable VAB flow for Agilex5 SoCFPGA boards
Vendor Authorized Boot flow configurations are enabled for boards
based on Agilex5 SoCFPGA. Also, required changes are made to the
SoCFPGA make file for building and linking relevant secure source
code files.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
arm: socfpga: mailbox: Notify SDM on HPS code execution stages
Introducing a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure
Device Manager (SDM) on the stage of HPS code execution.
Generally, there are three main code execution stages: First Stage Boot
Loader (FSBL) which is U-Boot SPL, Second Stage Boot Loader (SSBL) which
is U-Boot, and the Operating System (OS) which is Linux.
This enables the user to query the SDM for HPS error details.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
reset: socfpga: release more A10 peripherals out of reset
Current implementation releases most peripherals out of reset for
gen5, but A10 has more peripherals than gen5, hence this patch is
required to release the rest of peripherals to support old kernels.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com> Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
drivers: ddr: altera: Fix integer overflow during size calculation
Data structure, dramaddrw, is defined as u32. Compiler performs
32-bit arithmetic and logic operations on this data structure. Fix
is provided to avoid integer overflow while performing shifting
operations greater than 32-bit.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
fs/squashfs: avoid illegal free() in sqfs_opendir()
* Use calloc() to allocate token_list. This avoids an illegal free if
sqfs_tokenize() fails.
* Do not iterate over token_list if it has not been allocated.
Addresses-Coverity-ID: 510453: Null pointer dereferences (FORWARD_NULL) Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Joao Marcos Costa <joaomarcos.costa@bootlin.com> Reviewed-by: Joao Marcos Costa <jmcosta944@gmail.com>
Marek Vasut [Sun, 13 Apr 2025 08:55:04 +0000 (10:55 +0200)]
fs: exfat: Implement trivial 'rename' support
Implement exfat_fs_rename() to rename or move files. This is used
by the 'mv' generic FS interface command. The rename implementation
for other filesystems was added recently and was not part of exfat
porting layer due to merge issue, which made 'mv' command crash,
fix this by adding the missing implementation.
Marek Vasut [Sun, 13 Apr 2025 08:55:02 +0000 (10:55 +0200)]
fs: exfat: Fix exfat_fs_exists() return value
The exfat_fs_exists() should return 0 in case the path does not exist,
and 1 in case the path does exist. Fix the inverted return value. This
fixes 'test -e' command with exfat.
Marek Vasut [Sun, 13 Apr 2025 08:55:01 +0000 (10:55 +0200)]
fs: exfat: Rework exfat_fs_readdir() to behave like exfat_fs_ls()
The exfat_fs_readdir() depends on state created in exfat_fs_opendir(),
but that state may be disrupted by fs_close() called by the FS layer
in fs_opendir(), because exfat porting layer unmounts the filesystem
in ->close() callback.
To avoid this disruption, avoid creating state in exfat_fs_opendir(),
cache only the directory name to list there, and rework exfat_fs_readdir()
to work in a similar way to exfat_fs_ls(). That is, make exfat_fs_readdir()
open the directory, look up specific entry, extract its properties to be
reported to FS layer, and close the directory. This is slow, but avoids
the disruption. The slowness does not affect regular 'ls' command, which
uses exfat_fs_ls() fast path.
Marek Vasut [Sun, 13 Apr 2025 08:55:00 +0000 (10:55 +0200)]
fs: exfat: Inhibit "impossible" print on write to bogus file
Write into a bogus file, like '/.', triggers an "impossible"
print from the exfat core code. That should not be printed
in U-Boot, because U-Boot prints its own error message sooner.
Inhibit this error message.
The following command triggers the bogus print:
"
=> save host 0:0 1000008 /. 0x10
"
Marek Vasut [Sun, 13 Apr 2025 08:54:59 +0000 (10:54 +0200)]
fs: exfat: Flush node before put in read() callback
Make sure the node is never dirty before being released, flush
the node first using exfat_flush_node() and only then release
the node using exfat_put_node(). This now matches the behavior
of exfat_fs_write() too.
Tom Rini [Mon, 21 Apr 2025 13:28:50 +0000 (07:28 -0600)]
Merge tag 'rpi-2025.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-raspberrypi
Updates for RPi for 2025.07:
- copy over uart clock-frequency in DT
- always set fdt_addr with firmware-provided FDT address
- Set bootm_size to 512MB
- Drop fdt_high and initrd_high
- Update environment to support booti and large initrd
projects / thirdparty / u-boot.git / log
