Stephen Boyd [Wed, 26 Mar 2025 18:26:36 +0000 (11:26 -0700)]
Merge branches 'clk-allwinner', 'clk-amlogic' and 'clk-qcom' into clk-next
* clk-allwinner:
clk: sunxi-ng: add support for the A523/T527 PRCM CCU
clk: sunxi-ng: a523: add reset lines
clk: sunxi-ng: a523: add bus clock gates
clk: sunxi-ng: a523: remaining mod clocks
clk: sunxi-ng: a523: add USB mod clocks
clk: sunxi-ng: a523: add interface mod clocks
clk: sunxi-ng: a523: add system mod clocks
clk: sunxi-ng: a523: add video mod clocks
clk: sunxi-ng: a523: Add support for bus clocks
clk: sunxi-ng: Add support for the A523/T527 CCU PLLs
dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs
clk: sunxi-ng: Add support for update bit
clk: sunxi-ng: mp: provide wrappers for setting feature flags
clk: sunxi-ng: mp: introduce dual-divider clock
clk: sunxi-ng: h616: Reparent GPU clock during frequency changes
clk: sunxi-ng: h616: Add clock/reset for LCD TCON
dt-bindings: clock: sun50i-h616-ccu: Add LCD TCON clk and reset
* clk-amlogic:
clk: amlogic: a1: fix a typo
clk: amlogic: gxbb: drop non existing 32k clock parent
clk: amlogic: gxbb: drop incorrect flag on 32k clock
clk: amlogic: g12b: fix cluster A parent data
clk: amlogic: g12a: fix mmc A peripheral clock
* clk-qcom: (41 commits)
clk: qcom: Add NSS clock Controller driver for IPQ9574
clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock
dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
clk: qcom: gcc-msm8953: fix stuck venus0_core0 clock
clk: qcom: mmcc-sdm660: fix stuck video_subcore0 clock
dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps
drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock
clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490
dt-bindings: clock: qcom: Add compatible for QCM6490 boards
clk: qcom: gdsc: Update the status poll timeout for GDSC
clk: qcom: gdsc: Set retain_ff before moving to HW CTRL
clk: qcom: gcc-sm8650: Do not turn off USB GDSCs during gdsc_disable()
clk: qcom: videocc: Constify 'struct qcom_cc_desc'
clk: qcom: gpucc: Constify 'struct qcom_cc_desc'
clk: qcom: dispcc: Constify 'struct qcom_cc_desc'
clk: qcom: camcc: Constify 'struct qcom_cc_desc'
dt-bindings: clock: qcom: sm8450-camcc: Remove qcom,x1e80100-camcc leftover
clk: qcom: Add support for Video Clock Controller on QCS8300
clk: qcom: Add support for GPU Clock Controller on QCS8300
...
* clk-cleanup:
dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles
clk: davinci: remove support for da830
dt-bindings: clock: ti: Convert ti-clkctrl.txt to json-schema
clk: mmp: Fix NULL vs IS_ERR() check
clk: Print an error when clk registration fails
clk: Correct the data types of the variables in clk_calc_new_rates
clk: imgtec: use %pe for better readability of errors while printing
clk: stm32f4: fix an uninitialized variable
clk: keystone: syscon-clk: Do not use syscon helper to build regmap
Stephen Boyd [Mon, 24 Mar 2025 23:17:51 +0000 (16:17 -0700)]
Merge tag 'qcom-clk-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom
Pull Qualcomm clk driver updates from Bjorn Andersson:
- Support associating GDSCs with multiple power domains
- Add Qualcomm IPQ9574 NSS clk driver
- Add Qualcomm QCS8300 GPU and video clk drivers
- Add Qualcomm SDM429 RPM clks
- Add Qualcomm QCM6490 LPASS (low power audio) resets
- Fix halt check of voted branch clks
- Properly park Qualcomm SM8250 camera clks
- Add SDCC rests to Qualcomm SDM660
- Fix Qualcomm SM8750 regmap to skip protected registers
- Retain state for Qualcomm's SM8650 USB hardware when powered down
- Remove GPU AHB and dispaly XO clks from Qualcomm X Elite clk driver
- Update UART frequency table on Qualcomm IPQ5424 to fix flow control
- Allow Qualcomm IPQ5018 GCC driver to be compiled on arm32
* tag 'qcom-clk-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (41 commits)
clk: qcom: Add NSS clock Controller driver for IPQ9574
clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock
dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
clk: qcom: gcc-msm8953: fix stuck venus0_core0 clock
clk: qcom: mmcc-sdm660: fix stuck video_subcore0 clock
dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps
drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock
clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490
dt-bindings: clock: qcom: Add compatible for QCM6490 boards
clk: qcom: gdsc: Update the status poll timeout for GDSC
clk: qcom: gdsc: Set retain_ff before moving to HW CTRL
clk: qcom: gcc-sm8650: Do not turn off USB GDSCs during gdsc_disable()
clk: qcom: videocc: Constify 'struct qcom_cc_desc'
clk: qcom: gpucc: Constify 'struct qcom_cc_desc'
clk: qcom: dispcc: Constify 'struct qcom_cc_desc'
clk: qcom: camcc: Constify 'struct qcom_cc_desc'
dt-bindings: clock: qcom: sm8450-camcc: Remove qcom,x1e80100-camcc leftover
clk: qcom: Add support for Video Clock Controller on QCS8300
clk: qcom: Add support for GPU Clock Controller on QCS8300
...
Stephen Boyd [Tue, 18 Mar 2025 21:38:01 +0000 (14:38 -0700)]
Merge tag 'clk-meson-v6.15-1' of https://github.com/BayLibre/clk-meson into clk-amlogic
Pull Amlogic clk driver updates from Jerome Brunet:
- Fix mmc A clock gate definition on Amlogic g12 SoCs
- Properly set cpu cluster A on Amlogic g12b
- Fix 32k clock definition on Amlogic gxbb
- Correct documentation typo on Amlogic a1
* tag 'clk-meson-v6.15-1' of https://github.com/BayLibre/clk-meson:
clk: amlogic: a1: fix a typo
clk: amlogic: gxbb: drop non existing 32k clock parent
clk: amlogic: gxbb: drop incorrect flag on 32k clock
clk: amlogic: g12b: fix cluster A parent data
clk: amlogic: g12a: fix mmc A peripheral clock
This clock can't be enable with VENUS_CORE0 GDSC turned off. But that
GDSC is under HW control so it can be turned off at any moment.
Instead of checking the dependent clock we can just vote for it to
enable later when GDSC gets turned on.
Fixes: 9bb6cfc3c77e6 ("clk: qcom: Add Global Clock Controller driver for MSM8953") Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20250315-clock-fix-v1-2-2efdc4920dda@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This clock can't be enable with VENUS_CORE0 GDSC turned off. But that
GDSC is under HW control so it can be turned off at any moment.
Instead of checking the dependent clock we can just vote for it to
enable later when GDSC gets turned on.
dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps
The switch to multiple power domains implies that the required-opps
property shall be updated accordingly, a record in one property
corresponds to a record in another one.
Fixes: 7ec95ff9abf4 ("dt-bindings: clock: move qcom,x1e80100-camcc to its own file") Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20250304143152.1799966-1-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Jerome Brunet [Fri, 20 Dec 2024 10:25:37 +0000 (11:25 +0100)]
clk: amlogic: gxbb: drop non existing 32k clock parent
The 32k clock reference a parent 'cts_slow_oscin' with a fixme note saying
that this clock should be provided by AO controller.
The HW probably has this clock but it does not exist at the moment in
any controller implementation. Furthermore, referencing clock by the global
name should be avoided whenever possible.
There is no reason to keep this hack around, at least for now.
Jerome Brunet [Fri, 13 Dec 2024 14:30:17 +0000 (15:30 +0100)]
clk: amlogic: g12b: fix cluster A parent data
Several clocks used by both g12a and g12b use the g12a cpu A clock hw
pointer as clock parent. This is incorrect on g12b since the parents of
cluster A cpu clock are different. Also the hw clock provided as parent to
these children is not even registered clock on g12b.
Fix the problem by reverting to the global namespace and let CCF pick
the appropriate, as it is already done for other clocks, such as
cpu_clk_trace_div.
Jerome Brunet [Fri, 13 Dec 2024 10:03:23 +0000 (11:03 +0100)]
clk: amlogic: g12a: fix mmc A peripheral clock
The bit index of the peripheral clock for mmc A is wrong
This was probably not a problem for mmc A as the peripheral is likely left
enabled by the bootloader.
No issues has been reported so far but it could be a problem, most likely
some form of conflict between the ethernet and mmc A clock, breaking
ethernet on init.
Use the value provided by the documentation for mmc A before this
becomes an actual problem.
drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock
The divider values in the sdcc1_apps frequency table were incorrectly
updated, assuming the frequency of gpll2_out_main to be 1152MHz.
However, the frequency of the gpll2_out_main clock is actually 576MHz
(gpll2/2).
Due to these incorrect divider values, the sdcc1_apps clock is running
at half of the expected frequency.
Fixing the frequency table of sdcc1_apps allows the sdcc1_apps clock to
run according to the frequency plan.
Taniya Das [Fri, 21 Feb 2025 09:34:55 +0000 (15:04 +0530)]
clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490
On the QCM6490 boards, the LPASS firmware controls the complete clock
controller functionalities and associated power domains. However, only
the LPASS resets required to be controlled by the high level OS. Thus,
add support for the resets in the clock driver to enable the Audio SW
driver to assert/deassert the audio resets as needed.
Taniya Das [Fri, 21 Feb 2025 09:34:54 +0000 (15:04 +0530)]
dt-bindings: clock: qcom: Add compatible for QCM6490 boards
On the QCM6490 boards, the LPASS firmware controls the complete clock
controller functionalities and associated power domains. However, only
the LPASS resets required to be controlled by the high level OS. Thus,
add the new QCM6490 compatible to support the reset functionality for
Low Power Audio subsystem.
Taniya Das [Fri, 14 Feb 2025 04:27:00 +0000 (09:57 +0530)]
clk: qcom: gdsc: Update the status poll timeout for GDSC
During the GDSC FSM state, the GDSC hardware waits for an ACK from the
respective subsystem core. In some scenarios, this ACK can be delayed.
To handle such delays, increase the GDSC status poll timeout from 1500us
to 2000us as per the design recommendation.
Taniya Das [Fri, 14 Feb 2025 04:26:59 +0000 (09:56 +0530)]
clk: qcom: gdsc: Set retain_ff before moving to HW CTRL
Enable the retain_ff_enable bit of GDSCR only if the GDSC is already ON.
Once the GDSCR moves to HW control, SW no longer can determine the state
of the GDSCR and setting the retain_ff bit could destroy all the register
contents we intended to save.
Therefore, move the retain_ff configuration before switching the GDSC to
HW trigger mode.
Cc: stable@vger.kernel.org Fixes: 173722995cdb ("clk: qcom: gdsc: Add support to enable retention of GSDCR") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Imran Shaik <quic_imrashai@quicinc.com> Tested-by: Imran Shaik <quic_imrashai@quicinc.com> # on QCS8300 Link: https://lore.kernel.org/r/20250214-gdsc_fixes-v1-1-73e56d68a80f@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Stephen Boyd [Thu, 13 Mar 2025 20:23:09 +0000 (13:23 -0700)]
Merge tag 'sunxi-clk-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver updates from Chen-Yu Tsai:
- Extend Allwinner H616 clock driver to cover TCON clock and reset
- Enable Allwinner H616 GPU clock reparenting during rate change
- Add new clock driver for Allwinner's A523/T527
* tag 'sunxi-clk-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: add support for the A523/T527 PRCM CCU
clk: sunxi-ng: a523: add reset lines
clk: sunxi-ng: a523: add bus clock gates
clk: sunxi-ng: a523: remaining mod clocks
clk: sunxi-ng: a523: add USB mod clocks
clk: sunxi-ng: a523: add interface mod clocks
clk: sunxi-ng: a523: add system mod clocks
clk: sunxi-ng: a523: add video mod clocks
clk: sunxi-ng: a523: Add support for bus clocks
clk: sunxi-ng: Add support for the A523/T527 CCU PLLs
dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs
clk: sunxi-ng: Add support for update bit
clk: sunxi-ng: mp: provide wrappers for setting feature flags
clk: sunxi-ng: mp: introduce dual-divider clock
clk: sunxi-ng: h616: Reparent GPU clock during frequency changes
clk: sunxi-ng: h616: Add clock/reset for LCD TCON
dt-bindings: clock: sun50i-h616-ccu: Add LCD TCON clk and reset
This SoC has some leftover code all over the kernel but no boards are
supported anymore. Remove support for da830 from the davinci clock
driver. With it: remove the ifdefs around the data structures as the
da850 remains the only davinci SoC supported and the only user of this
driver.
Andreas Kemnade [Tue, 11 Mar 2025 18:02:15 +0000 (19:02 +0100)]
dt-bindings: clock: ti: Convert ti-clkctrl.txt to json-schema
Convert the TI clkctrl clock device tree binding to json-schema.
Specify the creator of the original binding as a maintainer.
reg property is used mostly with one item, in am3xxx also with
an arbitrary number of items, so divert from the original binding
specifying two (probably meaning one address and one size).
The consumer part of the example is left out because the full consumer
node would be needed.
Andre Przywara [Fri, 7 Mar 2025 00:26:28 +0000 (00:26 +0000)]
clk: sunxi-ng: add support for the A523/T527 PRCM CCU
The A523/T527 SoCs have clock/reset controls in the PRCM part, like many
previous SoCs. For a change, the whole PRCM is documented in the A523
manual, including the system bus tree, so we can describe all those
clocks correctly based on that. There layout seems to be derived from
the H6 and H616 PRCM CCUs, though there are more clocks, and many clocks
have subtly changed.
Describe all the mod and gate clocks, including the three bus clocks
(R_AHB, R_APB0, and R_APB1).
Andre Przywara [Fri, 7 Mar 2025 00:26:27 +0000 (00:26 +0000)]
clk: sunxi-ng: a523: add reset lines
Allwinner SoCs do not contain a separate reset controller, instead the
reset lines for the various devices are integrated into the "BGR" (Bus
Gate / Reset) registers, for each device group: one for all UARTs, one
for all SPI interfaces, and so on.
The Allwinner CCU driver also doubles as a reset provider, and since the
reset lines are indeed just single bits in those BGR register, we can
represent them easily in an array of structs, just containing the
register offset and the bit number.
Add the location of the reset bits for all devices in the A523/T527
SoCs, using the existing sunxi CCU infrastructure.
Andre Przywara [Fri, 7 Mar 2025 00:26:26 +0000 (00:26 +0000)]
clk: sunxi-ng: a523: add bus clock gates
Add the various bus clock gates that control access to the devices'
register interface.
These clocks are each just one bit, typically the lower bits in some "BGR"
(Bus Gate / Reset) registers, for each device group: one for all UARTs,
one for all SPI interfaces, and so on.
Andre Przywara [Fri, 7 Mar 2025 00:26:25 +0000 (00:26 +0000)]
clk: sunxi-ng: a523: remaining mod clocks
Add the remaining mod clocks, driving various parts of the SoC: the "LEDC"
LED controller, the "CSI" camera interface, the "ISP" image processor,
the DSP clock, and the "fanout" clocks, which allow to put clock signals
on external pins.
Andre Przywara [Fri, 7 Mar 2025 00:26:24 +0000 (00:26 +0000)]
clk: sunxi-ng: a523: add USB mod clocks
Add the clocks driving the USB subsystem: this just covers the two
clocks creating the 12 MHz rate for the OHCI (USB 1.x) device. The rest
of the USB clocks are either gate clocks (added later) or created
internal to the USB IP.
Andre Przywara [Fri, 7 Mar 2025 00:26:23 +0000 (00:26 +0000)]
clk: sunxi-ng: a523: add interface mod clocks
Add the clocks driving what the user manual summarises under "interface"
devices: raw NAND flash, MMC, SPI, EMAC, "IR" infrared, and the "GPADC"
general purpose analogue/digital converter.
Andre Przywara [Fri, 7 Mar 2025 00:26:22 +0000 (00:26 +0000)]
clk: sunxi-ng: a523: add system mod clocks
Add the clocks driving some core system related subsystems of the SoC:
the "CE" crypto engine, the high speed timers, the DRAM and the associated
MBUS clock, and the PCIe clock.
Andre Przywara [Fri, 7 Mar 2025 00:26:21 +0000 (00:26 +0000)]
clk: sunxi-ng: a523: add video mod clocks
Add the clocks driving the various video subsystems of the SoC: the "DE"
display engine, the "DI" deinterlacer, the "G2D" 2D graphics system, the
Mali "GPU", the "VE" video engine, its associated IOMMU, as well as the
clocks for the various video output drivers (HDMI, DP, LCDs).
Andre Przywara [Fri, 7 Mar 2025 00:26:20 +0000 (00:26 +0000)]
clk: sunxi-ng: a523: Add support for bus clocks
Add the basic bus clocks for the Allwinner A523 and T527 SoCs.
This covers the AHB, APB0 and APB1 clocks. Linux is not supposed to
change those clocks, but they are needed as parents for many other mod
clocks.
Andre Przywara [Fri, 7 Mar 2025 00:26:19 +0000 (00:26 +0000)]
clk: sunxi-ng: Add support for the A523/T527 CCU PLLs
Add the PLL clocks of the main CCU of the Allwinner A523 and T527 SoCs.
The clocks were modelled after the A523 and T527 manual, and double
checked by writing all 1's into the respective register, to spot all
implemented bits.
The PLL and mod clocks for the two CPU clusters and the DSU are part of
a separate CCU, also most audio clocks are collected in a DSP CCU, so
both of these clock groups are missing from this driver.
Andre Przywara [Fri, 7 Mar 2025 00:26:18 +0000 (00:26 +0000)]
dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs
The Allwinner A523/T527 SoCs have four CCUs, this adds the binding for
the main and the PRCM R-CCU.
The source clock list differs in some annoying details, and folding this
into the existing Allwinner CCU clock binding document gets quite
unwieldy, so create a new document for these CCUs.
Add the new compatible string, along with the required input clock
lists. This conditionally describes the input clock lists, to make
adding support for the other two CCUs easier.
Also add the DT binding headers, listing all the clocks with their ID
numbers.
Andre Przywara [Fri, 7 Mar 2025 00:26:17 +0000 (00:26 +0000)]
clk: sunxi-ng: Add support for update bit
Some clocks in the Allwinner A523 SoC contain an "update bit" (bit 27),
which must be set to apply any register changes, namely the mux
selector, the divider and the gate bit.
Add a new CCU feature bit to mark those clocks, and set bit 27 whenever
we are applying any changes.
Andre Przywara [Fri, 7 Mar 2025 00:26:16 +0000 (00:26 +0000)]
clk: sunxi-ng: mp: provide wrappers for setting feature flags
So far our sunxi clock instantiation macros set the required clock
features depending on the clock type, but the new "dual divider MP
clock" requires us to pass that piece of information in by the user.
Add new wrapper macros that allow to specify a "features" field, to
allow marking those dual-divider clocks accordingly. Also add two
convenience macros that deal with the most common cases.
Andre Przywara [Fri, 7 Mar 2025 00:26:15 +0000 (00:26 +0000)]
clk: sunxi-ng: mp: introduce dual-divider clock
The Allwinner A523 SoC introduces some new MP-style mod clock, where the
second "P" divider is an actual numerical divider value, and not the
numbers of bits to shift (1..32 instead of 1,2,4,8).
The rest of the clock is the same as the existing MP clock, so enhance the
existing code to accommodate for this.
Introduce the new CCU feature bit CCU_FEATURE_DUAL_DIV to mark an MP
clock as having two dividers, and change the dividing and encoding code
to differentiate the two cases.
Stephen Boyd [Tue, 11 Mar 2025 18:14:21 +0000 (11:14 -0700)]
Merge tag 'clk-imx-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clk driver updates from Abel Vesa:
- Add missing AXI clock to the i.MX8MP AUDIOMIX in dt-bindings schema
- Fix DSP and OCRAM_A parent clocks in i.MX8MP AUDIOMIX clock provider
- Document vendor specific operating-mode property in i.MX8M clock
provider dt-bindings schema
- Apply overdrive/nominal constraints based on DT property in i.MX8MP
clock provider
* tag 'clk-imx-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
clk: imx8mp: inform CCF of maximum frequency of clocks
dt-bindings: clock: imx8m: document nominal/overdrive properties
clk: clk-imx8mp-audiomix: fix dsp/ocram_a clock parents
dt-bindings: clock: imx8mp: add axi clock
Stephen Boyd [Tue, 11 Mar 2025 18:06:52 +0000 (11:06 -0700)]
Merge tag 'samsung-clk-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung clk driver updates from Krzysztof Kozlowski:
- Samsung Exynos990: Add support for the PERIS clock controller in existing
driver
- Samsung Exynos2200: Add new driver for several clock controllers (Alive,
CMGP, HSI, PERIC/PERIS, TOP, UFS and VFS)
- Samsung Exynos7870: Add new driver for several clock controllers (Alive,
MIF, DISP AUD, FSYS, G3D, ISP, MFC and PERI)
- Correct undefined behavior / runtime array bounds check of flexible
array member (last 'hws' element in 'struct clk_hw_onecell_data').
The code was logically correct for normal case, but not for the
clang/GCC runtime bounds checking of flexible array member.
- Spelling and header inclusion cleanups
* tag 'samsung-clk-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
clk: samsung: Drop unused clk.h and of.h headers
clk: samsung: Add missing mod_devicetable.h header
clk: samsung: add initial exynos7870 clock driver
clk: samsung: introduce Exynos2200 clock driver
clk: samsung: clk-pll: add support for pll_4311
dt-bindings: clock: add clock definitions and documentation for exynos7870 CMU
dt-bindings: clock: add Exynos2200 SoC
clk: samsung: Fix UBSAN panic in samsung_clk_init()
clk: samsung: Fix spelling mistake "stablization" -> "stabilization"
clk: samsung: exynos990: Add CMU_PERIS block
dt-bindings: clock: exynos990: Add CMU_PERIS block
Stephen Boyd [Tue, 11 Mar 2025 17:56:09 +0000 (10:56 -0700)]
Merge tag 'v6.15-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
- New clock controller drivers for Rockchip rk3528 and rk3562
- Fix a parent for Rockchip rk3328 clk_ref_usb3otg
- Add camera interface clocks for Rockchip rk3188
* tag 'v6.15-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: Add clock controller for the RK3562
dt-bindings: clock: Add RK3562 cru
clk: rockchip: rk3528: Add reset lookup table
clk: rockchip: Add clock controller driver for RK3528 SoC
clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE
dt-bindings: clock: Document clock and reset unit of RK3528
clk: rockchip: rk3328: fix wrong clk_ref_usb3otg parent
clk: rockchip: rk3568: mark hclk_vi as critical
clk: rockchip: rk3188: use PCLK_CIF0/1 clock IDs on RK3066
dt-bindings: clock: rk3188-common: add PCLK_CIF0/PCLK_CIF1
Stephen Boyd [Fri, 7 Mar 2025 23:34:59 +0000 (15:34 -0800)]
Merge tag 'renesas-clk-for-v6.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull more Renesas clk driver updates from Geert Uytterhoeven:
- Add DMA clocks and reset on Renesas RZ/V2H
- Add thermal (TSU) clock and reset on Renesas RZ/G3E
* tag 'renesas-clk-for-v6.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP
clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1
clk: renesas: r7s9210: Distinguish clocks by clock type
clk: renesas: rzg2l: Remove unneeded nullify checks
clk: renesas: cpg-mssr: Remove obsolete nullify check
clk: renesas: r9a09g057: Add entries for the DMACs
<clk.h> header is for clock consumers, so drop its include from the
Samsung clock controller drivers which do not use the consumer API
(there are few which do, so leave it there).
Drop including of <of.h> and <of_address.h> headers for all drivers
which do not use anything from generic OF API or of_iomap().
Neil Armstrong [Wed, 5 Mar 2025 19:00:29 +0000 (20:00 +0100)]
clk: qcom: gcc-sm8650: Do not turn off USB GDSCs during gdsc_disable()
With PWRSTS_OFF_ON, USB GDSCs are turned off during gdsc_disable(). This
can happen during scenarios such as system suspend and breaks the resume
of USB controller from suspend.
So use PWRSTS_RET_ON to indicate the GDSC driver to not turn off the GDSCs
during gdsc_disable() and allow the hardware to transition the GDSCs to
retention when the parent domain enters low power state during system
suspend.
Stephen Boyd [Wed, 26 Feb 2025 23:54:07 +0000 (15:54 -0800)]
clk: Print an error when clk registration fails
We have a lot of driver code that prints an error message when
registering a clk fails. Do that in the core function instead to
consolidate code. This also helps drivers avoid the anti-pattern of
accessing the struct clk_hw::init pointer after registration.
Chuan Liu [Fri, 7 Feb 2025 09:36:10 +0000 (17:36 +0800)]
clk: Correct the data types of the variables in clk_calc_new_rates
In clk_calc_new_rates, the "ret" is only used to store the return value
of clk_core_determine_round_nolock, and the data type of the return
value of clk_core_determine_round_nolock is int.
Dario Binacchi [Fri, 24 Jan 2025 11:16:54 +0000 (12:16 +0100)]
clk: stm32f4: fix an uninitialized variable
The variable s, used by pr_debug() to print the mnemonic of the modulation
depth in use, was not initialized. Fix the output by addressing the correct
mnemonic.
Fixes: 65b3516dbe50 ("clk: stm32f4: support spread spectrum clock generation") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/r/77355eb9-19b3-46e5-a003-c21c0fae5bcd@stanley.mountain Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20250124111711.1051436-1-dario.binacchi@amarulasolutions.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Andrew Davis [Thu, 23 Jan 2025 18:19:13 +0000 (12:19 -0600)]
clk: keystone: syscon-clk: Do not use syscon helper to build regmap
The syscon helper device_node_to_regmap() is used to fetch a regmap
registered to a device node. It also currently creates this regmap
if the node did not already have a regmap associated with it. This
should only be used on "syscon" nodes. This driver is not such a
device and instead uses device_node_to_regmap() on its own node as
a hacky way to create a regmap for itself.
This will not work going forward and so we should create our regmap
the normal way by defining our regmap_config, fetching our memory
resource, then using the normal regmap_init_mmio() function.
Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250123181913.597304-1-afd@ti.com Tested-by: Nishanth Menon <nm@ti.com>
[sboyd@kernel.org: Drop dev_err_probe() because the mapping function
already does it] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
clk: renesas: r7s9210: Distinguish clocks by clock type
When registering a clock, its type should be devised from the clock's
type member, not from its id member.
Merge the two checks for the main clock, to improve readability.
All core clock nullify users and helpers were removed in commit b1dec4e78599a2ce ("clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*"),
but the CPG/MSSR driver still checks for nullified core clocks.
Remove the obsolete check.
Ahmad Fatoum [Tue, 18 Feb 2025 18:26:46 +0000 (19:26 +0100)]
clk: imx8mp: inform CCF of maximum frequency of clocks
The IMX8MPCEC datasheet lists maximum frequencies allowed for different
modules. Some of these limits are universal, but some depend on
whether the SoC is operating in nominal or in overdrive mode.
The imx8mp.dtsi currently assumes overdrive mode and configures some
clocks in accordance with this. Boards wishing to make use of nominal
mode will need to override some of the clock rates manually.
As operating the clocks outside of their allowed range can lead to
difficult to debug issues, it makes sense to register the maximum rates
allowed in the driver, so the CCF can take them into account.
The imx8m-clock.yaml binding covers the clock controller inside all
of the i.MX8M Q/M/N/P SoCs. All of them have in common that they
support two operating modes: nominal and overdrive mode.
While the overdrive mode allows for higher frequencies for many IPs,
the nominal mode needs a lower SoC voltage, thereby reducing
heat generation and power usage.
As increasing clock rates beyond the maximum permitted by the supplied
SoC voltage can lead to difficult to debug issues, device tree consumers
would benefit from knowing what mode is active to enforce the clock rate
limits that come with it.
To facilitate this, extend the clock controller bindings with an
optional fsl,operating-mode property. This intentionally allows the
absence of the property, because there is no default suitable for all
boards:
For i.MX8M Mini and Nano, the kernel SoC DTSIs has assigned-clock-rates
that are all achievable in nominal mode. For i.MX8MP, there are some
rates only validated for overdrive mode.
But even for the i.MX8M Mini/Nano boards, we don't know what rates they
may configure at runtime, so it has not been possible so far to infer from
just the device tree what the mode is.
Some components of AUDIOMIX (i.e: DSP, OCRAM_A) are clocked by
AUDIO_AXI_CLK_ROOT. Since the AUDIOMIX block control manages the clock
gates for those components, include their root clock in the list of clocks
consumed by the IP.
Fixes: 95a0aa7bb10e ("dt-bindings: clock: imx8mp: Add audiomix block control") Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com> Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20250226164513.33822-2-laurentiumihalcea111@gmail.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
This is a basic implementation of the clock driver required by
Samsung's Exynos7870 SoC. It implements CMU_MIF, CMU_DISPAUD, CMU_FSYS,
CMU_G3D, CMU_ISP, CMU_MFCMSCL, and CMU_PERI. all other CMUs depend on
CMU_MIF.
Ivaylo Ivanov [Sun, 23 Feb 2025 11:56:00 +0000 (13:56 +0200)]
clk: samsung: introduce Exynos2200 clock driver
CMU_TOP is the top level clock management unit which contains PLLs,
muxes, dividers and gates that feed the other clock management units.
CMU_ALIVE provides clocks for SPMI, the new MCT and other clock
management units
CMU_CMGP provides clocks for USI blocks
CMU_HSI0 provides clocks for USB
CMU_PERIC0 provides clocks for USI4 and I3C blocks
CMU_PERIC1 provides clocks for USI blocks
CMU_PERIC2 provides clocks for USI and I3C blocks
CMU_PERIS provides clocks for GIC and the legacy MCT
CMU_UFS provides clocks for UFS
CMU_VTS provides clocks for other clock management units
like CMU_AUD, which will be added in the future.
Ivaylo Ivanov [Sun, 23 Feb 2025 11:55:59 +0000 (13:55 +0200)]
clk: samsung: clk-pll: add support for pll_4311
pll4311 (also known in the vendor kernel as frd_4311_rpll) is a PLL used
in the Exynos2200 SoC. It's an integer/fractional PLL with mid frequency
FVCO (650 to 3500Mhz).
The PLL is functionally similar enough to pll531x, so the same code can
handle both.
Locktime for pll4311 is 500 - the same as the pll531x lock factor. MDIV,
PDIV, SDIV and FDIV masks and bit shifts are also the same as pll531x.
When defining a PLL, the "con" parameter should be set to CON3
register, like this:
dt-bindings: clock: add clock definitions and documentation for exynos7870 CMU
Add unique identifiers for exynos7870 clocks for every bank. It adds all
clocks of CMU_MIF, CMU_DISPAUD, CMU_G3D, CMU_ISP, CMU_MFCMSCL, and
CMU_PERI. Document the devicetree bindings as well.
Friday Yang [Fri, 21 Feb 2025 07:50:53 +0000 (15:50 +0800)]
dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188
On the MediaTek platform, some SMI LARBs are directly connected to
the SMI Common, while others are connected to the SMI Sub-Common,
which in turn is connected to the SMI Common. The hardware block
diagram can be described as follows.
For previous discussion on the direction of the code modifications,
please refer to:
https://lore.kernel.org/all/CAFGrd9qZhObQXvm2_abqaX83xMLqxjQETB2=
wXpobDWU1CnvkA@mail.gmail.com/
https://lore.kernel.org/all/CAPDyKFpokXV2gJDgowbixTvOH_5VL3B5H8ey
hP+KJ5Fasm2rFg@mail.gmail.com/
On the MediaTek MT8188 SoC platform, we encountered power-off failures
and SMI bus hang issues during camera stress tests. The issue arises
because bus glitches are sometimes produced when MTCMOS powers on or
off. While this is fairly normal, the software must handle these
glitches to avoid mistaking them for transaction signals. What's
more, this issue emerged only after the initial upstreaming of this
binding. Without these patches, the SMI becomes unstable during camera
stress tests.
The software solutions can be summarized as follows:
1. Use CLAMP to disable the SMI sub-common port after turning off the
LARB CG and before turning off the LARB MTCMOS.
2. Use CLAMP to disable/enable the SMI sub-common port.
3. Implement an AXI reset for SMI LARBs.
This patch add '#reset-cells' for the clock controller located in image,
camera and IPE subsystems.
Signed-off-by: Friday Yang <friday.yang@mediatek.com> Link: https://lore.kernel.org/r/20250221075058.14180-2-friday.yang@mediatek.com Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Jonas Karlman [Thu, 27 Feb 2025 17:52:57 +0000 (17:52 +0000)]
clk: rockchip: rk3528: Add reset lookup table
In the commit 5d0eb375e685 ("clk: rockchip: Add clock controller driver
for RK3528 SoC") only the dt-binding header was added for the reset
controller for the RK3528 SoC.
Add a reset lookup table generated from the SRST symbols used by vendor
linux-6.1-stan-rkr5 kernel to complete support for the reset controller.
Stephen Boyd [Wed, 26 Feb 2025 22:33:45 +0000 (14:33 -0800)]
Merge tag 'renesas-clk-for-v6.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add thermal (TSU) clock, reset, and power domain on Renesas RZ/G3S
- Add AI accelerator (DRP-AI) clocks and reset on Renesas RZ/V2L
- Add Image Signal Processor (ISP, FCPVX, VSPX) clocks on Renesas R-Car V3U
V4H, and V4M
- Add Watchdog (WDT), SDHI, Interrupt Controller (ICU), Camera (CRU0)
and CAN-FD clocks and resets on Renesas RZ/G3E
* tag 'renesas-clk-for-v6.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: r9a09g047: Add CANFD clocks and resets
clk: renesas: r9a09g047: Add CRU0 clocks and resets
clk: renesas: rzv2h: Update error message
clk: renesas: rzg2l: Update error message
clk: renesas: r9a09g047: Add ICU clock/reset
clk: renesas: r9a07g043: Fix HP clock source for RZ/Five
clk: renesas: r9a09g047: Add SDHI clocks/resets
clk: renesas: r8a779h0: Add VSPX clock
clk: renesas: r8a779h0: Add FCPVX clock
clk: renesas: r8a08g045: Check the source of the CPU PLL settings
clk: renesas: r9a09g047: Add WDT clocks and resets
clk: renesas: r8a779h0: Add ISP core clocks
clk: renesas: r8a779g0: Add ISP core clocks
clk: renesas: r8a779a0: Add ISP core clocks
clk: renesas: r8a779a0: Add FCPVX clocks
clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI
clk: renesas: r9a08g045: Add clocks, resets and power domain support for the TSU IP
clk: renesas: rzg2l-cpg: Refactor Runtime PM clock validation
Heiko Stuebner [Sat, 22 Feb 2025 22:37:33 +0000 (23:37 +0100)]
clk: check for disabled clock-provider in of_clk_get_hw_from_clkspec()
of_clk_get_hw_from_clkspec() checks all available clock-providers by
comparing their of nodes to the one from the clkspec. If no matching
clock provider is found, the function returns -EPROBE_DEFER to cause a
re-check at a later date. If a matching clock provider is found, an
authoritative answer can be retrieved from it whether the clock exists
or not.
This does not take into account that the clock-provider may never
appear, because it's node is disabled. This can happen when a clock is
optional, provided by a separate block which never gets enabled.
One example of this happening is the rk3588's VOP, which has optional
additional display clocks coming from PLLs inside the hdmiphy blocks.
These can be used for better rates, but the system will also work
without them.
The problem around that is described in the followups to[1]. As we
already know the of node of the presumed clock provider, add a check via
of_device_is_available() whether this is a "valid" device node. This
prevents eternal defer loops.
Yao Zi [Mon, 17 Feb 2025 06:11:44 +0000 (06:11 +0000)]
clk: rockchip: Add clock controller driver for RK3528 SoC
Add clock tree definition for RK3528. Similar to previous Rockchip
SoCs, clock controller of RK3528 is combined with the reset controller.
We omit the reset part for now since it's hard to test it without
support for other basic peripherals.
Yao Zi [Mon, 17 Feb 2025 06:11:43 +0000 (06:11 +0000)]
clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE
RK3528 comes with a new PLL variant: its "PPLL", which mainly generates
clocks for the PCIe controller, operates in normal mode only. Let's
describe it with flag ROCKCHIP_PLL_FIXED_MODE and handle it in code.
Yao Zi [Mon, 17 Feb 2025 06:11:42 +0000 (06:11 +0000)]
dt-bindings: clock: Document clock and reset unit of RK3528
There are two types of clocks in RK3528 SoC, CRU-managed and
SCMI-managed. Independent IDs are assigned to them.
For the reset part, differing from previous Rockchip SoCs and
downstream bindings which embeds register offsets into the IDs, gapless
numbers starting from zero are used.
Correct the clk_ref_usb3otg parent to fix clock control for the usb3
controller on rk3328. Verified against the rk3328 trm, the rk3228h trm,
and the rk3328 usb3 phy clock map.
Michael Riesch [Mon, 10 Feb 2025 08:29:02 +0000 (09:29 +0100)]
clk: rockchip: rk3568: mark hclk_vi as critical
The clock 'pclk_vi_niu' has a dependency on 'hclk_vi_niu' according
to the Technical Reference Manual section '2.8.6 NIU Clock gating
reliance'. However, this kind of dependency cannot be addressed
properly at the moment (until the support for linked clocks is
implemented for the RK3568).
As an intermediate solution, mark the hclk_vi as critical on the
Rockchip RK3568.
Philippe Simons [Thu, 20 Feb 2025 11:38:08 +0000 (12:38 +0100)]
clk: sunxi-ng: h616: Reparent GPU clock during frequency changes
The H616 manual does not state that the GPU PLL supports
dynamic frequency configuration, so we must take extra care when changing
the frequency. Currently any attempt to do device DVFS on the GPU lead
to panfrost various ooops, and GPU hangs.
The manual describes the algorithm for changing the PLL
frequency, which the CPU PLL notifier code already support, so we reuse
that to reparent the GPU clock to GPU1 clock during frequency
changes.
Chris Morgan [Thu, 13 Feb 2025 17:22:48 +0000 (11:22 -0600)]
clk: sunxi-ng: h616: Add clock/reset for LCD TCON
Add the required clock and reset which is used for the LCD TCON. Please
note that these clocks are exposed on the T507, H616, and H700; however
the H616 does not expose an LCD controller for which these clocks are
needed.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Ryan Walklin <ryan@testtoast.com> Link: https://patch.msgid.link/20250213172248.158447-3-macroalpha82@gmail.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Lad Prabhakar [Tue, 11 Feb 2025 10:56:03 +0000 (10:56 +0000)]
clk: renesas: rzv2h: Update error message
Update the error message in `rzv2h_mod_clock_endisable()` to provide
clearer debugging information. Instead of printing only the register
address, include both the `GET_CLK_ON_OFFSET(reg)` offset and the
corresponding `clk` name (`%pC`). This enhances readability and aids
in debugging clock enable failures.
Lad Prabhakar [Tue, 11 Feb 2025 10:56:02 +0000 (10:56 +0000)]
clk: renesas: rzg2l: Update error message
Update the error message in `rzg2l_mod_clock_endisable()` to provide
clearer debugging information. Instead of printing only the register
address, include both the `CLK_ON_R(reg)` offset and the corresponding
`clk` name (`%pC`). This enhances readability and aids in debugging
clock enable failures.
projects / thirdparty / kernel / linux.git / log
