Alan Modra [Mon, 22 Dec 2014 00:15:13 +0000 (10:45 +1030)]
Move support code for linker script DEFINED to ldexp.c
This moves support code for DEFINED to ldexp.c where it is used,
losing the lang_ prefix on identifiers. Two new functions are needed
to initialize and clean up to hash table, but other than that there
are no functional changes here.
Alan Modra [Fri, 12 Dec 2014 05:32:34 +0000 (16:02 +1030)]
PowerPC register numbers in DWARF
This makes gas .cfi output to .debug_frame match register numbering
emitted by gcc. md_reg_eh_frame_to_debug_frame follows the ABI,
targets not using it, notably Linux, don't.
* config/tc-ppc.h (md_reg_eh_frame_to_debug_frame): Match current
gcc behaviour.
* config/te-aix.h: New file.
* configure.tgt: Use em=aix for powerpc-aix.
Alan Modra [Fri, 12 Dec 2014 12:23:46 +0000 (22:53 +1030)]
Copy relocations against protected symbols
Copy relocs are used in a scheme to avoid dynamic text relocations in
non-PIC executables that refer to variables defined in shared
libraries. The idea is to have the linker define any such variable in
the executable, with a copy reloc copying the initial value, then have
both the executable and shared library refer to the executable copy.
If the shared library defines the variable as protected then we have
two copies of the variable being used.
Alan Modra [Thu, 11 Dec 2014 05:32:35 +0000 (16:02 +1030)]
Use autoconf check for long long in binutils
* configure.ac: Check for long long and sizes of long long and long.
* elfcomm.h (HOST_WIDEST_INT): Test HAVE_LONG_LONG in place of
__STDC_VERSION__ and __GNUC__.
* strings.c (print_strings): Likewise.
* dwarf.c (DWARF_VMA_FMT, DWARF_VMA_FMT_LONG): Likewise.
* configure: Regenerate.
* config.in: Regenerate.
Alan Modra [Tue, 9 Dec 2014 23:21:56 +0000 (09:51 +1030)]
Don't return DW_AT_name for function name in C++
DW_AT_name for functions typically just contains the base function
name, so lacks namespace, class and parameter information. It would
be possible to extract all these from the DWARF, but at a considerable
complication of the parser in dwarf2.c, and then you'd need to mangle
it all together. Much simpler is to look up the actual symbol. This
patch does that, avoiding the extra symbol lookup when the language
doesn't do name mangling.
PR 17541
* dwarf2.c (struct comp_unit): Add "lang".
(non_mangled): New function.
(struct funcinfo): Add "is_linkage". Reorder for better packing.
Make "name" a const char*.
(lookup_address_in_function_table): Delete functionname_ptr param.
(find_abstract_instance_name): Add is_linkage param. Set if we
have DW_AT_linkage_name or non_mangled DW_AT_name.
(scan_unit_for_symbols): Similarly set func->is_linkage.
(parse_comp_unit): Stash DW_AT_language.
(comp_unit_find_nearest_line): Replace functionname_ptr param
with function_ptr param.
(_bfd_dwarf2_find_nearest_line): Adjust above calls. Set
functionname_ptr from function->name. Call _bfd_elf_find_function
to retrieve symbol for function if not linkage name.
(_bfd_elf_find_function): Add bfd_target_elf_flavour test, moved from..
* elf.c (elf_find_function): ..here.
(_bfd_elf_find_nearest_line): Adjust calls.
* elf-bfd.h (_bfd_elf_find_function): Declare.
Alan Modra [Tue, 9 Dec 2014 04:02:22 +0000 (14:32 +1030)]
Don't sort ld -r relocs for mips
HI16/LO16 are deliberately put adjacent, which might mean relocs are
then not sorted by r_offset. See tc-mips.c:mips_frob_file. Don't undo
the HI16/LO16 sorting.
Alan Modra [Tue, 2 Dec 2014 04:39:16 +0000 (15:09 +1030)]
ppc64_elf_edit_opd revamp
This patch sorts .opd relocs (see pr17666) and allows .opd sections
with a mix of 16 and 24 byte entries to be edited.
* elf64-ppc.c (OPD_NDX): Define. Use throughout for sizing/indexing
_opd_sec_data array, halving required memory.
(sort_r_offset): New function.
(ppc64_elf_edit_opd): Sort incoming relocs. Accept .opd
sections with a mix of 16 and 24 byte OPD entries. Don't
attempt to honour --non-overlapping-opd for .opd sections with
unexpected relocs. Simplify opd entry size calculations by
first finding the reloc for the next entry. Make edit loop
handle one opd entry per iteration, with an inner loop
handling relocs per entry.
H.J. Lu [Sun, 11 Jan 2015 16:04:27 +0000 (08:04 -0800)]
Only discard space for pc-relative relocs symbols
When building PIE, we should only discard space for pc-relative relocs
symbols which turn out to need copy relocs.
bfd/
PR ld/17827
* elf64-x86-64.c (elf_x86_64_allocate_dynrelocs): For PIE,
only discard space for pc-relative relocs symbols which turn
out to need copy relocs.
Matthew Wahab [Tue, 12 Jan 2016 16:35:30 +0000 (16:35 +0000)]
[ARM] Support ARMv8.2 RAS extension.
The ARMv8.2 architecture includes the RAS extension which adds an
instruction, ESB, and a number of coprocessor registers. This patch adds
the instruction to binutils, making it available when -march=armv8.2-a
is selected. It also adds tests for the instruction and for the
coprocessor registers.
gas/
2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Fri, 11 Dec 2015 10:22:40 +0000 (10:22 +0000)]
[AArch64][Patch 5/5] Add instruction PSB CSYNC
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds the instruction to
binutils as a HINT alias that takes an operand.
A new operand type, AARCH64_OPND_BARRIER_PSB, is added to represent the
operand to PSB. A parser for the operand type is added to the assembler
and a printer to the disassembler. The operand name "csync" is added to
the list of HINT options with HINT number #17. Encoding and decoding of
the operand is handled by the ins_hint/ext_hint functions added in the
preceding patches.
gas/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_hint_opt_hsh): New.
(parse_barrier_psb): New.
(parse_operands): Add case for AARCH64_OPND_BARRIER_PSB.
(md_begin): Set up aarch64_hint_opt_hsh.
gas/testsuite/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/system-2.d: Enable the statistical profiling
extension. Update the expected output.
* gas/aarch64/system-2.s: Add tests for PSB CSYNC.
* gas/aarch64/system.d: Update the expected output.
include/opcode/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Fri, 11 Dec 2015 10:11:27 +0000 (10:11 +0000)]
[AArch64][Patch 4/5] Support HINT aliases taking operands.
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. This patch adds support for aliases
of HINT which take an operand, adding a table to store operand names and
their matching hint number as well as encoding and decoding functions
for such operands. Parsing and printing the operands are deferred to any
support added for aliases with such operands.
include/opcode/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_hint_options): Declare.
(aarch64_opnd_info): Add field hint_option.
opcodes/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Fri, 11 Dec 2015 09:56:07 +0000 (09:56 +0000)]
[AArch64][Patch 3/5] Adjust maximum number of instruction aliases.
The Statistical Profile Extension adds the instruction PSB CSYNC as an
alias for the HINT #17 instruction. The HINT instruction currently has 8
aliases, which is the maximum number allowed. This patch raises to 16
the limit on the number of aliases an instruction can have.
opcodes/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
Matthew Wahab [Fri, 11 Dec 2015 09:52:11 +0000 (09:52 +0000)]
[AArch64][Patch 2/5] Add Statistical Profiling Extension system registers.
The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers. This patch adds the registers to
binutils, making them available when the architecture extension
"+profile" is enabled.
opcodes/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
pmscr_el2.
(aarch64_sys_reg_supported_p): Add architecture feature tests for
the new registers.
gas/testsuite/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.s: Add tests for the statistical profiling
system registers.
* gas/aarch64/sysreg-2.d: Enable the statistical profiling
extension and update the expected output.
Matthew Wahab [Fri, 11 Dec 2015 09:30:26 +0000 (09:30 +0000)]
[AArch64][Patch 1/5] Support the ARMv8.2 Statistical Profiling Extension.
The Statistical Profile extension included in the ARMv8.2 architecture
adds a number of system registers and a new instruction. This patch set
adds support for the extension to binutils, enabled when
-march=armv8.2-a+profile is given.
The patches in this series:
- Add the new command line option and feature flags.
- Add the new system registers.
- Adjust the maximum number of aliases permitted for an instruction.
- Add support for HINT aliases which take operands.
- Add the new instruction, an alias of the HINT instruction.
This patch adds the option "profile" to the permitted architecture
extensions, disabling it by default.
gas/
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Thu, 10 Dec 2015 16:58:51 +0000 (16:58 +0000)]
[Aarch64] Support ARMv8.2 AT instructions
ARMv8.2 adds new instructions AT S1E1RP and AT S1E1WP to Aarch64. This
patch adds support for the instructions, making them available when
-march=armv8.2-a is selected.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and
AT S1E1WP.
* gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
(aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
feature test for "s1e1rp" and "s1e1wp".
Matthew Wahab [Thu, 10 Dec 2015 16:31:35 +0000 (16:31 +0000)]
[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.
ARMv8.2 adds the new system instruction DC CVAP. This patch series adds
support for this instruction to binutils, enabled when -march=armv8.2-a
is selected.
The AArch64 binutils record of some system registers uses a boolean
value to hold the single flag currently supported for them. To allow
these registers to be limited to specific architectures, the first patch
in this series replaces the boolean flag with a bitset and feature test.
include/opcode/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
(aarch64_sys_ins_reg_has_xt): Declare.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
with aarch64_sys_ins_reg_has_xt.
(aarch64_ext_sysins_op): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): Likewise.
(F_HASXT): New.
(aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
(aarch64_sys_regs_dc): Likewise.
(aarch64_sys_regs_at): Likewise.
(aarch64_sys_regs_tlbi): Likewise.
(aarch64_sys_ins_reg_has_xt): New.
Matthew Wahab [Thu, 10 Dec 2015 16:01:29 +0000 (16:01 +0000)]
[AArch64][binutils] Add support for ARMv8.2 PSTATE.UAO.
ARMv8.2 adds a new control bit PSTATE.UAO. This patch adds support for
this bit to binutils, following the same basic pattern as for
PSTATE.PAN. The new control bit is only available when -march=armv8.2-a
is specified.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Thu, 10 Dec 2015 14:09:03 +0000 (14:09 +0000)]
[AArch64][PATCH 2/2] Add RAS system registers.
The ARMv8.2 RAS extension adds a number of new registers. This patch
adds the registers and makes them available whenever the RAS extension
is enabled, as it is when -march=armv8.2-a is selected.
The new registers are:
erridr_el1, errselr_el1, erxfr_el1, erxctlr, erxaddr_el1,
erxmisc0_el1, erxmisc1_el1, vsesr_el2, disr_el1 and
vdisr_el2.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Add tests for new registers.
* gas/aarch64/sysreg-2.s: Likewise. Also replace some spaces with
tabs.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
"errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
"erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
(aarch64_sys_reg_supported_p): Add architecture feature tests for
new registers.
Matthew Wahab [Thu, 10 Dec 2015 14:05:01 +0000 (14:05 +0000)]
[AArch64][PATCH 1/2] Add support for RAS instruction ESB.
The ARMv8.2 RAS extension adds a new barrier instruction ESB as an alias
and the preferred form of HINT 16.
This patch adds an architectural feature flag for the RAS extension and
includes it in the features selected enabled by -march=armv8.2-a. It
also adds the ESB instruction, making it available whenever the RAS
feature is enabled.
Because ESB is the preferred form and because the target architecture
isn't available to the disassembler, HINT 16 will be disassembled as ESB
even when the target has no support for the RAS extension.
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/system-2.d: New.
* gas/aarch64/system-2.s: New.
* gas/aarch64/system.d: Adjust expected output for HINT 16.
include/opcode/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Thu, 10 Dec 2015 13:58:21 +0000 (13:58 +0000)]
[AArch64] Fix ARMv8.1 and ARMv8.2 feature settings.
ARMv8.1 includes CRC as a required extension but this isn't reflected in
the features enabled by -march=armv8.1-a. The FP16 feature modifier also
clashes with AARCH64_FEATURE_V8_1 and the list of features for ARMv8.2
is missing ARMv8.1 features.
This patch enables +crc for -march values of armv8.1-a and later. It
also fixes the values for AARCH64_FEATURE_F16 and makes
AARCH64_ARCH_V8_2 and superset of AARCH64_ARCH_V8_2.
gas/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* doc/c-aarch64.texi (AArch64 Extensions): Update entry for crc.
include/opcode
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_F16): Fix clash with
AARCH64_FEATURE_V8_1.
(AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
(AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
AARCH64_FEATURE_V8_1.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the ARMv8 FP support. This patch adds the new FP16 instructions,
making them available when the architecture extension +fp+fp16 is
specified.
The instructions added are:
- Comparisons and conditionals: FCMP, FCCMPE, FCMP, FCMPE and FCSEL.
- Arithmetic: FABS, FNEG, FSQRT, FMUL, FDIV, FADD, FSUB, FMADD, FMSUB,
FNMADD and FNMSUB.
- Rounding: FRINTN, FRINTP, FRINTM, FRINTZ, FRINTA, FRINTX and FRINTI.
- Conversions: SCVTF (fixed-point), SCVTF (integer), UCVTF (fixed-point)
UCVTF (integer), FCVTZS (fixed-point), FCVTZS (integer), FCVTZU
(fixed-point), FCVTZU (integer), FCVTNS, FCVTNU, FCVTAS, FCVTAU,
FCVTPS, FCVTPU, FCVTMS and FCVTMU.
- Scalar FMOV: immediate, general and register
gas/testsuite/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Fri, 27 Nov 2015 16:25:52 +0000 (16:25 +0000)]
[AArch64][PATCH 2/3] Adjust a utility function for floating point values.
ARMv8.2 adds 16-bit floating point operations as an optional
extension. This patch adjusts the utility function expand_fp_imm to
support 16-bit values.
The function is intended to convert an 8-bit immediate representing a
floating point value to a representation that can be passed to
fprintf. Because of the limited use of the results, the only change made
to the function is to treat a request for a 16-bit float as a request
for a 32-bit float.
opcodes/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (half_conv_t): New.
(expand_fp_imm): Replace is_dp flag with the parameter size to
specify the number of bytes for the required expansion. Treat
a 16-bit expansion like a 32-bit expansion. Add check for an
unsupported size request. Update comment.
(aarch64_print_operand): Update to support 16-bit floating point
values. Update for changes to expand_fp_imm.
Matthew Wahab [Fri, 27 Nov 2015 15:47:53 +0000 (15:47 +0000)]
[AArch64][PATCH 1/3] Support ARMv8.2 FP16 floating point instructions.
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the ARMv8 FP support. This patch set adds support for the 16-bit FP
instructions to binutils, enabling the instructions when both +fp and
+fp16 architecture extensions are enabled.
The patches in this series:
- Add a feature macro for use by the encoding/decoding mechanism.
- Adjust a utility function, used when disassembling, to support 16-bit
floating point values.
- Add the new scalar floating-point instructions.
This patch adds the feature macro FP_F16 to the AArch64 encoding/decoding
mechanism, enabling it when both +fp and +fp16 are selected.
opcodes/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Fri, 27 Nov 2015 15:25:08 +0000 (15:25 +0000)]
[AArch64] Add ARMv8.2 instructions BFC and REV64.
ARMv8.2 adds two new instructions: BFC as an alias for BFM and REV64 as
an alias for REV. This patch set adds support for these to binutils,
enabled when the -march=armv8.2-a is given. It depends on the support
for an instruction being its preferred form which was added in an
earlier patch.
This patch adds the alias BFC <Rd>, #<imm>, #<width> as the preferred
form for BFM when the source is a zero register and the conditions for
using the BFI form are met (in other words, BFC is the preferred form
for BFI <Rd>, <Rs>, #<imm>, #<width> when the <Rs> is a zero register).
gas/testsuite/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Fri, 27 Nov 2015 15:02:26 +0000 (15:02 +0000)]
[AArch64] Let aliased instructions be their preferred form.
Although the AArch64 backend supports aliased instructions, the aliasing
forms are always preferred over the real instruction. This makes it
awkward to handle instructions which have aliases but which are their
own preferred form.
This patch includes the instruction being aliased in the list of
alternatives which is searched when considering which form to use.
opcodes/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-dis.c: Weaken assert.
* aarch64-gen.c: Include the instruction in the list of its
possible aliases.
Matthew Wahab [Fri, 27 Nov 2015 13:44:10 +0000 (13:44 +0000)]
[Aarch64] Support an ARMv8.2 system register.
ARMv8.2 adds a new system register id_aa64mmfr2_el1. This patch adds
support for the register to binutils, making it available when
-march=armv8.2-a is selected.
opcodes/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Fri, 27 Nov 2015 13:19:50 +0000 (13:19 +0000)]
[AArch64] Add feature flags and command line for ARMv8.2 FP16 support.
ARMv8.2 adds optional support for 16-bit operations to the FP and
Adv.SIMD instructions. This patch adds a feature macro for this support
with a new command line option "+fp16" to enable/disable it.
Although the command line option is added as an architecture extension,
it only affects instructions available with when +fp or +simd is
enabled. If +fp16 is specified then it will also enable +fp.
There are currently no FP16 instructions implemented in binutils, this
patch is to enable subsequent work on supporting the extension.
gas/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Fri, 20 Nov 2015 16:09:34 +0000 (16:09 +0000)]
[AArch64] Add support for ARMv8.1 Virtulization Host Extensions.
The ARMv8.1 architecture includes the Virtualization Host Extensions
which add a number of system registers. This patch adds support for
these system registers, making them available when -march=armv8.1-a is
selected.
include/opcode/
2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Thu, 19 Nov 2015 09:24:14 +0000 (09:24 +0000)]
[ARM] Add ARMv8.2 architecture feature and command line option.
ARMv8.2 is an architectural extension of ARMv8. This patch adds an
architecture feature macro for ARMv8.2 to the binutils ARM target
with GAS command line option -march=armv8.2-a.
gas/
2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
Matthew Wahab [Thu, 19 Nov 2015 09:12:49 +0000 (09:12 +0000)]
[AArch64] Add ARMv8.2 command line option and feature flag.
ARMv8.2 is an architectural extension of ARMv8. This patch adds an
architecture feature macro for ARMv8.2 to the binutils AArch64 target
with GAS command line option -march=armv8.2-a.
gas/
2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
[Patch ARM] Fix build attributes for armv8-a in case of assembler files that contain no directives.
There is currently a problem in the way in which we produce
build attributes for simple assembler files that have armv8-a
instructions.
In these case we need to generate TAG_ISA_THUMB_Use to be Thumb-2
and set the architecture profile to be 'A' rather than not
setting architecture profile to be 'A' and setting TAG_ISA_THUMB_Use
to be Thumb-1.
This is a pre-requisite for any v8-m patches that have been posted.
arm-none-eabi gas testsuite run. no regressions.
* gas/config/tc-arm.c (aeabi_set_public_attributes): Adjust
TAG_ARCH_profile for armv8-a.
* gas/testsuite/gas/arm/armv8a-automatic-hlt.d: New test.
* gas/testsuite/gas/arm/armv8a-automatic-hlt.s: New test.
* gas/testsuite/gas/arm/armv8a-automatic-lda.d: New test.
* gas/testsuite/gas/arm/armv8a-automatic-lda.s: New test.
Maxim Kuvyrkov [Wed, 4 Nov 2015 13:52:34 +0000 (14:52 +0100)]
Fix detection of GNU LD version in GCC's scripts
GCC's configure scripts are confused by YYYY.MM format of Linaro releases
and mistake YYYY for major version (currently 2) and MM for minor version
(currently 25). This, in turn, makes GCC think that GNU LD doesn't support
plugins, which disables -fuse-linker-plugin functionality used by LTO.
This problem was already fixed before, and there is a comment about avoiding
"." in the BFD_VERSION_STRING, but, for reasons I can't explain, the problem
occurred again. So fixing it ... again.
Alan Modra [Sat, 25 Jul 2015 07:08:42 +0000 (16:38 +0930)]
Fix broken -Bsymbolic-functions
For selected targets. The testcase reveals a number of targets that
still need fixing.
bfd/
* elf32-arm.c (elf32_arm_final_link_relocate): Use SYMBOLIC_BIND to
check if a symbol should be bound symbolically.
* elf32-hppa.c (elf32_hppa_check_relocs,
elf32_hppa_adjust_dynamic_symbol, elf32_hppa_relocate_section,
elf32_hppa_finish_dynamic_symbol): Likewise.
* elf32-m68k.c (elf_m68k_check_relocs,
elf_m68k_relocate_section): Likewise.
* elf32-nios2.c (nios2_elf32_relocate_section,
nios2_elf32_check_relocs, allocate_dynrelocs): Likewise.
* elf32-tic6x.c (elf32_tic6x_finish_dynamic_symbol,
elf32_tic6x_relocate_section): Likewise.
ld/testsuite/
* ld-elf/symbolic-func.s,
* ld-elf/symbolic-func.r: New test.
* ld-elf/elf.exp: Run it.
projects / thirdparty / binutils-gdb.git / log
