Yao Zi [Wed, 16 Apr 2025 16:25:31 +0000 (16:25 +0000)]
riscv: dts: binman.dtsi: Switch to u-boot-nodtb entry for proper U-Boot
Switch to u-boot-nodtb entry which precisely represents a proper U-Boot
and could be matched with u_boot_any. This allows RISC-V ports that make
use of binman to be built without disabling SPL_BINMAN_UBOOT_SYMBOLS
explicitly, which is set to y by default.
Fixes: 0784510f741 ("riscv: sifive: unleashed: Switch to use binman to generate u-boot.itb") Suggested-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Yao Zi [Fri, 7 Mar 2025 13:13:41 +0000 (13:13 +0000)]
riscv: lib: Add a default implementation of board_fdt_blob_setup
It's common for S-Mode proper U-Boot to retrieve a FDT blob along with
taking control from SBI firmware. Add a weak version of
board_fdt_blob_setup to make use of it by default, avoiding copy-pasting
similar functions among boards.
Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Tom Rini [Thu, 24 Apr 2025 16:46:17 +0000 (10:46 -0600)]
Merge patch series "Add PCIe support for TI AM64 SoC"
Hrushikesh Salunke <h-salunke@ti.com> says:
TI's AM64 SoC has a single instance of Cadence PCIe Controller. This
series enables support for PCIe in AM64 SoC and to configure it in
Root-Complex mode of operation.
configs: am64x_evm_a53_defconfig: Enable configs for PCIe support
TI's AM64 SoC has single instance of PCIe Controller namely PCIe0 which
is Cadence PCIe Controller. To support PCIe functionality with PCIe0
instance in Root-Complex mode enable corresponding configs. Also enable
configs to support NVMe over PCIe.
pci: pcie_cdns_ti: Enable PCIe root-complex mode in AM64 SoC
TI's AM64 SoC has single instance of PCIe Controller namely PCIe0 which
is Cadence PCIe Controller. Add support to configure PCIe0 in Root-
Complex mode of operation.
Driver uses macro SZ_4G to configure inbound base address register.
The macro is used without including the header file in which it is
defined. Fix this.
Tom Rini [Thu, 24 Apr 2025 16:45:41 +0000 (10:45 -0600)]
Merge patch series "arm: mach-k3: remove some firewalls left over by ROM"
Bryan Brattlof <bb@ti.com> says:
This small series is here to remove some firewalls setup by ROM during
their boot and clean things up for Linux later on. Ideally this would be
a simple call to remove_fwl_configs() however the location of the
firewall is problematic (could potentially crash the core) when we're
currently executing from the memory region protected by the firewall.
So we need to introduce a function which allows us to disable specific
firewall regions and skip others to ensure boot stability.
arm: mach-k3: am625: remove any firewalls ROM has configured for HSRAM
ROM will configure a firewall to only allow HSRAM to be touched by the
R5 core. Any outside entity like DMA or the A53s will not have access to
this region. This can be problematic when U-Boot, running on the A53,
loads firmware that runs out of this region.
To simplify things remove the firewall here and let the remote core
firmware place a new firewall themselves if they wish for the memory
region.
arm: mach-k3: support disabling a single firewall region
During boot some firewall regions could contain the R5's code which if
we change the firewalls settings will crash the core. To get around this
issue, define a new function which allows us to specify specific regions
we want unlocked.
Add TI_COMMON_CMD_OPTIONS config options to Sitara K3 boards at
a53 stage since we rely on most of the commands implied for testing
and debugging purposes. Since all commands are now enabled by
default, remove the redundant CMD_* options in the a53 defconfigs.
Also add MMC_REG & MMC_SPEED_MODE_SET useful commands to
TI_COMMON_CMD_OPTIONS.
This patch adds am654_sdhci_set_control_reg to am654_sdhci.
This is required to fix UHS_MODE_SELECT for TI K3 boards.
If any of HIGH_SPEED_ENA, V1P8_SIGNAL_ENA, UHS_MODE_SELECT
are set, then data will be launched on the pos-edge of the
clock.
Since K3 SoCs did not meet timing requirements for High Speed
SDR mode at rising clock edge, none of these three should be
set, therefore limit UHS_MODE_SELECT to only be set for modes
above MMC_HS_52.
This fixes MMC write issue on am64x evm at mode High Speed
SDR.
High Speed enable bit switches data launch from the falling
clock edge (half cycle timing) to the rising clock edge (full
cycle timing). For all SD UHS modes, data launch must happen
at the rising clock edge, so set HIGH_SPEED_ENA for SDR12 and
SDR25 modes. For all HS modes, data launch must happen at the
falling clock edge, so do not set HIGH_SPEED_ENA for MMC_HS_52.
This patch adds MMC_HS_52 to the timing data structure.
Previously, this bus mode tap settings were not populated and
were instead populated for MMC_HS which is a different bus mode
up to 26MHz. Since we intended these settings according to the
device data sheet[0] for MMC_HS_52 up to 52MHz, populate MMC_HS
tap settings for MMC_HS_52.
While we are here, fix typo in ti,itap-del-sel-mms-hs.
Adding quirk to disable STIG mode since cadence controller has
issue for read/write using the STIG mode. STIG mode is enabled
by default since 2023.04 for small read/write(<8bytes).
Updated STIG mode reading from dev_get_driver_data by assigning
to platdata struct before read quirks variable.
The STIG mode is disabled for normal read case and enabled
for QSPI Jedec ID read/write since it requires STIG read/write.
Porting from linux implementation
https://lore.kernel.org/all/20241204063338.296959-1-niravkumar
.l.rabara@intel.com/T/
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Daniel Schultz [Tue, 15 Apr 2025 15:12:41 +0000 (08:12 -0700)]
mach-k3: common_fdt: Move carveout struct
Labels are not allowed before declarations. Move the carveout struct
at the beginning and only update 'end' at this point.
This will fix following error:
arch/arm/mach-k3/common_fdt.c: In function 'fdt_fixup_reserved':
arch/arm/mach-k3/common_fdt.c:156:2: error: a label can only be part of a statement and a declaration is not a statement
156 | struct fdt_memory carveout = {
| ^~~~~~
make[1]: *** [scripts/Makefile.build:256: arch/arm/mach-k3/common_fdt.o] Error 1
make: *** [Makefile:1919: arch/arm/mach-k3] Error 2
This makes spl_mmc_boot_mode consistent across am62x, 62a and 62p.
If MMCSD_MODE_EMMCBOOT is returned, FS boot fails since it checks for FS
on the hardware partitions, not the UDA. So to allow FS boot from EMMC,
the function should return MMCSD_MODE_FS instead which allows us to read
from FS on the UDA.
configs: set SPL_TEXT_BASE by default for k3 platforms
SPL_TEXT_BASE is used as the load address for the main domain SPL on k3
platforms.
Since the config value is the same for every board, this patch sets the
value 0x80080000 as default for all 64-bit ARCH_K3, 0x43c00000 as
default for the R5 cores and deletes the instances of SPL_TEXT_BASE in
individual defconfigs.
Signed-off-by: Anshul Dalal <anshuld@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Samuel Holland [Mon, 14 Apr 2025 19:30:11 +0000 (12:30 -0700)]
net: dwc_eth_qos: Fix hang when freeing packet after stop
If eqos_free_pkt() is called after eqos_stop(), eqos_stop_resets() will
have been called already. This may prevent accessing the MMIO space to
update the RX descriptor tail pointer, so we must skip the descriptor
maintenance logic. This is okay because the descriptors and tail pointer
will all be rewritten anyway during the next call to eqos_start().
This hang was observed after a failed TFTP transaction:
TFTP error: 'file <FILE> not found for <IP>' (1)
Not retrying...
eqos_stop(dev=000000047fb57330):
eqos_stop: OK
eqos_free_pkt(packet=000000c3ffb5c080, length=151)
<HANG>
Fixes: ba4dfef1469f ("net: add driver for Synopsys Ethernet QoS device") Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
This series introduces threads and uses them to improve the performance
of the USB bus scanning code and to implement background jobs in the
shell via two new commands: 'spawn' and 'wait'.
The threading framework is called 'uthread' and is inspired from the
barebox threads [2]. setjmp() and longjmp() are used to save and
restore contexts, as well as a non-standard extension called initjmp().
This new function is added in several patches, one for each
architecture that supports HAVE_SETJMP. A new symbol is defined:
HAVE_INITJMP. Two tests, one for initjmp() and one for the uthread
scheduling, are added to the lib suite.
After introducing threads and making schedule() and udelay() a thread
re-scheduling point, the USB stack initialization is modified to benefit
from concurrency when UTHREAD is enabled, where uthreads are used in
usb_init() to initialize and scan multiple busses at the same time.
The code was tested on arm64 and arm QEMU with 4 simulated XHCI buses
and some devices. On this platform the USB scan takes 2.2 s instead of
5.6 s. Tested on i.MX93 EVK with two USB hubs, one ethernet adapter and
one webcam on each, "usb start" takes 2.4 s instead of 4.6 s.
Finally, the spawn and wait commands are introduced, allowing the use of
threads from the shell. Tested on the i.MX93 EVK with a spinning HDD
connected to USB1 and the network connected to ENET1. The USB plus DHCP
init sequence "spawn usb start; spawn dhcp; wait" takes 4.5 seconds
instead of 8 seconds for "usb start; dhcp".
Add a spawn command which runs another command in the background, as
well as a wait command to suspend the shell until one or more background
jobs have completed. The job_id environment variable is set by spawn and
wait accepts optional job ids, so that one can selectively wait on any
job.
Another example showing how background jobs can make initlizations
faster. The board is i.MX93 EVK, with one spinning HDD connected to
USB1 via a hub, and a network cable plugged into ENET1.
# From power up / reset
u-boot=> setenv autoload 0
u-boot=> setenv ud "usb start; dhcp"
u-boot=> time run ud
[...]
time: 8.058 seconds
# From power up / reset
u-boot=> setenv autoload 0
u-boot=> setenv ud "spawn usb start; spawn dhcp; wait"
u-boot=> time run ud
[...]
time: 4.475 seconds
dm: usb: initialize and scan multiple buses simultaneously with uthread
Use the uthread framework to initialize and scan USB buses in parallel
for better performance. The console output is slightly modified with a
final per-bus report of the number of devices found, common to UTHREAD
and !UTHREAD. The USB tests are updated accordingly.
Tested on two platforms:
1. arm64 QEMU on a somewhat contrived example (4 USB buses, each with
one audio device, one keyboard, one mouse and one tablet)
$ make qemu_arm64_defconfig
$ make -j$(nproc) CROSS_COMPILE="ccache aarch64-linux-gnu-"
$ qemu-system-aarch64 -M virt -nographic -cpu max -bios u-boot.bin \
$(for i in {1..4}; do echo -device qemu-xhci,id=xhci$i \
-device\ usb-{audio,kbd,mouse,tablet},bus=xhci$i.0; \
done)
2. i.MX93 EVK (imx93_11x11_evk_defconfig) with two USB hubs, each with
one webcam and one ethernet adapter, resulting in the following device
tree:
USB device tree:
1 Hub (480 Mb/s, 0mA)
| u-boot EHCI Host Controller
|
+-2 Hub (480 Mb/s, 100mA)
| GenesysLogic USB2.1 Hub
|
+-3 Vendor specific (480 Mb/s, 350mA)
| Realtek USB 10/100/1000 LAN 001000001
|
+-4 (480 Mb/s, 500mA)
HD Pro Webcam C920 8F7CD51F
dm: usb: move bus initialization into new static function usb_init_bus()
To prepare for the introduction of threads in the USB initialization
sequence, move code out of usb_init() into a new helper function:
usb_init_bus() and count the number of USB controllers initialized
successfully by using the DM device_active() function.
Introduce a uthread scheduling loop into udelay() when CONFIG_UTHREAD
is enabled. This means that any uthread calling into udelay() may yield
to uthread and be scheduled again later. There is no delay in the
scheduling loop because tests have shown that such a delay can have a
detrimental effect on the console (input drops characters).
Make the schedule() call from the CYCLIC framework a uthread scheduling
point too. This makes sense since schedule() is called from a lot of
places where uthread_schedule() needs to be called.
Add struct uthread_mutex and uthread_mutex_lock(),
uthread_mutex_trylock(), uthread_mutex_unlock() to protect shared data
structures from concurrent modifications.
Add a new internal API called uthread (Kconfig symbol: UTHREAD) which
provides cooperative multi-tasking. The goal is to be able to improve
the performance of some parts of U-Boot by overlapping lengthy
operations, and also implement background jobs in the U-Boot shell.
Each uthread has its own stack allocated on the heap. The default stack
size is defined by the UTHREAD_STACK_SIZE symbol and is used when
uthread_create() receives zero for the stack_sz argument.
The implementation is based on context-switching via initjmp()/setjmp()/
longjmp() and is inspired from barebox threads [1]. A notion of thread
group helps with dependencies, such as when a thread needs to block
until a number of other threads have returned.
The name "uthread" comes from "user-space threads" because the
scheduling happens with no help from a higher privileged mode, contrary
to more complex models where kernel threads are defined. But the 'u'
may as well stand for 'U-Boot' since the bootloader may actually be
running at any privilege level and the notion of user vs. kernel may
not make much sense in this context.
Add initjm[() to sandbox, a non-standard extension to setjmp()/
longjmp() allowing to initialize a jump buffer with a function pointer
and a stack pointer. This will be useful to later introduce threads.
With this new function it becomes possible to longjmp() to a particular
function pointer (rather than to a point previously reached during
program execution as is the case with setjmp()), and with a custom stack.
Both things are needed to spin off a new thread. Then the usual
setjmp()/longjmp() pair is enough to save and restore a context, i.e.,
switch thread. The implementation is taken verbatim from barebox [1] with
the exception of the additional stack_sz argument. It is quite complex
because contrary to U-Boot platform code we don't know how the system's
C library implements the jump buffer, so we can't just write the function
and stack pointers into it.
Implement initjmp() for RISC-V, a non-standard extension to setjmp()/
longjmp() allowing to initialize a jump buffer with a function pointer
and a stack pointer. This will be useful to later introduce threads.
With this new function it becomes possible to longjmp() to a particular
function pointer (rather than to a point previously reached during
program execution as is the case with setjmp()), and with a custom stack.
Both things are needed to spin off a new thread. Then the usual
setjmp()/longjmp() pair is enough to save and restore a context, i.e.,
switch thread.
Implement initjmp() for Arm. a non-standard extension to setjmp()/
longjmp() allowing to initialize a jump buffer with a function pointer
and a stack pointer. This will be useful to later introduce threads.
With this new function it becomes possible to longjmp() to a particular
function pointer (rather than to a point previously reached during
program execution as is the case with setjmp()), and with a custom stack.
Both things are needed to spin off a new thread. Then the usual
setjmp()/longjmp() pair is enough to save and restore a context, i.e.,
switch thread.
arch: introduce initjmp() and Kconfig symbol HAVE_INITJMP
Add the HAVE_INIJMP symbol to be set by architectures that support
initjmp(), a non-standard extension to setjmp()/longjmp() allowing to
initialize a jump buffer with a function pointer and a stack pointer.
This will be useful to later introduce threads. With this new function
it becomes possible to longjmp() to a particular function pointer
(rather than to a point previously reached during program execution as
is the case with setjmp()), and with a custom stack. Both things are
needed to spin off a new thread. Then the usual setjmp()/longjmp() pair
is enough to save and restore a context, i.e., switch thread.
Add the initjmp() prototype to <include/setjmp.h> since it is common to
all architectures.
Add an entry to the API documentation: doc/api/setjmp.rst.
Tom Rini [Wed, 23 Apr 2025 14:57:13 +0000 (08:57 -0600)]
Merge tag 'mmc-2025-04-23' of https://source.denx.de/u-boot/custodians/u-boot-mmc
- Introducing back send_init_stream for omap_hsmmc
to perform the 74 clocks cycle sequence
- Move scmi regulator subnode hack to scmi_regulator
- Typo fix
Jonas Karlman [Sun, 30 Mar 2025 17:20:35 +0000 (17:20 +0000)]
board: rockchip: Add minimal generic RK3399 board
Add a minimal generic RK3399 board that only have eMMC, SDMMC, SPI flash
and USB OTG enabled. This defconfig can be used to boot from eMMC,
SD-card or SPI flash on most RK3399 boards that follow reference board
design.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Christopher Obbard <christopher.obbard@linaro.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 30 Mar 2025 17:20:34 +0000 (17:20 +0000)]
board: rockchip: Add minimal generic RK3328 board
Add a minimal generic RK3328 board that only have eMMC, SDMMC, SPI flash
and USB OTG enabled. This defconfig can be used to boot from eMMC,
SD-card or SPI flash on most RK3328 boards that follow reference board
design.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Christopher Obbard <christopher.obbard@linaro.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The rk3576 uses a different base-compatible, as starting with this
generation, the clock phase tuning is done via registers inside
the mmc controller and not from inside the CRU.
In U-Boot we do not tune at all, so no other code changes are
necessary.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The current DT bindings for the rk3576 clock use a different ID than the
one that is supposed to be written to the hardware registers.
Thus, we cannot use directly the id provided in the phandle, but rather
use a lookup table to correctly setup the hardware.
This follows the implementation done in the Linux-Kernel and also
how the rk3588 does this both in the Linux-Kernel as well as U-Boot.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[adapted from mainline Linux code for u-boot] Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Steven Liu [Tue, 15 Apr 2025 21:51:17 +0000 (23:51 +0200)]
pinctrl: rockchip: support rk3576 pinctrl
Add support for the rk3576 variant of pinctrl.
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
[adapted to mainline u-boot] Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Xuhui Lin [Tue, 15 Apr 2025 21:51:16 +0000 (23:51 +0200)]
arm: rockchip: Add RK3576 arch core support
The Rockchip RK3576 is a ARM-based SoC with quad-core Cortex-A72
and quad-core Cortex-A53 including 6TOPS NPU, Mali-G52 MC3, HDMI Out,
DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1, SD3.0/MMC4.5, UFS,
USB OTG 3.0, Type-C, USB 2.0, PCIe 2.1, SATA 3, Ethernet, SDIO3.0, I2C,
UART, SPI, GPIO and PWM.
Add arch core support for it.
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
[adapted for mainline u-boot] Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:47:02 +0000 (22:47 +0000)]
board: rockchip: Add minimal generic RK3528 board
Add a minimal generic RK3528 board that only have eMMC and SD-card
enabled. This defconfig can be used to boot from eMMC or SD-card on most
RK3528 boards that follow reference board design.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:57 +0000 (22:46 +0000)]
adc: rockchip-saradc: Add support for RK3528
The Successive Approximation ADC (SARADC) in RK3528 uses the v2
controller and support:
- 10-bit resolution
- Up to 1MS/s sampling rate
- 4 single-ended input channels
- Current consumption: 0.5mA @ 1MS/s
Add support for the 4 channels of 10-bit resolution supported by SARADC
in RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:55 +0000 (22:46 +0000)]
mmc: rockchip_sdhci: Gate clock for glitch free phase switching
Enable clock stopping to gate clock during phase code change to ensure
glitch free phase switching in auto-tuning circuit. Fixes HS200 mode
on RK3528.
POST_CHANGE_DLY
Time taken for phase switching and stable clock output.
- Less than 4-cycle latency
PRE_CHANGE_DLY
Maximum Latency specification between transmit clock and receive clock.
- Less than 4-cycle latency
TUNE_CLK_STOP_EN
Clock stopping control for Tuning and auto-tuning circuit. When enabled,
clock gate control output is pulled low before changing phase select
codes. This effectively stops the receive clock. Changing phase code
when clocks are stopped ensures glitch free phase switching.
- Clocks stopped during phase code change
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Steven Liu [Mon, 7 Apr 2025 22:46:50 +0000 (22:46 +0000)]
pinctrl: rockchip: Add support for RK3528
Add pinctrl driver for RK3528.
Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with adjustments
to use regmap_update_bits().
Signed-off-by: Steven Liu <steven.liu@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit bd4c8a1c08f92d863d89c0ddff59e5f5bc6a1e34) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 460ef5b623e5fa69843305faf50f6b1a8e81e1cd) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 6793b56b79df26ab3323e5293b97577d0786ddb3) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit a3556ede6b48c7760ac3608ad77601fca26d2ce0) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 9bcf6ccdd87c3be48fe7d75150c6e403c5c0a42d) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit db7a99c423dea0ead19d6a18053d898a762a3b48) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 8ba64ba5cb301bca777ba7f0d2a2a72f49af5ff2) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 6e03c7e28e2d929a420809a24b0379305a9fb86a) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The Quality-of-Service (QsS) node stores/restores specific
register contents when the power domains is turned off/on.
Add QoS node so that they can connect to the power domain.
(cherry picked from commit 9ee90dfd6957fcc42ea94c43d195b01d1b286713) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 7 Apr 2025 22:46:37 +0000 (22:46 +0000)]
arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528
Add pinctrl and gpio nodes for RK3528 and import rk3528-pinctrl.dtsi
from vendor linux-6.1-stan-rkr5 kernel with the hdmi-pins-idle node
removed due to missing label reference to pcfg_output_low_pull_down.
(cherry picked from commit 89a24fa2e923b68a42ccc8cc9cb2d5bdf291ac40) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 12f69f638472dc9cf1b62816c7d4407de1846d12) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Yao Zi [Mon, 7 Apr 2025 22:46:35 +0000 (22:46 +0000)]
arm64: dts: rockchip: Add clock generators for RK3528 SoC
Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is
generated by internal Ethernet phy, a fixed clock node is added as a
placeholder to avoid orphans.
(cherry picked from commit 60741472b42e92d2393327cb70669ab90e3b382f) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Yao Zi [Mon, 7 Apr 2025 22:46:34 +0000 (22:46 +0000)]
dt-bindings: clock: Document clock and reset unit of RK3528
There are two types of clocks in RK3528 SoC, CRU-managed and
SCMI-managed. Independent IDs are assigned to them.
For the reset part, differing from previous Rockchip SoCs and
downstream bindings which embeds register offsets into the IDs, gapless
numbers starting from zero are used.
(cherry picked from commit 8768d063e732e64892e4d1d09aa583d1394c8388) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
projects / thirdparty / u-boot.git / log
