pr28651.c (main): Use INT_MAX instead of assuming it is 0x7fffffff.
* gcc.c-torture/execute/pr28651.c (main): Use INT_MAX instead of
assuming it is 0x7fffffff.
* gcc.dg/tree-ssa/vrp29.c (decCompare)(main): Likewise.
* gcc.dg/Wconversion-integer-no-sign.c (h): Likewise.
* df-problems.c (df_create_unused_note): Removed do_not_gen parm
and the updating of the live and do_not_gen sets.
(df_note_bb_compute): Added updating of live and do_not_gen sets
for regular defs so that the case of clobber inside conditional
call is processed correctly.
Mark Mitchell [Fri, 27 Jul 2007 17:13:29 +0000 (17:13 +0000)]
re PR c++/32346 (long long bitfield passed to int argument incorrectly)
PR c++/32346
* call.c (convert_for_arg_passing): Only widen bitfields to their
declared types if necessary.
PR c++/32346
* g++.dg/expr/bitfield9.C: New test.
re PR fortran/32035 ('<anonymous>' may be used uninitialized in this function)
PR fortran/32035
* trans-stmt.c (gfc_trans_character_select): Replace the
mechanism with labels by a SWITCH_EXPR.
* trans-decl.c (gfc_build_builtin_function_decls): Change
return type for select_string.
* runtime/select.c (select_string): Adjust prototype and function
so that the return value is an integer, not a pointer.
gcc/
* expr.h (store_bit_field): Don't return a value.
* expmed.c (check_predicate_volatile_ok): New function.
(store_bit_field_1): New function, extracted from store_bit_field.
Take a fallback_p argument and return true if the operation succeeded.
Only use store_fixed_bit_field if fallback_p. Don't recompute
mode_for_extraction; use op_mode instead. Try forcing memories
into registers if the insv expander fails.
(store_bit_field): Use store_bit_field_1 with fallback_p true.
Don't return a value.
(convert_extracted_bit_field): New function, extracted from
store_bit_field.
(extract_bit_field_1): Likewise. Take a fallback_p argument
and return NULL if the operation succeeded. Only use
extract_fixed_bit_field if fallback_p. Only calculate one
extraction mode. Combine code for extv and extzv. Try forcing
memories into registers if the ext(z)v expander fails.
(extract_bit_field): Use extract_bit_field_1 with fallback_p true.
gcc/testsuite/
* gcc.target/mips/ins-1.c: New test.
gcc/
* df.h (df_mw_hardreg): Remove "loc" field.
* df-scan.c (df_ref_record): Don't set it. Remove redundant
local variable.
* df-problems.c (df_whole_mw_reg_unused_p): New function,
split out from df_set_unused_notes_for_mw. Return false for
partial references. Assert that mw_reg is a REG when returning true.
(df_set_unused_notes_for_mw): Use it. Use mw_reg instead of *loc.
(df_whole_mw_reg_dead_p): New function, split out from
df_set_dead_notes_for_mw. Return false for partial references.
Assert that mw_reg is a REG when returning true.
(df_set_dead_notes_for_mw): Use it. Use mw_reg instead of *loc.
Remove redundant bitmap check.
Nick Clifton [Thu, 26 Jul 2007 08:37:01 +0000 (08:37 +0000)]
Change copyright header to refer to version 3 of the GNU General Public License and to point readers at the COPYING3 file and the FSF's license web page.
Jan Hubicka [Thu, 26 Jul 2007 03:43:40 +0000 (05:43 +0200)]
tree-ssa-live.c: Include debug.h and flags.h.
* tree-ssa-live.c: Include debug.h and flags.h.
(mark_scope_block_unused): New function.
(remove_unused_scope_block_p): New function.
(remove_unused_locals): Remove unused blocks too.
Ian Lance Taylor [Thu, 26 Jul 2007 00:27:34 +0000 (00:27 +0000)]
combine.c (combine_max_regno): Remove.
* combine.c (combine_max_regno): Remove. Remove all uses.
(struct reg_stat_struct): Rename from struct reg_stat.
(reg_stat_type): Define, and declare VECs.
(reg_stat): Change from pointer to VEC. Change all uses.
(combine_split_insns): New static function.
(try_combine, find_split_point): Call it instead of split_insns.
gcc/
* config/mips/mips.c (machine_function): Add
initialized_mips16_gp_pseudo_p.
(mips16_gp_pseudo_reg): Do not emit the initialization of
mips16_gp_pseudo_rtx when being called from the gimple cost-
calculation routines; emit it on the first use outside those
routines.
re PR libstdc++/31836 (FAIL: 27_io/basic_istream/extractors_arithmetic/char/12.cc execution test)
PR libstdc++/31836
* config/locale/generic/c_locale.cc (__convert_to_v): Don't use
strtold if _GLIBCXX_HAVE_BROKEN_STRTOLD is defined.
* config/os/hpux/os_defines.h (_GLIBCXX_HAVE_BROKEN_STRTOLD): Define
if __hppa__ is defined.
gcc/
* Makefile.in (TEXI_GCC_FILES): Add arm-neon-intrinsics.texi.
* config.gcc (arm*-*-*): Add arm_neon.h to extra headers.
(with_fpu): Allow --with-fpu=neon.
* config/arm/aof.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15.
* config/arm/aout.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15.
* config/arm/arm-modes.def (EI, OI, CI, XI): New modes.
* config/arm/arm-protos.h (neon_immediate_valid_for_move)
(neon_immediate_valid_for_logic, neon_output_logic_immediate)
(neon_pairwise_reduce, neon_expand_vector_init, neon_reinterpret)
(neon_emit_pair_result_insn, neon_disambiguate_copy)
(neon_vector_mem_operand, neon_struct_mem_operand, output_move_quad)
(output_move_neon): Add prototypes.
* config/arm/arm.c (FL_NEON): New flag for NEON processor capability.
(all_fpus): Add FPUTYPE_NEON.
(fp_model_for_fpu): Add NEON field.
(arm_return_in_memory): Return vectors <= 16 bytes in ARM registers.
(arm_arg_partial_bytes): Allow NEON vectors to be passed partially
in registers.
(arm_legitimate_address_p): Don't support fancy addressing for NEON
structure moves.
(thumb2_legitimate_address_p): Likewise.
(neon_valid_immediate): Recognize and prepare constants suitable for
NEON instructions.
(neon_immediate_valid_for_move): New function. Recognize and prepare
immediates for NEON move instructions.
(neon_immediate_valid_for_logic): New function. Recognize and
prepare immediates for NEON logic instructions.
(neon_output_logic_immediate): New function. Create asm string
suitable for outputting immediate logic instructions.
(neon_pairwise_reduce): New function. Implement reduction using
pairwise operations.
(neon_expand_vector_init): New function. Expand a (possibly
non-constant) vector initialization.
(neon_vector_mem_operand): New function. Memory operands supported
for quad-word loads/stores to/from ARM or NEON registers. Don't
allow base+offset addressing for core regs.
(neon_struct_mem_operand): New function. Valid mems for NEON
structure moves.
(coproc_secondary_reload_class): Enable NEON registers to be loaded
from neon_vector_mem_operand addresses without a secondary register.
(add_minipool_forward_ref): Handle >8-byte minipool entries.
(add_minipool_backward_ref): Likewise.
(dump_minipool): Likewise.
(push_minipool_fix): Likewise.
(output_move_quad): New function. Output quad-word moves, loads and
stores using ARM registers.
(output_move_vfp): Add support for vectors in VFP (NEON) D
registers.
(output_move_neon): Output a NEON load/store to/from a quadword
register.
(arm_print_operand): Implement new codes:
- 'c' for unadorned integers (without a # sign).
- 'J', 'K' for reg+2/reg+3, reg+3/reg+2 in little/big-endian
mode.
- 'e', 'f' for the low and high D parts of a NEON Q register.
- 'q' outputs a NEON Q register.
- 'h' outputs ranges of D registers for VLDM/VSTM etc.
- 'T' prints NEON opcode features from a coded bitmask.
- 'F' is similar to T, but signed/unsigned codes both print as
'i'.
- 't' is similar to T, but 'u' is printed instead of 'p'.
- 'O' prints 'r' if NEON instruction should perform rounding (as
specified by bitmask), else prints nothing.
- '#' is a punctuation character to stop operand numbers from
running together with following digits in the assembler
strings for instructions (when using mode attributes).
(arm_assemble_integer): Handle extra NEON vector modes. Permute
constant vectors in big-endian mode, where necessary.
(arm_hard_regno_mode_ok): Allow vectors in VFP/NEON registers.
Handle EI, OI, CI, XI modes.
(ashlv4hi3, ashlv2si3, lshrv4hi3, lshrv2si3, ashrv4hi3)
(ashrv2si3): Rename IWMMXT2_BUILTINs to...
(ashlv4hi3_iwmmxt, ashlv2si3_iwmmxt, lshrv4hi3_iwmmxt)
(lshrv2si3_iwmmxt, ashrv4hi3_iwmmxt, ashrv2si3_iwmmxt): New names.
(neon_builtin_type_bits): Add enumeration, one bit for each vector
type.
(v8qi_UP, v4hi_UP, v2si_UP, v2sf_UP, di_UP, v16qi_UP, v8hi_UP)
(v4si_UP, v4sf_UP, v2di_UP, ti_UP, ei_UP, oi_UP, UP): Define macros
to turn v8qi, etc. into bits defined above.
(neon_itype): New enumeration. Classifications of NEON builtins.
(neon_builtin_datum): Define struct. Contains information about
a single builtin (with multiple modes).
(CF): Define helper macro for...
(VAR1...VAR10): Define builtins with a type, name and 1-10 different
modes.
(neon_builtin_data): New array. Define information about builtins
for use during initialization/expansion.
(arm_init_neon_builtins): New function.
(arm_init_builtins): Call arm_init_neon_builtins if TARGET_NEON is
true.
(neon_builtin_compare): New function.
(locate_neon_builtin_icode): New function. Find an insn code for a
builtin given a function code for that builtin. Also return type of
builtin (NEON_BINOP, NEON_UNOP etc.).
(builtin_arg): New enumeration. Types of arguments for builtins.
(arm_expand_neon_args): New function. Expand a generic NEON builtin.
Takes a variable argument list of builtin_arg types, terminated by
NEON_ARG_STOP.
(arm_expand_neon_builtin): New function. Expand a NEON builtin.
(neon_reinterpret): New function. Expand NEON reinterpret intrinsic.
(neon_emit_pair_result_insn): New function. Support returning pairs
of vectors via a pointer.
(neon_disambiguate_copy): New function. Set up operands for a
multi-word copy such that registers do not get clobbered.
(arm_expand_builtin): Call arm_expand_neon_builtin if fcode >=
ARM_BUILTIN_NEON_BASE.
(arm_file_start): Set float-abi attribute for NEON.
(arm_vector_mode_supported_p): Enable NEON vector modes.
(arm_mangle_map_entry): New.
(arm_mangle_map): New.
(arm_mangle_vector_type): New.
* config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_NEON__
when appropriate.
(TARGET_NEON): New macro. Target supports NEON.
(fputype): Add FPUTYPE_NEON.
(UNITS_PER_SIMD_WORD): Define. Allow quad-word registers to be used
for vectorization based on command-line arg.
(NEON_REGNO_OK_FOR_NREGS): Define.
(VALID_NEON_DREG_MODE, VALID_NEON_QREG_MODE)
(VALID_NEON_STRUCT_MODE): Define.
(PRINT_OPERAND_PUNCT_VALID_P): '#' is valid punctuation.
(arm_builtins): Add ARM_BUILTIN_NEON_BASE.
* config/arm/arm.md (VUNSPEC_POOL_16): Insert constant for unspec.
(consttable_16): Add pattern for outputting 16-byte minipool
entries.
(movv2si, movv4hi, movv8qi): Remove blank expanders (redefined in
vec-common.md).
(vec-common.md, neon.md): Include md files.
* config/arm/arm.opt (mvectorize-with-neon-quad): Add option.
* config/arm/constraints.md (constraint "Dn", "Dl", "DL"): Define.
(memory_constraint "Ut", "Un", "Us"): Define.
* config/arm/iwmmxt.md (VMMX, VSHFT): New mode macros.
(MMX_char): New mode attribute.
(addv8qi3, addv4hi3, addv2si3): Remove. Replace with...
(*add<mode>3_iwmmxt): New insn pattern.
(subv8qi3, subv4hi3, subv2si3): Remove. Replace with...
(*sub<mode>3_iwmmxt): New insn pattern.
(mulv4hi3): Rename to...
(*mulv4hi3_iwmmxt): This.
(smaxv8qi3, smaxv4hi3, smaxv2si3, umaxv8qi3, umaxv4hi3)
(umaxv2si3, sminv8qi3, sminv4hi3, sminv2si3, uminv8qi3)
(uminv4hi3, uminv2si3): Remove. Replace with...
(*smax<mode>3_iwmmxt, *umax<mode>3_iwmmxt, *smin<mode>3_iwmmxt)
(*umin<mode>3_iwmmxt): These.
(ashrv4hi3, ashrv2si3, ashrdi3_iwmmxt): Replace with...
(ashr<mode>3_iwmmxt): This new pattern.
(lshrv4hi3, lshrv2si3, lshrdi3_iwmmxt): Replace with...
(lshr<mode>3_iwmmxt): This new pattern.
(ashlv4hi3, ashlv2si3, ashldi3_iwmmxt): Replace with...
(ashl<mode>3_iwmmxt): This new pattern.
* config/arm/neon-docgen.ml: New file. Generate documentation for
intrinsics.
* config/arm/neon-gen.ml: New file. Generate arm_neon.h header.
* config/arm/arm_neon.h: New (autogenerated).
* config/arm/neon-testgen.ml: New file. Generate NEON tests
automatically.
* config/arm/neon.md: New file. Define NEON instructions.
* config/arm/neon.ml: New file. Abstract description of NEON
instructions, used to generate arm_neon.h header, documentation and tests.
* config/arm/t-arm (MD_INCLUDES): Add vec-common.md, neon.md.
* vec-common.md: New file. Shared parts for iWMMXt and NEON vector
support.
* doc/extend.texi (ARM Built-in Functions): Rename and remove
extraneous comma.
(ARM NEON Intrinsics): New subsection.
* doc/arm-neon-intrinsics.texi: New (autogenerated).
gcc/testsuite/
* gcc.dg/vect/vect.exp: Check is-effective-target arm_neon_hw.
* gcc.dg/vect/tree-vect.h: Check for NEON SIMD support.
* lib/gcc-dg.exp (cleanup-saved-temps): Fix comment.
* lib/target-supports.exp (check_effective_target_arm_neon_ok)
(check_effective_target_arm_neon_hw): New.
* gcc.target/arm/neon/neon.exp: New file.
* gcc.target/arm/neon/polytypes.c: New file.
* gcc.target/arm/neon/v*.c (1870 files): New (autogenerated).
Co-Authored-By: Joseph Myers <joseph@codesourcery.com> Co-Authored-By: Mark Shinwell <shinwell@codesourcery.com> Co-Authored-By: Paul Brook <paul@codesourcery.com>
From-SVN: r126911
predcom-1.c (count_averages): Avoid overflow during addition if an int is only 16 bits wide.
* gcc.dg/tree-ssa/predcom-1.c (count_averages): Avoid overflow
during addition if an int is only 16 bits wide.
* gcc.dg/tree-ssa/predcom-2.c (fib): Avoid overflow of 16-bit int.
pr29584.c: Only run test if pointers have the same size as "long int" and are 32 or 64...
* gcc.dg/torture/pr29584.c: Only run test if pointers have the same
size as "long int" and are 32 or 64 bits wide.
* gcc.dg/torture/pr28814.c: Likewise.
Danny Smith [Wed, 25 Jul 2007 07:34:52 +0000 (07:34 +0000)]
struct-layout-1_generate.c (COMPAT_PRLL): Define and use throughout as long long printf format specifier.
* gcc.dg/compat/struct-layout-1_generate.c (COMPAT_PRLL):
Define and use throughout as long long printf format specifier.
* g++.dg/compat/struct-layout-1_generate.c (COMPAT_PRLL):
Likewise.
Jan Hubicka [Wed, 25 Jul 2007 05:58:40 +0000 (07:58 +0200)]
regclass.c (move_table): New type.
* regclass.c (move_table): New type.
(move_cost, may_move_in_cost, may_move_out_cost): Use it.
(init_move_cost): Break out from ...
(init_reg_sets_1): ... here; simplify computation of
have_regs-of_mode and contains_reg_of_mode.
(record_reg_classes): Unswitch internal loops.
(copy_cost): Trigger lazy initialization of move cost
(record_address_regs): Likewise.
Paul Thomas [Tue, 24 Jul 2007 19:16:36 +0000 (19:16 +0000)]
re PR fortran/31205 (aliased operator assignment produces wrong result)
2007-07-24 Paul Thomas <pault@gcc.gnu.org>
PR fortran/31205
PR fortran/32842
* trans-expr.c (gfc_conv_function_call): Remove the default
initialization of intent(out) derived types.
* symbol.c (gfc_lval_expr_from_sym): New function.
* matchexp.c (gfc_get_parentheses): Return argument, if it is
character and posseses a ref.
* gfortran.h : Add prototype for gfc_lval_expr_from_sym.
* resolve.c (has_default_initializer): Move higher up in file.
(resolve_code): On detecting an interface assignment, check
if the rhs and the lhs are the same symbol. If this is so,
enclose the rhs in parenetheses to generate a temporary and
prevent any possible aliasing.
(apply_default_init): Remove code making the lval and call
gfc_lval_expr_from_sym instead.
(resolve_operator): Give a parentheses expression a type-
spec if it has no type.
* trans-decl.c (gfc_trans_deferred_vars): Apply the a default
initializer, if any, to an intent(out) derived type, using
gfc_lval_expr_from_sym and gfc_trans_assignment. Check if
the dummy is present.
2007-07-24 Paul Thomas <pault@gcc.gnu.org>
PR fortran/31205
* gfortran.dg/alloc_comp_basics_1.f90 : Restore number of
"deallocates" to 24, since patch has code rid of much spurious
code.
* gfortran.dg/interface_assignment_1.f90 : New test.
PR fortran/32842
* gfortran.dg/interface_assignment_2.f90 : New test.
Paul Thomas [Tue, 24 Jul 2007 19:15:27 +0000 (19:15 +0000)]
re PR fortran/31205 (aliased operator assignment produces wrong result)
2007-07-24 Paul Thomas <pault@gcc.gnu.org>
PR fortran/31205
PR fortran/32842
* trans-expr.c (gfc_conv_function_call): Remove the default
initialization of intent(out) derived types.
* symbol.c (gfc_lval_expr_from_sym): New function.
* matchexp.c (gfc_get_parentheses): Return argument, if it is
character and posseses a ref.
* gfortran.h : Add prototype for gfc_lval_expr_from_sym.
* resolve.c (has_default_initializer): Move higher up in file.
(resolve_code): On detecting an interface assignment, check
if the rhs and the lhs are the same symbol. If this is so,
enclose the rhs in parenetheses to generate a temporary and
prevent any possible aliasing.
(apply_default_init): Remove code making the lval and call
gfc_lval_expr_from_sym instead.
(resolve_operator): Give a parentheses expression a type-
spec if it has no type.
* trans-decl.c (gfc_trans_deferred_vars): Apply the a default
initializer, if any, to an intent(out) derived type, using
gfc_lval_expr_from_sym and gfc_trans_assignment. Check if
the dummy is present.
2007-07-24 Paul Thomas <pault@gcc.gnu.org>
PR fortran/31205
* gfortran.dg/alloc_comp_basics_1.f90 : Restore number of
"deallocates" to 24, since patch has code rid of much spurious
code.
* gfortran.dg/interface_assignment_1.f90 : New test.
PR fortran/32842
* gfortran.dg/interface_assignment_2.f90 : New test.
Daniel Franke [Tue, 24 Jul 2007 16:45:32 +0000 (12:45 -0400)]
re PR fortran/32778 (pedantic warning: intrinsics that are GNU extensions not part of -std=gnu)
gcc/fortran:
2007-07-24 Daniel Franke <franke.daniel@gmail.com>
PR fortran/32778
* intrinsic.c (add_sym): Do not exclude any symbols, even if not part
of the selected standard.
(make generic): Likewise.
(make alias): Likewise, set standard the alias belongs to.
(add_subroutines): Call make_noreturn unconditionally.
(check_intrinsic_standard): Change return value to try.
(gfc_intrinsic_func_interface): Check return value of above function.
(gfc_intrinsic_sub_interface): Likewise.
gcc/testsuite:
2007-07-24 Daniel Franke <franke.daniel@gmail.com>
PR fortran/32778
* gfortran.dg/imag_2.f: Removed
* gfortran.dg/warn_std_1.f90: New test.
* gfortran.dg/warn_std_2.f90: New test.
* gfortran.dg/warn_std_3.f90: New test.
Thomas Koenig [Tue, 24 Jul 2007 05:52:44 +0000 (05:52 +0000)]
re PR fortran/30814 (non-conforming array sizes in PACK should raise an error)
2007-07-24 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/30814
* trans-decl.c (generate_function_code): Add argument
for flag_bounds_check to the array for set_options.
* invoke.texi: Mention that some checks require
-fbounds-check to be set during compilation of the
main program.
2007-07-24 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/30814
* libgfortran.h: Add bounds_check to compile_options_t.
* runtime/compile_options.c (set_options): Add handling
of compile_options.bounds_check.
* intrinsics/pack_generic.c (pack_internal): Also determine
the number of elements if compile_options.bounds_check is
true. Raise runtime error if a different array shape is
detected.
2007-07-24 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/30814
* gfortran.dg/pack_bounds_1.f90: New test case.
Jan Hubicka [Mon, 23 Jul 2007 23:07:46 +0000 (23:07 +0000)]
i386.c (ix86_secondary_memory_needed): Break out to...
* i386.c (ix86_secondary_memory_needed): Break out to...
(inline_secondary_memory_needed): ... here.
(ix86_memory_move_cost): Break out to ...
(inline_memory_move_cost): ... here; add support for IN value of 2 for
maximum of input and output; fix handling of Q_REGS on 64bit.
(ix86_secondary_memory_needed): Microoptimize.
re PR fortran/32797 ([ISO C Binding] Internal Error: gfc_basic_typename(): Undefined type)
2007-07-23 Christopher D. Rickett <crickett@lanl.gov>
PR fortran/32797
PR fortran/32800
* decl.c (verify_bind_c_sym): Use the result symbol for functions
with a result clause. Warn if implicitly typed. Verify the type
and rank of the SHAPE argument, if given.
* resolve.c (gfc_iso_c_sub_interface): Use gfc_procedure_use to
check the actual args against the formal, sorting them if
necessary.
* symbol.c (gen_shape_param): Initialize type of SHAPE param to
BT_VOID.
2007-07-23 Christopher D. Rickett <crickett@lanl.gov>
PR fortran/32797
PR fortran/32800
* gfortran.dg/bind_c_usage_8.f03: New test case.
* gfortran.dg/c_f_pointer_tests_2.f03: Ditto.
* gfortran.dg/c_ptr_tests_5.f03: Updated expected error message.
Peter Bergner [Mon, 23 Jul 2007 16:43:24 +0000 (11:43 -0500)]
PR middle-end/PR28690
PR middle-end/PR28690
* optabs.c (expand_binop): (emit_cmp_and_jump_insns): Allow EQ compares.
* rtlanal.c (commutative_operand_precedence): Prefer both REG_POINTER
and MEM_POINTER operands over REG and MEM operands.
(swap_commutative_operands_p): Change return value to bool.
* rtl.h: Update the corresponding prototype.
* tree-ssa-address.c (gen_addr_rtx): Use simplify_gen_binary
instead of gen_rtx_PLUS.
* simplify-rtx.c (simplify_plus_minus_op_data_cmp): Change return
value to bool. Change function arguments to rtx's and update code
to match.
(simplify_plus_minus): Update the simplify_plus_minus_op_data_cmp
calls to match the new declaration.
* simplify-rtx.c (simplify_associative_operation): Don't
reorder simplify_binary_operation arguments.
Co-Authored-By: Jakub Jelinek <jakub@redhat.com>
From-SVN: r126852
mips.c (override_options): Use mips_costs to derive the default branch cost.
gcc/
* config/mips/mips.c (override_options): Use mips_costs to derive
the default branch cost.
* config/mips/mips.h (BRANCH_COST): Use mips_branch_cost rather
than mips_costs.
* config/mips/mips.opt (mbranch-cost=): New option.
* doc/invoke.texi (-mbrach-cost): Document new MIPS option.
gcc/testsuite/
* gcc.target/mips/branch-cost-1.c: New test.
* gcc.target/mips/branch-cost-2.c: Likewise.
projects / thirdparty / gcc.git / log
