__builtin_round() fails to save/restore FP exception flags around the FP
compare insn which can potentially clobber the same.
Worth noting that the fflags restore bracketing is slightly different
than the glibc implementation. Both FLT and FCVT can potentially clobber
fflags. gcc generates below where even if branch is not taken and FCVT
is not executed, FLT still executed. Thus FSFLAGS is placed AFTER the
label 'L3'. glibc implementation FLT can't clobber due to early NaN check,
so FSFLAGS can be moved under the branch, before the label.
Tomasz Kamiński [Tue, 8 Jul 2025 08:04:41 +0000 (10:04 +0200)]
libstdc++: Do not expose set_brackets/set_separator for formatter with format_kind other than sequence [PR119861]
The standard defines separate specializations of range-default-formatter, out
of which only one for range_format::sequence provide the set_brackets and
set_separator methods. We implemented it as one specialization and exposed
this method for range_format other than string or debug_string, i.e. when
range_formatter was used as underlying formatter.
PR libstdc++/119861
libstdc++-v3/ChangeLog:
* include/std/format (formatter<_Rg, _CharT>::set_separator)
(formatter<_Rg, _CharT>::set_brackets): Constrain with
(format_kind<_Rg> == range_format::sequence).
* testsuite/std/format/ranges/pr119861_neg.cc: New test.
Nathaniel Shead [Sun, 17 Aug 2025 03:06:52 +0000 (13:06 +1000)]
testsuite: Fix PR108080 testcase for some targets [PR121396]
I added a testcase for the (temporary) warning that we don't currently
support the 'gnu::optimize' or 'gnu::target' attributes in r15-10183;
however, some targets produce target nodes even when only an optimize
attribute is present. This adjusts the warning.
PR c++/108080
PR c++/121396
gcc/testsuite/ChangeLog:
* g++.dg/modules/pr108080.H: Also allow target warnings.
aarch64: Fix mode mismatch when building a predicate [PR121118]
This PR is about a case where we used aarch64_expand_sve_const_pred_trn
to combine two predicates, one of which was constructing using
aarch64_sve_move_pred_via_while. The former requires the inputs
to have mode VNx16BI, but the latter returned VNx8BI for a .H
WHILELO.
The proper fix, used on trunk, is to make the pattern emitted by
aarch64_sve_move_pred_via_while produce an VNx16BI for all element
sizes, since every bit of the result is significant. However,
that required some target-independent changes that are too invasive
to backport. This patch goes for the simpler (but less robust) approach
of using the original pattern and casting it to VNx16BI after the fact.
Since the WHILELO pattern is an unspec, the chances of something
optimising it in a way that changes the undefined bits of the output
should be very low, especially on a release branch. It is still a less
satisfactory fix though.
gcc/
PR target/121118
* config/aarch64/aarch64.cc (aarch64_sve_move_pred_via_while):
Return a VNx16BI predicate.
gcc/testsuite/
PR target/121118
* gcc.target/aarch64/sve/acle/general/pr121118_1.c: New test.
Alex Coplan [Tue, 15 Jul 2025 10:49:27 +0000 (11:49 +0100)]
aarch64: Relax fpm_t assert to allow const_ints [PR120986]
This relaxes an overzealous assert that required the fpm_t argument to
be in DImode when expanding FP8 intrinsics. Of course this fails to
account for modeless const_ints.
Alex Coplan [Tue, 15 Jul 2025 09:37:58 +0000 (10:37 +0100)]
aarch64: Fix predication of FP8 FDOT insns [PR120986]
The predication of the SVE2 FP8 dot product insns was relying on the
architectural dependency:
FEAT_FP8DOT2 => FEAT_FP8DOT4
which was relaxed in GCC as of r15-7480-g299a8e2dc667e795991bc439d2cad5ea5bd379e2, thus leading to
unrecognisable insn ICEs when compiling a two-way FDOT with just
+fp8dot2. This patch introduces a new mode iterator which selectively
enables the appropriate mode(s) depending on which of the FP8DOT{2,4}
features are available, and uses it to fix the predication of the
patterns.
gcc/ChangeLog:
PR target/120986
* config/aarch64/aarch64-sve2.md (@aarch64_sve_dot<mode>):
Switch mode iterator from SVE_FULL_HSF to new iterator;
remove insn predicate as this is now taken care of by conditions
in the mode iterator.
(@aarch64_sve_dot_lane<mode>): Likewise.
* config/aarch64/iterators.md (SVE_FULL_HSF_FP8_FDOT): New.
gcc/testsuite/ChangeLog:
PR target/120986
* gcc.target/aarch64/pr120986-1.c: New test.
Pengfei Li [Thu, 7 Aug 2025 14:52:45 +0000 (14:52 +0000)]
AArch64: Fix invalid immediate offsets in SVE gather/scatter [PR121449]
This patch fixes incorrect constraints in RTL patterns for AArch64 SVE
gather/scatter with type widening/narrowing and vector-plus-immediate
addressing. The bug leads to below "immediate offset out of range"
errors during assembly, eventually causing compilation failures.
/tmp/ccsVqBp1.s: Assembler messages:
/tmp/ccsVqBp1.s:54: Error: immediate offset out of range 0 to 31 at operand 3 -- `ld1b z1.d,p0/z,[z1.d,#64]'
Current RTL patterns for such instructions incorrectly use vgw or vgd
constraints for the immediate operand, base on the vector element type
in Z registers (zN.s or zN.d). However, for gather/scatter with type
conversions, the immediate range for vector-plus-immediate addressing is
determined by the element type in memory, which differs from that in
vector registers. Using the wrong constraint can produce out-of-range
offset values that cannot be encoded in the instruction.
This patch corrects the constraints used in these patterns. A test case
that reproduces the issue is also included.
Bootstrapped and regression-tested on aarch64-linux-gnu.
gcc/ChangeLog:
PR target/121449
* config/aarch64/aarch64-sve.md
(mask_gather_load<mode><v_int_container>): Use vg<Vesize>
constraints for alternatives with immediate offset.
(mask_scatter_store<mode><v_int_container>): Likewise.
gcc/testsuite/ChangeLog:
PR target/121449
* g++.target/aarch64/sve/pr121449.C: New test.
aarch64: Mark SME functions as .variant_pcs [PR121414]
Unlike base PCS functions, __arm_streaming and __arm_streaming_compatible
functions allow/require PSTATE.SM to be 1 on entry, so they need to
be treated as STO_AARCH64_VARIANT_PCS.
Similarly, functions that share ZA or ZT0 with their callers require
ZA to be active on entry, whereas the base PCS requires ZA to be
dormant or off. These functions too need to be marked as having
a variant PCS.
gcc/
PR target/121414
* config/aarch64/aarch64.cc (aarch64_is_variant_pcs): New function,
split out from...
(aarch64_asm_output_variant_pcs): ...here. Handle various types
of SME function type.
gcc/testsuite/
PR target/121414
* gcc.target/aarch64/sme/pr121414_1.c: New test.
The previous patch for PR121294 handled svtrn1/2, svuzp1/2, and svzip1/2.
This one extends it to handle svrev intrinsics, where the same kind of
wrong code can be generated.
gcc/
PR target/121294
* config/aarch64/aarch64.md (UNSPEC_REV_PRED): New unspec.
* config/aarch64/aarch64-sve.md (@aarch64_sve_rev<mode>_acle)
(*aarch64_sve_rev<mode>_acle): New patterns.
* config/aarch64/aarch64-sve-builtins-base.cc
(svrev_impl::expand): Use the new patterns for boolean svrev.
gcc/testsuite/
PR target/121294
* gcc.target/aarch64/sve/acle/general/rev_2.c: New test.
aarch64: Use VNx16BI for more permutations [PR121294]
The patterns for the predicate forms of svtrn1/2, svuzp1/2,
and svzip1/2 are shared with aarch64_vectorize_vec_perm_const.
The .H, .S, and .D forms operate on VNx8BI, VNx4BI, and VNx2BI
respectively. Thus, for all four element widths, there is one
significant bit per element, for both the inputs and the output.
That's appropriate for aarch64_vectorize_vec_perm_const but not
for the ACLE intrinsics, where every bit of the output is
significant, and where every bit of the selected input elements
is therefore also significant. The current expansion can lead
the optimisers to simplify inputs by changing the upper bits
of the input elements (since the current patterns claim that
those bits don't matter), which in turn leads to wrong code.
The ACLE expansion should operate on VNx16BI instead, for all
element widths.
There was already a pattern for a VNx16BI-only form of TRN1, for
constructing certain predicate constants. The patch generalises it to
handle the other five permutations as well. For the reasons given in
the comments, this is done by making the permutation unspec an operand
to a new UNSPEC_PERMUTE_PRED, rather than overloading the existing
unspecs, and rather than adding a new unspec for each permutation.
gcc/
PR target/121294
* config/aarch64/iterators.md (UNSPEC_TRN1_CONV): Delete.
(UNSPEC_PERMUTE_PRED): New unspec.
* config/aarch64/aarch64-sve.md (@aarch64_sve_trn1_conv<mode>):
Replace with...
(@aarch64_sve_<perm_insn><mode>_acle)
(*aarch64_sve_<perm_insn><mode>_acle): ...these new patterns.
* config/aarch64/aarch64.cc (aarch64_expand_sve_const_pred_trn):
Update accordingly.
* config/aarch64/aarch64-sve-builtins-functions.h
(binary_permute::expand): Use the new _acle patterns for
predicate operations.
Remove MODE_COMPOSITE_P test from simplify_gen_subreg [PR120718]
simplify_gen_subreg rejected subregs of literal constants if
MODE_COMPOSITE_P. This was added by the fix for PR96648 in
g:c0f772894b6b3cd8ed5c5dd09d0c7917f51cf70f. Jakub said:
As for the simplify_gen_subreg change, I think it would be desirable
to just avoid creating SUBREGs of constants on all targets and for all
constants, if simplify_immed_subreg simplified, fine, otherwise punt,
but as we are late in GCC11 development, the patch instead guards this
behavior on MODE_COMPOSITE_P (outermode) - i.e. only conversions to
powerpc{,64,64le} double double long double - and only for the cases where
simplify_immed_subreg was called.
I'm not sure about relaxing the codes further, since subregs might
be wanted for CONST, SYMBOL_REF and LABEL_REF. But removing the
MODE_COMPOSITE_P is needed to fix PR120718, where we get an ICE
from generating a subreg of a V2SI const_vector.
Unlike the trunk version, this backport does not remove the
VOIDmode test; see PR121501.
[PR121007, LRA]: Fall back to reload of whole inner address in PR case and constrain iteration number of address reloads
gcc/ChangeLog:
PR target/121007
* lra-constraints.cc (process_address_1): When changing base reg
on a reg of the base class, fall back to reload of whole inner address.
(process_address): Constrain the iteration number.
Andrew Pinski [Sun, 22 Jun 2025 18:35:19 +0000 (12:35 -0600)]
[RISC-V][PR target/119830] Fix RISC-V codegen on 32bit hosts
So this is Andrew's patch from the PR. We weren't clean for a 32bit host in
some of the arithmetic for constant synthesis.
I confirmed the bug on a 32bit linux host, then confirmed that Andrew's patch
from the PR fixes the problem, then ran Andrew's patch through my tester
successfully.
Naturally I'll wait for pre-commit testing, but I'm not expecting problems.
PR target/119830
gcc/
* config/riscv/riscv.cc (riscv_build_integer_1): Make arithmetic in bclr case
clean for 32 bit hosts.
gcc/testsuite/
* gcc.target/riscv/pr119830.c: New test.
H.J. Lu [Thu, 24 Jul 2025 14:38:13 +0000 (07:38 -0700)]
x86: Disallow -mtls-dialect=gnu with no_caller_saved_registers
__tls_get_addr doesn't preserve vector registers. When a function
with no_caller_saved_registers attribute calls __tls_get_addr, YMM
and ZMM registers will be clobbered. Issue an error and suggest
-mtls-dialect=gnu2 in this case.
gcc/
PR target/121208
* config/i386/i386.cc (ix86_tls_get_addr): Issue an error for
-mtls-dialect=gnu with no_caller_saved_registers attribute and
suggest -mtls-dialect=gnu2.
aarch64: Adapt unwinder to linux's SME signal behaviour
SME uses a lazy save system to manage ZA. The idea is that,
if a function with ZA state wants to call a "normal" function,
it can leave its state in ZA and instead set up a lazy save buffer.
If, unexpectedly, that normal function contains a nested use of ZA,
that nested use of ZA must commit the lazy save first.
This lazy save system uses a special system register called TPIDR2_EL0.
See:
The ABI specifies that, on entry to an exception handler, the following
things must be true:
* PSTATE.SM must be 0 (the processor must be in non-streaming mode)
* PSTATE.ZA must be 0 (ZA must be off)
* TPIDR2_EL0 must be 0 (there must be no uncommitted lazy save)
This is normally done by making _Unwind_RaiseException & friends
commit any lazy save before they unwind. This also has the side
effect of ensuring that TPIDR2_EL0 is never left pointing to a
lazy save buffer that has been unwound.
However, things get more complicated with signals. If:
(a) a signal is raised while ZA is dormant (that is, while there is an
uncommitted lazy save);
(b) the signal handler throws an exception; and
(c) that exception is caught outside the signal handler
something must ensure that the lazy save from (a) is committed.
This would be simple if the signal handler was entered with ZA and
TPIDR2_EL0 intact. However, for various good reasons that are out
of scope here, this is not done. Instead, Linux now clears both
TPIDR2_EL0 and PSTATE.ZA before entering a signal handler, see:
Therefore, it is the unwinder that must simulate a commit of the lazy
save from (a). It can do this by reading the previous values of
TPIDR2_EL0 and ZA from the sigcontext.
The SME-related sigcontext structures were only added to linux's
asm/sigcontext.h relatively recently and we can't rely on GCC being
built against such recent kernel header files. The patch therefore uses
defines relevant macros if they are not defined and provide types that
comply with ABI layout of the corresponding linux types.
The patch includes some ugly casting in an attempt to support big-endian
ILP32, even though SME on big-endian ILP32 linux should never be a thing.
We can remove it if we also remove ILP32 support from GCC.
gcc/testsuite/
* lib/target-supports.exp (add_options_for_aarch64_sme)
(check_effective_target_aarch64_sme_hw): New procedures.
* g++.target/aarch64/sme/sme_throw_1.C: New test.
* g++.target/aarch64/sme/sme_throw_2.C: Likewise.
libgcc/
* config/aarch64/linux-unwind.h (aarch64_fallback_frame_state):
If a signal was raised while there was an uncommitted lazy save,
commit the save as part of the unwind process.
The rtx cost value defined by the target backend affects the
calculation of register pressure classes in the IRA, thus affecting
scheduling. This may cause program performance degradation.
For example, OpenSSL 3.5.1 SHA512 and SPEC CPU 2017 exchange_r.
This problem can be avoided by defining a set of register pressure
classes in the target backend instead of using the default IRA to
automatically calculate them.
gcc/ChangeLog:
PR target/120476
* config/loongarch/loongarch.cc
(loongarch_compute_pressure_classes): New function.
(TARGET_COMPUTE_PRESSURE_CLASSES): Define.
mengqinggang [Fri, 8 Aug 2025 08:22:59 +0000 (16:22 +0800)]
LoongArch: macro instead enum for base abi type
enum can't be used in #if.
For #if expression, identifiers that are not macros,
which are all considered to be the number zero.
This patch may fix https://sourceware.org/bugzilla/show_bug.cgi?id=32776.
gcc/ChangeLog:
* config/loongarch/loongarch-def.h (ABI_BASE_LP64D): New macro.
(ABI_BASE_LP64F): New macro.
(ABI_BASE_LP64S): New macro.
(N_ABI_BASE_TYPES): New macro.
testsuite: handle-multiline-outputs must allow both cc1 and cc1.exe
Prior to 14-2027-g985d6480fe5, the input text had the file extensions
pruned. In 14-2027-g985d6480fe5, due to the move of the call, the
pruning is never done. This change restores the pruning of the file
extension to allow multiline test to pass on both Windows and other
platforms like Linux.
Xi Ruoyao [Tue, 8 Jul 2025 06:39:11 +0000 (14:39 +0800)]
lra: Reallow reloading user hard registers if the insn is not asm [PR 120983]
The PR 87600 fix has disallowed reloading user hard registers to resolve
earlyclobber-induced conflict.
However before reload, recog completely ignores the constraints of
insns, so the RTL passes may produce insns where some user hard
registers violate an earlyclobber. Then we'll get an ICE without
reloading them, like what we are recently encountering in LoongArch test
suite.
IIUC "recog does not look at constraints until reload" has been a
well-established rule in GCC for years and I don't have enough skill to
challange it. So reallow reloading user hard registers (but still
disallow doing so for asm) to fix the ICE.
gcc/ChangeLog:
PR rtl-optimization/120983
* lra-constraints.cc (process_alt_operands): Allow reloading
user hard registers unless the insn is an asm.
Xi Ruoyao [Tue, 8 Jul 2025 06:07:21 +0000 (14:07 +0800)]
testsuite: Enable the PR 87600 tests for LoongArch
I'm going to refine a part of the PR 87600 fix which seems triggering
PR 120983 that LoongArch is particularly suffering. Enable the PR 87600
tests so I'll not regress PR 87600.
Patrick Palka [Mon, 4 Aug 2025 20:51:00 +0000 (16:51 -0400)]
c++: constrained memfn vs corresponding using [PR121351]
The b.f(42) calls in the below testcases started to get rejected as
ambiguous after r15-3740 which corrected our inheritedness tiebreaker to
only apply to constructors (and not all member functions) as per CWG2273.
But arguably these calls should still be valid regardless of the
tiebreaker because B::f corresponds to and therefore hides A::f, so
there should only be a single candidate in the first place. This
doesn't happen because when determining correspondence we compare
the members' uninstantiated constraints instead of their partially
substituted constraints as in other declaration matching situations.
It doesn't really make sense to compare uninstantiated constraints
from two different template contexts.
This patch fixes this by substituting in outer template arguments before
comparing constraints of two potentially corresponding member functions.
PR c++/121351
PR c++/119859
gcc/cp/ChangeLog:
* class.cc (add_method): Substitute outer template arguments
into constraints before comparing them if the declarations are
from different classes.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/concepts-using5.C: New test.
* g++.dg/cpp2a/concepts-using5a.C: New test.
Patrick Palka [Mon, 4 Aug 2025 20:43:33 +0000 (16:43 -0400)]
c++: constexpr evaluation of abi::__dynamic_cast [PR120620]
r13-3299 changed our internal declaration of __dynamic_cast to reside
inside the abi/__cxxabiv1:: namespace instead of the global namespace,
matching the real declaration. This inadvertently made us now attempt
constexpr evaluation of user-written calls to abi::__dynamic_cast since
cxx_dynamic_cast_fn_p now also returns true for them, but we're not
prepared to handle arbitrary calls to __dynamic_cast, and therefore ICE.
This patch restores cxx_dynamic_cast_fn_p to return true only for
synthesized calls to __dynamic_cast, which can be distinguished by
DECL_ARTIFICIAL, since apparently the synthesized declaration of
__dynamic_cast doesn't get merged with the actual declaration.
PR c++/120620
gcc/cp/ChangeLog:
* constexpr.cc (cxx_dynamic_cast_fn_p): Return true only
for synthesized __dynamic_cast.
gcc/testsuite/ChangeLog:
* g++.dg/cpp2a/constexpr-dynamic19.C: New test.
* g++.dg/cpp2a/constexpr-dynamic1a.C: New test.
Jakub Jelinek [Fri, 8 Aug 2025 07:20:51 +0000 (09:20 +0200)]
tailc: Handle other forms of finally_tmp.N conditional cleanups after musttail [PR121389]
My earlier r16-1886 PR120608 change incorrectly assumed that the
finally_tmp.N vars introduced by eh pass will be only initialized
to values 0 and 1 and there will be only EQ_EXPR/NE_EXPR comparisons
of those.
The following testcases show that is a bad assumption, the eh pass
sets finally_tmp.N vars to 0 up to some highest index depending on
hoiw many different exits there are from the finally region.
And it emits then switch (finally_tmp.N) statement for all the
different cases. So, if it uses more than 0/1 indexes, the lowering
of the switch can turn it into a series of GIMPLE_CONDs,
if (finally_tmp.N_M > 15)
goto ...
else
goto ...
if (finally_tmp.N_M > 7)
goto ...
else
goto ...
etc. (and that also means no longer single uses). And if unlucky,
we can see a non-lowered GIMPLE_SWITCH as well.
So, the following patch removes the assumption that it has to be 0/1
and EQ_EXPR/NE_EXPR, allows all the normal integral comparisons
and handles GIMPLE_SWITCH too.
2025-08-08 Jakub Jelinek <jakub@redhat.com>
PR middle-end/121389
* tree-tailcall.cc (find_tail_calls): For finally_tmp.N
handle not just GIMPLE_CONDs with EQ_EXPR/NE_EXPR and only
values 0 and 1, but arbitrary non-negative values, arbitrary
comparisons in conditions and also GIMPLE_SWITCH next to
GIMPLE_CONDs.
* c-c++-common/asan/pr121389-1.c: New test.
* c-c++-common/asan/pr121389-2.c: New test.
* c-c++-common/asan/pr121389-3.c: New test.
* c-c++-common/asan/pr121389-4.c: New test.
Jakub Jelinek [Wed, 6 Aug 2025 09:30:08 +0000 (11:30 +0200)]
bitint: Fix up INTEGER_CST PHI handling [PR121413]
The following testcase is miscompiled on aarch64-linux.
The problem is in the optimization to shorten large constants
in PHI arguments.
In a couple of places during bitint lowering we compute
minimal precision of constant and if it is significantly
smaller than the precision of the type, store smaller constant
in memory and extend it at runtime (zero or all ones).
Now, in most places that works fine, we handle the stored number
of limbs by loading them from memory and then the rest is
extended. In the PHI INTEGER_CST argument handling we do
it differently, we don't form there any loops (because we
insert stmt sequences on the edges).
The problem is that we copy the whole _BitInt variable from
memory to the PHI VAR_DECL + initialize the rest to = {} or
memset to -1. It has
min_prec = CEIL (min_prec, limb_prec) * limb_prec;
precision, so e.g. on x86_64 there is no padding and it works
just fine. But on aarch64 which has abi_limb_mode TImode
and limb_mode DImode it doesn't in some cases.
In the testcase the constant has 408 bits min precision, rounded up
to limb_prec (64) is 448, i.e. 7 limbs. But aarch64 with TImode
abi_limb_mode will actually allocate 8 limbs and the most significant
limb is solely padding. As we want to extend the constant with all
ones, copying the padding (from memory, so 0s) will result in
64 0 bits where 1 bits were needed.
The following patch fixes it by detecting this case and setting
min_prec to a multiple of abi limb precision so that it has
no padding.
2025-08-06 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/121413
* gimple-lower-bitint.cc (abi_limb_prec): New variable
(bitint_precision_kind): Initialize it.
(gimple_lower_bitint): Clear it at the start. For
min_prec > limb_prec descreased precision vars for
INTEGER_CST PHI arguments ensure min_prec is either
prec or multiple of abi_limb_prec.
Jakub Jelinek [Wed, 6 Aug 2025 09:28:37 +0000 (11:28 +0200)]
bitint: Fix up handling of uninitialized mul/div/float cast operands [PR121127]
handle_operand_addr (used for the cases where we use libgcc APIs, so
multiplication, division, modulo, casts of _BitInt to float/dfp) when it
sees default definition of an SSA_NAME which is not PARM_DECL (i.e.
uninitialized one) just allocates single uninitialized limb, there is no
need to waste more memory on it, it can just tell libgcc that it has
64-bit precision, not say 1024 bit etc.
Unfortunately, doing this runs into some asserts when we have a narrowing
cast of the uninitialized SSA_NAME (but still large/huge _BitInt).
The following patch fixes that by using a magic value in *prec_stored
for the uninitialized cases (0) and just don't do any *prec tweaks for
narrowing casts from that. precs still needs to be maintained as before,
that one is used for big endian adjustment.
2025-08-06 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/121127
* gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr): For
uninitialized SSA_NAME, set *prec_stored to 0 rather than *prec.
Handle that case in narrowing casts. If prec_stored is non-NULL,
set *prec_stored to prec_stored_val.
Jakub Jelinek [Mon, 4 Aug 2025 15:12:55 +0000 (17:12 +0200)]
libstdc++: Add various missing exports [PR121373]
On Sat, Aug 02, 2025 at 09:05:07PM +0200, Jakub Jelinek wrote:
> Wonder how to automatically discover other missing exports (like in PR121373
> std::byteswap), maybe one could dig that stuff somehow from the raw
> dump (look for identifiers in std namespace (and perhaps inlined namespaces
> thereof at least) which don't start with underscore.
To answer that question, I wrote a simple plugin which just dumps the names
(which do not start with underscore) in std namespace (and its inlined
namespaces) and for non-inline namespaces in there which do not start with
underscore also recurses on those namespaces.
Plugin source in
https://gcc.gnu.org/pipermail/libstdc++/2025-August/062859.html
I went through it all now, using cppreference as a quick check for stuff
removed in C++17/C++20 and for everything added verified it is in
corresponding eel.is/c++-draft/*.syn etc. and looked it up in the libstdc++
headers for guarding macros.
2025-08-04 Jakub Jelinek <jakub@redhat.com>
hexne <printfne@gmail.com>
PR libstdc++/121373
* src/c++23/std.cc.in (std::ranges::shift_left,
std::ranges::shift_right): Only export for C++23 and later.
(std::ranges::fold_left_first_with_iter_result,
std::ranges::fold_left_with_iter_result): Export.
(std::byteswap): Export for C++23 and later.
(std::ranges::iter_move, std::ranges::iter_swap): Export.
(std::projected_value_t): Export for C++26 and later.
(std::out_ptr_t, std::inout_ptr_t): Export.
(std::ranges::iota_result): Export.
(std::regex_constants): Export a lot of constants.
(std::is_scoped_enum, std::is_scoped_enum_v): Export.
Jakub Jelinek [Sun, 3 Aug 2025 16:27:42 +0000 (18:27 +0200)]
libcpp: Fix up cpp_maybe_module_directive [PR120845]
My changes for "Module Declarations Shouldn’t be Macros" paper broke
the following testcase. The backup handling intentionally tries to
drop CPP_PRAGMA_EOL token if things go wrong, which is desirable for the
case where we haven't committed to the module preprocessing directive
(i.e. changed the first token to the magic one). In that case there is
no preprocessing directive start and so CPP_PRAGMA_EOL would be wrong.
If there is a premature new-line after we've changed the first token though,
we shouldn't drop CPP_PRAGMA_EOL, because otherwise we ICE in the FE.
While clang++ and MSVC accept the testcase, in my reading it is incorrect
at least in the C++23 and newer wordings and I think the changes have been
a DR, https://eel.is/c++draft/cpp.module has no exception for new-lines
and https://eel.is/c++draft/cpp.pre#1.sentence-2 says that new-line (unless
deleted during phase 2 when after backslash) ends the preprocessing
directive.
The patch arranges for eol being set only in the not_module case.
2025-08-03 Jakub Jelinek <jakub@redhat.com>
PR c++/120845
libcpp/
* lex.cc (cpp_maybe_module_directive): Move eol variable declaration
to the start of the function, initialize to false and only set it to
peek->type == CPP_PRAGMA_EOL in the not_module case. Formatting fix.
gcc/testsuite/
* g++.dg/modules/cpp-21.C: New test.
* libgomp.texi (omp_init_allocator): Refer to 'Memory allocation'
for available memory spaces.
(OMP_ALLOCATOR): Move list of traits and predefined memspaces
and allocators to ...
(Memory allocation): ... here. Document omp(x)::allocator::*;
minor wording tweaks, be more explicit about memkind, pinned and
pool_size.
matches any mode of (and ...) on input, but hard-codes (and:SI ...)
in the output. This causes an ICE if the incoming (and ...) is DImode
rather than SImode.
Co-developed-by: Richard Sandiford <richard.sandiford@arm.com>
PR target/96226
gcc/ChangeLog:
* config/i386/predicates.md (and_operator): New operator.
* config/i386/i386.md (splitter after *<rotate_insn><mode>3_mask):
Use and_operator to match AND RTX and use its mode
in the split pattern.
Richard Earnshaw [Mon, 19 May 2025 15:19:39 +0000 (16:19 +0100)]
arm: fully validate mem_noofs_operand [PR120351]
It's not enough to just check that a memory operand is of the form
mem(reg); after RA we also need to validate the register being used.
The safest way to do this is to call memory_operand.
PR target/120351
gcc/ChangeLog:
* config/arm/predicates.md (mem_noofs_operand): Also check the op
is a valid memory_operand.
Richard Biener [Thu, 31 Jul 2025 11:06:36 +0000 (13:06 +0200)]
tree-optimization/121320 - UBSAN error in ao_ref_init_from_vn_reference
The multiplication by BITS_PER_UNIT should be done in poly_offset_int.
PR tree-optimization/121320
* tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Convert
op->off to poly_offset_int before multiplying by
BITS_PER_UNIT.
Jakub Jelinek [Fri, 1 Aug 2025 06:41:54 +0000 (08:41 +0200)]
bswap: Fix up ubsan detected UB in find_bswap_or_nop [PR121322]
The following testcase results in compiler UB as detected by ubsan.
find_bswap_or_nop first checks is_bswap_or_nop_p and if that fails
on the tmp_n value, tries some rotation of that if possible.
The discovery what rotate count to use ignores zero bytes from
the least significant end (those mean zero bytes and so can be masked
away) and on the first non-zero non-0xff byte (0xff means don't know),
1-8 means some particular byte of the original computes count (the rotation
count) from that byte + the byte index.
Now, on the following testcase we have tmp_n 0x403020105060700, i.e.
the least significant byte is zero, then the msb from the original value,
byte below it, another one below it, then the low 32 bits of the original
value. So, we stop at count 7 with i 1, it wraps around and we get count
0.
Then we invoke UB on
tmp_n = tmp_n >> count | tmp_n << (range - count);
because count is 0 and range is 64.
Now, of course I could fix it up by doing tmp_n << ((range - count) % range)
or something similar, but that is just wasted compile time, if count is 0,
we already know that is_bswap_or_nop_p failed on that tmp_n value and
so it will fail again if the value is the same. So I think better
just return NULL (i.e. punt).
2025-08-01 Jakub Jelinek <jakub@redhat.com>
PR middle-end/121322
* gimple-ssa-store-merging.cc (find_bswap_or_nop): Return NULL if
count is 0.
c++/modules: Warn for optimize attributes instead of ICEing [PR108080]
This PR is the most frequently reported modules bug for 15, as the ICE
message does not indicate the issue at all and reducing to find the
underlying cause can be tricky.
I have a WIP patch to fix this issue by just reconstructing these nodes
on stream-in from any attributes applied to the functions, but since at
this stage it may still take a while to be ready, it seems useful to me
to at least make the error here more friendly and guide users to what
they could do to work around this issue.
In fact, as noted on the PR, a lot of the time it should be harmless to
just ignore the optimize etc. attribute and continue translation, at the
user's own risk; this patch as such turns the ICE into a warning with no
option to silence.
PR c++/108080
gcc/cp/ChangeLog:
* module.cc (trees_out::core_vals): Warn when streaming
target/optimize node; adjust comments.
(trees_in::core_vals): Don't stream a target/optimize node.
gcc/testsuite/ChangeLog:
* g++.dg/modules/pr108080.H: New test.
Signed-off-by: Nathaniel Shead <nathanieloshead@gmail.com> Reviewed-by: Jason Merrill <jason@redhat.com> Reviewed-by: Patrick Palka <ppalka@redhat.com>
(cherry picked from commit 643c5b42e21dbc02e9bde01865c880b26aa5f938)
c++/modules: Merge PARM_DECL properties from function definitions [PR121238]
When we merge a function definition, if there already exists a forward
declaration in the importing TU we use the PARM_DECLs belonging to that
decl. This usually works fine, except as noted in the linked PR there
are some flags (such as TREE_ADDRESSABLE) that only get set on a
PARM_DECL once a definition is provided.
This patch fixes the wrong-code issues by propagating any properties on
PARM_DECLs I could find that may affect codegen.
PR c++/121238
gcc/cp/ChangeLog:
* module.cc (trees_in::fn_parms_fini): Merge properties for
definitions.
gcc/testsuite/ChangeLog:
* g++.dg/modules/merge-19.h: New test.
* g++.dg/modules/merge-19_a.H: New test.
* g++.dg/modules/merge-19_b.C: New test.
Signed-off-by: Nathaniel Shead <nathanieloshead@gmail.com> Reviewed-by: Jason Merrill <jason@redhat.com> Reviewed-by: Patrick Palka <ppalka@redhat.com>
(cherry picked from commit 70136bdc76ae1774162ccbeeedd33aa531950e68)
AVR: rtl-optimization/121340 - New mini-pass to undo superfluous moves from insn combine.
Insn combine may come up with superfluous reg-reg moves, where the combine
people say that these are no problem since reg-alloc is supposed to optimize
them. The issue is that the lower-subreg pass sitting between combine and
reg-alloc may split such moves, coming up with a zoo of subregs which are
only handled poorly by the register allocator.
This patch adds a new avr mini-pass that handles such cases.
As an example, take
int f_ffssi (long x)
{
return __builtin_ffsl (x);
}
where the two functions have the same interface, i.e. there are no extra
moves required for the argument or for the return value. However,
Jason Merrill [Thu, 31 Jul 2025 18:23:31 +0000 (14:23 -0400)]
c++: constexpr, array, private ctor [PR120800]
Here cxx_eval_vec_init_1 wants to recreate the default constructor call that
we previously built and threw away in build_vec_init_elt, but we aren't in
the same access context at this point. Since we already checked access,
let's just suppress access control here.
Redoing overload resolution at constant evaluation time is sketchy, but
should usually be fine for a default/copy constructor.
In powerpc64-unknown-linux-musl, signal.h does not include asm/ptrace.h,
which causes "member access into incomplete type 'struct pt_regs'"
errors. Include the header explicitly to fix this.
Also in sanitizer_linux_libcdep.cpp, there is a usage of TlsPreTcbSize
which is not defined in such a platform. Guard the branch with macro.
aarch64: Prevent streaming-compatible code from assembler rejection [PR121028]
Streaming-compatible functions can be compiled without SME enabled, but need
to use "SMSTART SM" and "SMSTOP SM" to temporarily switch into the streaming
state of a callee. These switches are conditional on the current mode being
opposite to the target mode, so no SME instructions are executed if SME is not
available.
However, in GAS, "SMSTART SM" and "SMSTOP SM" always require +sme. A call
from a streaming-compatible function, compiled without SME enabled, to a non
-streaming function will be rejected as:
Error: selected processor does not support `smstop sm'..
To work around this, we make use of the .inst directive to insert the literal
encodings of "SMSTART SM" and "SMSTOP SM".
gcc/ChangeLog:
PR target/121028
* config/aarch64/aarch64-sme.md (aarch64_smstart_sm): Use the .inst
directive if !TARGET_SME.
(aarch64_smstop_sm): Likewise.
gcc/testsuite/ChangeLog:
PR target/121028
* gcc.target/aarch64/sme/call_sm_switch_1.c: Tell check-function
-bodies not to ignore .inst directives, and replace the test for
"smstart sm" with one for it's encoding.
* gcc.target/aarch64/sme/call_sm_switch_11.c: Likewise.
* gcc.target/aarch64/sme/pr121028.c: New test.
GCC doesn't support SME without SVE2, so the -march=armv8-a+<ext> argument to
check_no_compiler_messages causes aarch64_asm_<ext>_ok to return zero for SME
and any <ext> that implies it.
This patch changes the baseline architecure to armv9-a for these extensions.
gcc/testsuite/ChangeLog:
* lib/target-supports.exp: Split the extensions that require SME into
a separate set, and use armv9-a as their baseline.
Patrick Palka [Thu, 5 Jun 2025 15:07:25 +0000 (11:07 -0400)]
c++: substituting fn parm redeclared with dep alias tmpl [PR120224]
Here we declare f twice, the second time around using a dependent
alias template. Due to alias template transparency these are logically
the same overload. But now the function type of f (produced from the
first declaration) diverges from the type of its formal parameter
(produced from the subsequent redefinition) in that substituting T=int
succeeds for the function type but not for the formal parameter type.
This eventually causes us to produce an undiagnosed error_mark_node in
the AST of the function call, leading to failure of the sanity check
check added in r14-6343-g0c018a74eb1aff.
Before r14-6343 we would still go on to reject the testcase later at
instantiation time, from regenerate_decl_from_template, making this a
regression.
To fix this, it seems we just need to propagate error_mark_node upon
substitution failure into the type of a PARM_DECL.
PR c++/120224
gcc/cp/ChangeLog:
* pt.cc (tsubst_function_decl): Return error_mark_node if
substituting into the formal parameter list failed.
(tsubst_decl) <case PARM_DECL>: Return error_mark_node
upon TREE_TYPE substitution failure, when in a SFINAE
context. Return error_mark_node upon DECL_CHAIN substitution
failure.
Jakub Jelinek [Thu, 31 Jul 2025 10:10:02 +0000 (12:10 +0200)]
change get_best_mode args int -> HOST_WIDE_INT [PR121264]
The following testcase is miscompiled, because byte 0x20000000
is bit 0x100000000 and ifcombine incorrectly combines the two loads
into a BIT_FIELD_REF even when they are very far away.
The problem is that gimple-fold.cc ifcombine uses get_best_mode heavily,
and that function has just int bitsize and int bitpos arguments, so
when called e.g. with
if (get_best_mode (end_bit - first_bit, first_bit, 0, ll_end_region,
ll_align, BITS_PER_WORD, volatilep, &lnmode))
where end_bit - first_bit doesn't fit into int, it is silently truncated.
If there was just a single problematic get_best_mode call, I would probably
just check for overflows in the caller, but there are many.
And the two arguments are used solely as arguments to
bit_field_mode_iterator constructor which has HOST_WIDE_INT arguments,
so I think the easiest fix is just make the get_best_mode arguments
also HOST_WIDE_INT.
2025-07-31 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/121264
* machmode.h (get_best_mode): Change type of first 2 arguments
from int to HOST_WIDE_INT.
* stor-layout.cc (get_best_mode): Likewise.
Jan Hubicka [Fri, 11 Jul 2025 10:37:24 +0000 (12:37 +0200)]
Fix ICE in speculative devirtualization
This patch fixes ICE bilding lto1 with autoprofiledbootstrap and in pr114790.
What happens is that auto-fdo speculatively devirtualizes to a wrong target.
This is due to a bug where it mixes up dwarf names and linkage names of inline
functions I need to fix as well.
Later we clone at WPA time. At ltrans time clone is materialized and call is
turned into a direct call (this optimization is missed by ipa-cp propagation).
At this time we should resolve speculation but we don't. As a result we get
error from verifier after inlining complaining that there is speculative call
with corresponding direct call lacking speculative flag.
This seems long-lasting problem in cgraph_update_edges_for_call_stmt_node but
I suppose it does not trigger since we usually speculate correctly or notice
the direct call at WPA time already.
Bootstrapped/regtested x86_64-linux.
gcc/ChangeLog:
PR ipa/114790
* cgraph.cc (cgraph_update_edges_for_call_stmt_node): Resolve devirtualization
if call statement was optimized out or turned to direct call.
gcc/testsuite/ChangeLog:
* g++.dg/lto/pr114790_0.C: New test.
* g++.dg/lto/pr114790_1.C: New test.
Pengfei Li [Wed, 30 Jul 2025 09:51:11 +0000 (10:51 +0100)]
vect: Fix insufficient alignment requirement for speculative loads [PR121190]
This patch fixes a segmentation fault issue that can occur in vectorized
loops with an early break. When GCC vectorizes such loops, it may insert
a versioning check to ensure that data references (DRs) with speculative
loads are aligned. The check normally requires DRs to be aligned to the
vector mode size, which prevents generated vector load instructions from
crossing page boundaries.
However, this is not sufficient when a single scalar load is vectorized
into multiple loads within the same iteration. In such cases, even if
none of the vector loads crosses page boundaries, subsequent loads after
the first one may still access memory beyond current valid page.
Consider the following loop as an example:
while (i < MAX_COMPARE) {
if (*(p + i) != *(q + i))
return i;
i++;
}
When compiled with "-O3 -march=znver2" on x86, the vectorized loop may
include instructions like:
Note two speculative vector loads are generated for each DR (p and q).
The first vmovdqa and vpcmpeqq are safe due to the vector size (32-byte)
alignment, but the following ones (at offset 32) may not be safe because
they could read from the beginning of the next memory page, potentially
leading to segmentation faults.
To avoid the issue, this patch increases the alignment requirement for
speculative loads to DR_TARGET_ALIGNMENT. It ensures all vector loads in
the same vector iteration access memory within the same page.
disabled transformation from "movq $-1,reg" to "pushq $-1; popq reg" for
-Oz. But for legacy integer registers, the former is 4 bytes and the
latter is 3 bytes. Enable such transformation for -Oz.
gcc/
PR target/120427
* config/i386/i386.md (peephole2): Transform "movq $-1,reg" to
"pushq $-1; popq reg" for -Oz if reg is a legacy integer register.
gcc/testsuite/
PR target/120427
* gcc.target/i386/pr120427-5.c: New test.
Eliminate redundant vpextrq/vpinsrq when move TI to V4SI.
r14-1902-g96c3539f2a3813 split TImode move with 2 DImode move, it's
supposed to optimize TImode in parameter/return since accoring to
psABI it's stored into 2 general registers.
But when TImode is not in parameter/return, it could create redundancy
in the PR.
The termio ioctls are no longer used after commit 59978b21ad9c
("[sanitizer_common] Remove interceptors for deprecated struct termio
(#137403)"), remove them. Fixes this build error:
../../../../libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp:765:27: error: invalid application of ‘sizeof’ to incomplete type ‘__sanitizer::termio’
765 | unsigned IOCTL_TCGETA = TCGETA;
| ^~~~~~
../../../../libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp:769:27: error: invalid application of ‘sizeof’ to incomplete type ‘__sanitizer::termio’
769 | unsigned IOCTL_TCSETA = TCSETA;
| ^~~~~~
../../../../libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp:770:28: error: invalid application of ‘sizeof’ to incomplete type ‘__sanitizer::termio’
770 | unsigned IOCTL_TCSETAF = TCSETAF;
| ^~~~~~~
../../../../libsanitizer/sanitizer_common/sanitizer_platform_limits_posix.cpp:771:28: error: invalid application of ‘sizeof’ to incomplete type ‘__sanitizer::termio’
771 | unsigned IOCTL_TCSETAW = TCSETAW;
| ^~~~~~~
C: Flex array in union followed by a structure field is not reported [PR120354]
There is only one last_field for a structure type, but there might
be multiple last_fields for a union type, therefore we should ORed
the result of TYPE_INCLUDES_FLEXARRAY for multiple last_fields of
a union type.
PR c/120354
gcc/c/ChangeLog:
* c-decl.cc (finish_struct): Or the results for TYPE_INCLUDES_FLEXARRAY.
C: Flex array in the middle via type alias is not reported [PR120353]
The root cause of the bug is: the TYPE_INCLUDES_FLEXARRAY marking of the
structure type is not copied to its aliased type.
The fix is to copy this marking to all the variant types of the current
structure type.
PR c/120353
gcc/c/ChangeLog:
* c-decl.cc (finish_struct): Copy TYPE_INCLUDES_FLEXARRAY marking
to all the variant types of the current structure type.
Jennifer Schmitz [Mon, 21 Jul 2025 17:07:20 +0000 (10:07 -0700)]
aarch64: Add tuning model for Olympus core.
This patch adds a new tuning model for the NVIDIA Olympus core.
The values used here are based on the Software Optimization Guide
that will be published imminently.
Bootstrapped and tested on aarch64-linux-gnu, no regression.
OK for trunk?
OK to backport to GCC 15?
Signed-off-by: Jennifer Schmitz <jschmitz@nvidia.com> Co-Authored-By: Dhruv Chawla <dhruvc@nvidia.com>
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (olympus): Use olympus tuning
model.
* config/aarch64/aarch64.cc: Include olympus.h.
* config/aarch64/tuning_models/olympus.h: New file.
Jakub Jelinek [Wed, 30 Jul 2025 11:23:56 +0000 (13:23 +0200)]
c++: Make __extension__ silence -Wlong-long pedwarns/warnings [PR121133]
The PR13358 r0-92909 change changed the diagnostics on long long
in C++ (either with -std=c++98 or -Wlong-long), but unlike the
C FE we unfortunately warn even in the
__extension__ long long a;
etc. cases. The C FE in that case in
disable_extension_diagnostics saves and clears not just
pedantic flag but also warn_long_long (and several others), while
C++ FE only temporarily disables pedantic.
The following patch makes it behave like the C FE in this regard,
though (__extension__ 1LL) still doesn't work because of the
separate lexing (and I must say I have no idea how to fix that).
Or do you prefer a solution closer to the C FE, cp_parser_extension_opt
saving the values into a bitfield and have another function to restore
the state (or use RAII)?
2025-07-30 Jakub Jelinek <jakub@redhat.com>
PR c++/121133
* parser.cc (cp_parser_unary_expression): Adjust
cp_parser_extension_opt caller and restore warn_long_long.
(cp_parser_declaration): Likewise.
(cp_parser_block_declaration): Likewise.
(cp_parser_member_declaration): Likewise.
(cp_parser_extension_opt): Add SAVED_LONG_LONG argument,
save previous warn_long_long state into it and clear it
for __extension__.
* g++.dg/warn/pr121133-1.C: New test.
* g++.dg/warn/pr121133-2.C: New test.
* g++.dg/warn/pr121133-3.C: New test.
* g++.dg/warn/pr121133-4.C: New test.
testsuite: Fix gcc.target/powerpc/vsx-builtin-7.c test [PR119382]
The test vsx-builtin-7.c failed on powerpc64le-linux due to Identical
Code Folding (ICF) merging the functions insert_di_0_v2 and insert_di_0.
This behavior was introduced by commit r15-7961-gdc47161c1f32c3, which
enhanced alias analysis in ao_compare::compare_ao_refs, enabling the
compiler to identify and optimize structurally identical functions. As a
result, the compiler replaced insert_di_0_v2 with a tail call to
insert_di_0, altering the expected test behavior.
This patch adds -fno-ipa-icf to the test's dg-options to disable ICF,
avoiding function merging and ensuring the test executes correctly.
Robert Dubner [Wed, 23 Jul 2025 12:44:54 +0000 (08:44 -0400)]
cobol: Tweak adjustments to location_t of GENERIC nodes for PERFORM.
COBOL has a group of PERFORM statements that require careful adjustments to
the location_t elements of the GENERIC nodes so that the COBOL-aware version
of GDB behaves properly. These changes are in service of that goal.
Robert Dubner [Mon, 21 Jul 2025 16:58:47 +0000 (12:58 -0400)]
cobol: Improved linemap and diagnostic handling; PIC validation. [PR120402]
Implementation of PICTURE string validation for PR120402. Expanded some printf
format attributes. Improved debugging and diagnostic messages. Improved
linemap and line location tracking in support of diagnostic messages and
location_t tagging of GENERIC nodes for improved GDB-COBOL performance.
Assorted changes to eliminate cppcheck warnings.
Co-Authored-By: James K. Lowden <jklowden@cobolworx.com> Co-Authored-By: Robert Dubner <rdubner@symas.com>
gcc/cobol/ChangeLog:
PR cobol/120402
* Make-lang.in: Elminate commented-out scripting.
* cbldiag.h (_CBLDIAG_H): Change #if 0 to #if GCOBOL_GETENV
(warn_msg): Add printf attributes.
(location_dump): Add debugging message.
* cdf.y: Improved linemap tracking.
* genapi.cc (treeplet_fill_source): const attribute for formal parameter.
(insert_nop): Created to consolidate var_decl_nop writes.
(build_main_that_calls_something): Move generation to the end of executable.
(level_88_helper): Formatting.
(parser_call_targets_dump): Formatting.
(function_pointer_from_name): const attribute for formal parameter.
(parser_initialize_programs): const attribute for formal parameter.
(parser_statement_begin): Improved linemap handling.
(section_label): Improved linemap handling.
(paragraph_label): Improved linemap handling.
(pseudo_return_pop): Improved linemap handling.
(leave_procedure): Formatting.
(parser_enter_section): Improved linemap handling.
(parser_enter_paragraph): Improved linemap handling.
(parser_perform): Formatting.
(parser_leave_file): Move creation of main() to this routine.
(parser_enter_program): Move creation of main from here to leave_file.
(parser_accept): Formatting. const attribute for formal parameter.
(parser_accept_command_line): const attribute for formal parameter.
(parser_accept_command_line_count): const attribute for formal parameter.
(parser_accept_envar): Likewise.
(parser_set_envar): Likewise.
(parser_display): Likewise.
(get_exhibit_name): Implement EXHIBIT verb.
(parser_exhibit): Likewise.
(parser_sleep): const attribute for formal parameter.
(parser_division): Improved linemap handling.
(parser_classify): const attribute for formal parameter.
(create_iline_address_pairs): Improved linemap handling.
(parser_perform_start): Likewise.
(perform_inline_until): Likewise.
(perform_inline_testbefore_varying): Likewise.
(parser_perform_until): Likewise.
(parser_perform_inline_times): Likewise.
(parser_intrinsic_subst): const attribute for formal parameter.
(parser_file_merge): Formatting.
(create_and_call): Improved linemap handling.
(mh_identical): const attribute for formal parameter.
(mh_numeric_display): const attribute for formal parameter.
(mh_little_endian): Likewise.
(mh_source_is_group): Likewise.
(psa_FldLiteralA): Formatting.
* genapi.h (parser_accept): const attribute for formal parameter.
(parser_accept_envar): Likewise.
(parser_set_envar): Likewise.
(parser_accept_command_line): Likewise.
(parser_accept_command_line_count): Likewise.
(parser_add): Likewise.
(parser_classify): Likewise.
(parser_sleep): Likewise.
(parser_exhibit): Likewise.
(parser_display): Likewise.
(parser_initialize_programs): Likewise.
(parser_intrinsic_subst): Likewise.
* gengen.cc (gg_assign): Improved linemap handling.
(gg_add_field_to_structure): Likewise.
(gg_define_from_declaration): Likewise.
(gg_build_relational_expression): Likewise.
(gg_goto_label_decl): Likewise.
(gg_goto): Likewise.
(gg_printf): Likewise.
(gg_fprintf): Likewise.
(gg_memset): Likewise.
(gg_memchr): Likewise.
(gg_memcpy): Likewise.
(gg_memmove): Likewise.
(gg_strcpy): Likewise.
(gg_strcmp): Likewise.
(gg_strncmp): Likewise.
(gg_return): Likewise.
(chain_parameter_to_function): Likewise.
(gg_define_function): Likewise.
(gg_get_function_decl): Likewise.
(gg_call_expr): Likewise.
(gg_call): Likewise.
(gg_call_expr_list): Likewise.
(gg_exit): Likewise.
(gg_abort): Likewise.
(gg_strlen): Likewise.
(gg_strdup): Likewise.
(gg_malloc): Likewise.
(gg_realloc): Likewise.
(gg_free): Likewise.
(gg_set_current_line_number): Likewise.
(gg_get_current_line_number): Likewise.
(gg_insert_into_assembler): Likewise.
(token_location_override): Likewise.
(gg_token_location): Likewise.
* gengen.h (location_from_lineno): Likewise.
(gg_set_current_line_number): Likewise.
(gg_get_current_line_number): Likewise.
(gg_token_location): Likewise.
(current_token_location): Likewise.
(current_location_minus_one): Likewise.
(current_location_minus_one_clear): Likewise.
(token_location_override): Likewise.
* genmath.cc (fast_divide): const attribute for formal parameter.
* genutil.cc (get_and_check_refstart_and_reflen): Likewise.
(get_data_offset): Likewise.
(refer_refmod_length): Likewise.
(refer_offset): Likewise.
(refer_size): Likewise.
(refer_size_dest): Likewise.
(refer_size_source): Likewise.
(qualified_data_location): Likewise.
* genutil.h (refer_offset): Likewise.
(refer_size_source): Likewise.
(refer_size_dest): Likewise.
(qualified_data_location): Likewise.
* parse.y: EVALUATE token; Implement EXHIBIT verb;
Improved linemap handling.
* parse_ante.h (input_file_status_notify): Improved linemap handling.
(location_set): Likewise.
* scan.l: PICTURE string validation.
* scan_ante.h (class picture_t): PICTURE string validation.
(validate_picture): Likewise.
* symbols.cc (symbol_currency): Revised default currency handling.
* symbols.h (symbol_currency): Likewise.
* util.cc (location_from_lineno): Improved linemap handling.
(current_token_location): Improved linemap handling.
(current_location_minus_one): Improved linemap handling.
(current_location_minus_one_clear): Improved linemap handling.
(gcc_location_set_impl): Improved linemap handling.
(warn_msg): Improved linemap handling.
* util.h (cobol_lineno): Improved linemap handling.
projects / thirdparty / gcc.git / log
