Marek Vasut [Sun, 7 Sep 2025 01:00:47 +0000 (03:00 +0200)]
board: dhelectronics: Use isascii() before isprint() in dh_read_eeprom_id_page()
The isprint() checks printability across all 256 characters, some of the
upper 128 characters are printable and produce artifacts on UART. Call
isascii() first to only consider the bottom 7bit ASCII characters as
printable, and then check their printability using isprint(). This fixes
a rare misprint in case the ID page content is uninitialized or corrupted.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Marek Vasut [Sun, 7 Sep 2025 01:00:46 +0000 (03:00 +0200)]
board: dhelectronics: Check pointer before access in dh_get_value_from_eeprom_buffer()
The eip pointer in dh_get_value_from_eeprom_buffer() might be NULL.
The current NULL pointer check happens too late, after the eip was
accessed in variable assignment. Reorder the two, so the NULL pointer
check happens first, and any access second, otherwise the access may
trigger a hang or other undefined behavior.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Tom Rini [Wed, 17 Sep 2025 13:52:31 +0000 (07:52 -0600)]
Merge patch series "Hyperflash boot fixes for j721e/j7200"
Anurag Dutta <a-dutta@ti.com> says:
This series introdues a couple of small fixes that involves
enabling hyperflash at R5 SPL and u-boot proper stage and
Kconfig changes that are required for HBMC boot on j721e/j7200
Michal Simek [Wed, 17 Sep 2025 07:22:18 +0000 (09:22 +0200)]
xilinx: Disable SPL_OS_BOOT for Zynq and ZynqMP
The commit 210702ae6ce8 ("spl: spi: fix falcon mode for spi boot") fixed
the logic of spl_start_uboot() where 0 means OS boot and 1 means u-boot.
Zynq/ZynqMP enable OS_BOOT by default but it was never really be used
that's why disable it to boot via U-Boot phase all the time.
Signed-off-by: Michal Simek <michal.simek@amd.com>
board: ti: am57xx: Remove "ti/omap/" from name_fit_config
Commit 649f4a7d3ca7 ("board: ti: am57xx: Set fdtfile from C code
instead of findfdt script") prepends "ti/omap/" to the actual name
of the fdtfile whereas fit image boot needs exact dtb name. So, remove
"ti/omap" from name_fit_config by substituting it with an empty string.
Fixes: 649f4a7d3ca7 ("board: ti: am57xx: Set fdtfile from C code instead of findfdt script") Signed-off-by: Anurag Dutta <a-dutta@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Alice Guo [Fri, 5 Sep 2025 18:22:04 +0000 (02:22 +0800)]
imx95_evk: Restore support for i.MX95 A0 silicon
This patch is used to restore support for i.MX95 A0 silicon. To avoid
duplicating defconfig, imx95.config is added and can be shared between
imx95_a0_19x19_evk_defconfig and imx95_19x19_evk_defconfig.
container.cfg and imximage.cfg are used to created .cfgout files that
are be passed to mkimage with -n to build flash.bin. Now they have been
deleted and replaced by adding their content to properties of node which
type is nxp-imx9image under binman node.
Fixes: 9936724aa9b ("imx95_evk: Add i.MX95 B0 support") Signed-off-by: Alice Guo <alice.guo@nxp.com> Tested-By: Tim Harvey <tharvey@gateworks.com> # imx95-19x19-evk (rA0)
Alice Guo [Fri, 5 Sep 2025 18:22:03 +0000 (02:22 +0800)]
binman: add a new entry type to support .bin file generation for the i.MX95 platform
To support passing specific commands defined in enum imx8image_cmd to
the imx8image_copy_image() function, this patch introduces a new entry
type nxp-imx9image. This entry generates a plain text data file
containing the relevant commands, enabling flexible configuration during
image creation.
Per recent discussion [1] product IDs VF7110A or VF7110B from EEPROM are
sufficient to select for VisionFive 2 1.2a or VisionFive 2 1.3b boards.
There are no VisionFive 2 products with mixed-case product IDs in EERPOM
so factor out the unnecessary select case conditional.
Marek Vasut [Mon, 15 Sep 2025 00:49:05 +0000 (02:49 +0200)]
ARM: stm32: Perform node compatible check for KS8851 early
Check the compatible string of ethernet1 node for KS8851 very early on,
before calling uclass_get_device_by_of_path() which might initialize
the device and possibly attempt to configure MAC address into device
which is not KS8851. Doing the compatibility check early prevent this.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Marek Vasut [Mon, 15 Sep 2025 00:53:04 +0000 (02:53 +0200)]
net: dwc_eth_qos: Fix support for stm32mp2 platform
The layout of SYSCFG_ETHnCR on STM32MP25xx is slightly different yet again.
Add missing swizzling to program the correct register with the correct content.
Fixes: 20afca89ed53 ("net: dwc_eth_qos: add support of stm32mp2 platform") Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Reviewed-by: Christophe ROULLIER<christophe.roullier@foss.st.com>
Marek Vasut [Sat, 6 Sep 2025 23:00:01 +0000 (01:00 +0200)]
clk: stm32: Pass udevice pointer to clk_register_composite()
The clk_register_composite() does clk_resolve_parent_clk() look up,
which requires valid udevice pointer. Do not pass NULL, pass a valid
device pointer to prevent hang on registering ck_usbo_48m clock on
STM32MP13xx.
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Ye Li [Fri, 12 Sep 2025 09:41:11 +0000 (17:41 +0800)]
arm: armv8: Fix spl recover data section broken
SPL recover data section is broken which causes reboot failure on
some i.MX platforms (iMX8QM/iMX95).
The global variable cold_reboot_flag is assigned to weak reset_flag
function which always return 1, so restore never been executed in
warm reboot.
Fixes: 1c37e59bfbba ("arm: armv8: Improve SPL data save and restore implementation") Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
spl_start_uboot is a board overridable function that switches to falcon
boot mode on return value of 0.
Though for SPI, the falcon boot mode was being enabled on return value
of 1 which is not the correct behaviour. Therefore this patch fixes it
to the expected boot flow.
Tom Rini [Thu, 11 Sep 2025 16:03:12 +0000 (10:03 -0600)]
Merge patch series "Fix dma_addr_t for R5 SPL"
Anshul Dalal <anshuld@ti.com> says:
On various TI's K3 platforms boot failure was observed on SPI NOR since the
commit 5609f200d062 ("arm: Kconfig: enable LTO for ARCH_K3"). This issue was
root caused to stack corruption by the 'udma_transfer' function. Where the local
variable 'paddr' of type 'dma_addr_t' was being written to as a 64-bit value
which overwrote the stack frame of the caller (dma_memcpy) as only 32-bits had
been reserved for paddr on the stack, specifically the r4 register in the frame
of dma_memcpy was being overwritten with a 0.
drivers/dma/ti/k3-udma.c:2192:
int udma_transfer(...)
{
...
dma_addr_t paddr = 0;
...
/* paddr was written to as 64-bit value here */
udma_poll_completion(uc, &paddr);
}
drivers/dma/dma-uclass.c:234:
int dma_memcpy(...)
{
dma_addr_t destination;
dma_addr_t source;
int ret;
...
/* This call resolves to udma_transfer */
ret = ops->transfer(...);
Enabling LTO changed how gcc mapped local variables of dma_memcpy to CPU
registers, where earlier the bug was hidden since the overwritten register
'r4' was allotted to 'ret' but was allotted to 'destination' once LTO was
enabled. And since the overwritten value was 0, the bug remained undetected
as it just meant ret was 0, but having 'destination' set to 0 caused
dma_unmap_single to fail silently leading to boot failures.
The fix entails enabling DMA_ADDR_T_64BIT which changes dma_addr_t from u32 to
u64 for the R5 SPL thus reserving enough space for 'paddr' to prevent the
overflow.
ARCH_K3 encompasses both 32 and 64-bit cores on the same SoC, though the
DMA addresses are always 64-bit in size.
With the current implementation, the R5 SPL uses a u32 for dma_addr_t
which leads to data overflow when functions such as k3_nav_*_pop_mem try
to write a 64-bit address to dma_addr_t variable.
In certain cases it leads to stack corruption which manifest as boot
failures on certain compilers, such as SPI boot on GCC 14.2 or 13.3.
Therefore this patch selects CONFIG_DMA_ADDR_T_64BIT for all ARCH_K3.
dma_addr_t is used to store any valid DMA address which might not
necessarily be the same size as host architecture's word size. Though
various typecasts in k3's dma and usb driver expect dma_addr_t to be the
same size as the word size.
This leads the compiler to throw a "cast from pointer to integer of
different size" warning when the condition is not met, for example when
enabling CONFIG_DMA_ADDR_T_64BIT for the R5 core.
Therefore this patch fixes the typecasts by using 'uintptr_t' as an
intermediary type which is guaranteed to be the same size as void* on
the host architecture. Thus, eliminating the compiler warning.
env: fix config dependency for ENV_OFFSET_REDUND_RELATIVE_END
Since commit 5fb88fa725 "env: Rename SYS_REDUNDAND_ENVIRONMENT to ENV_REDUNDANT"
the option SYS_REDUNDAND_ENVIRONMENT is no longer available and should be
renamed to ENV_REDUNDANT.
Fixes: 95f03ee65c0e ("env: mmc: fix offsets relative to the end of the partition") Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Tom Rini <trini@konsulko.com>
The SPI flash driver does not build without SPI support enabled.
Fixes: 4151f4f822bb ("spl: Rework and tighten some dependencies") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Acked-by: Peng Fan <peng.fan@nxp.com> Acked-by: Anshul Dalal <anshuld@ti.com>
Enable CONFIG_DNS for visionfive2 board target. With CONFIG_PROT_DNS_LWIP
enabled and CONFIG_CMD_DNS disabled this restores DNS functionality
displaced by LwIP DNS refactoring during the merge window.
Patrick Rudolph [Wed, 3 Sep 2025 07:05:01 +0000 (09:05 +0200)]
configs: Fix crash on coreboot x86
Booting u-boot as payload with coreboot's main branch is currently broken
since commit [1] on x86 as U-boot assumes the active GDT matches what
U-Boot would have installed in start16.S.
Make no assumptions and always load the GDT when building as coreboot
payload to make sure the segment registers are actually matching the GDT.
Fixes #GP seen when booting U-Boot as coreboot payload.
include: env: ti: Use .env for environment variables
Add omap common environment variables to .env. We retain the old-style C
environment .h files to maintain compatibility with other omap devices that
have not moved to using .env yet.
Marek Vasut [Wed, 3 Sep 2025 11:23:23 +0000 (13:23 +0200)]
arm64: renesas: r8a779g3: Use $loadaddr in bootcmd on Retronix R-Car V4H Sparrow Hawk board
Avoid use of hard-coded address in boot command, instead use $loadaddr
which is the default load address. This improves consistency of the
environment on this board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Wed, 3 Sep 2025 11:23:57 +0000 (13:23 +0200)]
ARM: renesas: Enable CONFIG_ENV_VARS_UBOOT_CONFIG on all boards
The CONFIG_ENV_VARS_UBOOT_CONFIG extends U-Boot environment with
variables arch/board/board_name/soc/vendor, which can be used to
discern different devices from each other based purely on U-Boot
environment variables.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Andrew Goodbody [Mon, 1 Sep 2025 15:13:14 +0000 (16:13 +0100)]
spi: exynos: Remove extra term from test
In spi_rx_tx there comes a test for execution of a code block that
allows execution if rxp is not NULL or stopping is true. However all the
code in this block relies on rxp being valid so allowing entry just if
stopping is true does not make sense. So remove this from the test
expression leaving just a NULL check for rxp.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Andrew Goodbody [Thu, 7 Aug 2025 14:41:18 +0000 (15:41 +0100)]
pinctrl: rzg2l: Variable may not have been assigned to
In rzg2l_pinconf_set and rzg2l_get_pin_muxing if the call to
rzg2l_selector_decode fails then the variable pin may not have been
assigned to. Remove the use of pin from the error message. Also update
the error message to show the invalid selector used instead of port
which will be the error code returned.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Paul Barker <paul@pbarker.dev> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Henrik Grimler [Fri, 22 Aug 2025 18:54:38 +0000 (20:54 +0200)]
ARM: exynos: use correct exynos4210-origen SoC in Kconfig
There exists both a Origen board based on exynos4210, and a board
based on exynos4412. U-boot only supports the one based on exynos
4210, but Kconfig string was accidentally written as Exynos4412 Origen
in previous migration to Kconfig. Fix the string to clear up
confusion, and to not give the impression that both types of Origen
boards are supported.
Fixes: 72df68cc6b73 ("exynos: kconfig: move board select menu and common settings") Signed-off-by: Henrik Grimler <henrik@grimler.se> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
ARM: tegra20: transformer: fix Hall sensor behavior
Hall sensor found in SL101 is not used for closed dock detection as on
TF101 or TF101G, it is used to detect if keyboard slider is out. To address
this, lets move Lid sensor switch into TF101/G trees and add Tablet mode
switch into SL101 tree.
Sam Protsenko [Wed, 6 Aug 2025 22:27:10 +0000 (17:27 -0500)]
configs: e850-96: Enable Ethernet
LAN9514 is a chip on E850-96 board which acts as a USB host hub and
Ethernet controller. It's controlled via USB lines when DWC3 is
configured to be in USB host role (by setting the "dr_mode" property to
"host" value in e850-96 dts file).
Enable network support and LAN9514 chip support. This makes Ethernet
functional on E850-96 board.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 6 Aug 2025 22:27:09 +0000 (17:27 -0500)]
configs: e850-96: Enable USB host support
Exynos850 SoC has a dual-role USB controller which can be configured in
USB host role. As it's the only one USB controller on the board, it's
shared between "device" USB connector (micro-USB) and host USB
connectors. The hardware automatically powers on the host related parts
when the micro-USB cable (for device role) is being disconnected. Also,
as U-Boot lacks dynamic USB role switching capability, the only way to
switch the role at the moment is to modify "dr_mode" property in
U-Boot's device tree file here:
Sam Protsenko [Wed, 6 Aug 2025 22:27:08 +0000 (17:27 -0500)]
configs: e850-96: Disable CONFIG_DEFAULT_FDT_FILE
Linux kernel should use some separate device tree obtained from another
source anyway. For example the dtb file can be read from /boot directory
in eMMC rootfs partition, either by GRUB or U-Boot. Using U-Boot's
device tree blob to provide it to the kernel (when
CONFIG_DEFAULT_FDT_FILE is set and nobody else overrides this choice)
might lead to undesired effects when booting the OS. For example, if a
user sets "dr_mode" property to "host" value in U-Boot's dts to enable
USB host capabilities in U-Boot, it might confuse usb-conn-gpio driver
in Linux kernel later like this:
platform connector: deferred probe pending: usb-conn-gpio:
failed to get role switch
Disable CONFIG_DEFAULT_FDT_FILE option to avoid any possible confusion.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 6 Aug 2025 22:27:07 +0000 (17:27 -0500)]
board: samsung: e850-96: Add bootdev var to choose boot device
Provide a way for the user to select which storage to load the LDFW
firmware from, by setting the corresponding environment variables:
- bootdev: block device interface name
- bootdevnum: block device number
- bootdevpart: partition number
This might be useful when the OS is flashed and booted from a different
storage device than eMMC (e.g. USB flash drive). In this case it should
be sufficient to just set:
=> setenv bootdev usb
=> env save
assuming that the USB drive layout follows the same partitioning scheme
as defined in $partitions.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 6 Aug 2025 22:27:06 +0000 (17:27 -0500)]
board: samsung: e850-96: Extract device info from fw loading code
Make it possible to provide the information about storage device where
LDFW firmware resides to the firmware loading routine. The firmware
loader code shouldn't have that data hard-coded anyway, and it also
allows for implementing more dynamic behavior later, like choosing the
storage device containing LDFW via some environment variables.
No functional change.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Make use of PMIC configuration routines and enable all LDOs that might
be useful for bootloader and kernel. The most crucial regulator being
enabled at the moment is LDO24 which provides power to LAN9514 chip.
That makes Ethernet controller and USB hub functional.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 6 Aug 2025 22:27:04 +0000 (17:27 -0500)]
board: samsung: e850-96: Add PMIC code
Add functions for configuring voltage regulators on S2MPU12 PMIC chip
for E850-96 board. The chip is accessed by commanding APM core (via
ACPM IPC protocol) to perform corresponding transfers over I3C bus.
The most important regulator being set up is LDO24 used for LAN9514 chip
power. As LAN9514 implements USB hub and Ethernet controller
functionality, it's crucial to enable and configure LDO24 to be able to
use it further. While at it, configure the rest of regulators that might
be needed later, both in the bootloader and in kernel.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 6 Aug 2025 22:27:03 +0000 (17:27 -0500)]
board: samsung: e850-96: Add ACPM code
Add functions to access I3C bus via APM (Active Power Management) core
by using ACPM IPC protocol. It will be further used for configuring PMIC
chip voltage regulators.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Sam Protsenko [Wed, 6 Aug 2025 22:27:02 +0000 (17:27 -0500)]
board: samsung: e850-96: Set ethaddr
Set the environment variable for Ethernet MAC address (ethaddr). Use the
SoC ID to make sure it's unique. It'll be formatted in a way that
follows the consecutive style of the serial number ("serial#" variable),
i.e.:
Enable support for Exynos850 SoC in DWC3 host glue layer driver.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Marek Vasut <marek.vasut@mailbox.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Andrew Goodbody [Wed, 23 Jul 2025 16:04:41 +0000 (17:04 +0100)]
clk: exynos: Fix always true test
In exynos7420_peric1_get_rate the variable ret is declared as an
'unsigned int' but is then used to receive the return value of
clk_get_by_index which returns an int. The value of ret is then tested
for being less than 0 which will always fail for an unsigned variable.
Fix this by declaring ret as an 'int' so that the test for the error
condition is valid.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Adriano Carvalho [Mon, 25 Aug 2025 22:32:28 +0000 (23:32 +0100)]
doc: Fix obvious typos and minor improvements
These are fixes to what looks like obvious typos.
Some minor improvments are also included, such as:
- Write "symbolic link" instead of symlink
- Correct capitalization for LLVM (all caps)
- Remove dead link and surrounding sentence
Tom Rini [Tue, 12 Aug 2025 18:01:32 +0000 (12:01 -0600)]
efi_loader: Make EFI_VARIABLES_PRESEED depend on !COMPILE_TEST
When doing compile testing build we cannot rely on having a valid file
for EFI_VAR_SEED_FILE to exist, so disable this option when doing
compile tests.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Andrew Goodbody [Mon, 11 Aug 2025 12:05:15 +0000 (13:05 +0100)]
efi: serial: Use correct EFI status type
int is not sufficient to hold and test the return from an EFI function
call. Use efi_status_t instead so that the test can work as expected.
This issue was found by Smatch.
Fixes: 275854baeeec ("efi: Add a serial driver") Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Jonas Karlman [Mon, 21 Jul 2025 22:07:19 +0000 (22:07 +0000)]
rockchip: rk3588-generic: Move usb nodes to board dts
After the commit 7a53abb18325 ("rockchip: rk3588: Remove USB3 DRD nodes
in u-boot.dtsi") was merged for v2024.10 there is no reason to keep the
usb nodes for the Generic RK3588 board in the board u-boot.dtsi.
Move usb related nodes from board u-boot.dtsi to main board device tree.
While at it, also drop use of the usb3-phy as we only want to enable the
usb2-phy to be compatible with as many boards as possible.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 21 Jul 2025 22:07:18 +0000 (22:07 +0000)]
rockchip: rk3576: Disable USB3OTG0 U3 port early
The RK3576 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (USBDP PHY).
Some board designs may not use the USBDP PHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.
Change to always disable the USB3OTG0 U3 port early and leave it to the
USBDP PHY driver to re-enable the U3 port when a usb3-phy is described
in the board device tree.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 21 Jul 2025 22:07:17 +0000 (22:07 +0000)]
rockchip: rk3588: Disable USB3OTG U3 ports early
The RK3588 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (USBDP PHY).
Some board designs may not use the USBDP PHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.
Change to always disable the USB3OTG U3 ports early and leave it to the
USBDP PHY driver to re-enable the U3 port when a usb3-phy is described
in the board device tree.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 21 Jul 2025 22:07:13 +0000 (22:07 +0000)]
phy: rockchip: naneng-combphy: Simplify init ops
The init ops for Rockchip COMBPHY driver is more complex than it needs
to be, e.g. declaring multiple init functions that only differ in the
error message.
Simplify the init ops based on code from the Linux mainline driver.
This change also ensure that errors returned from combphy_cfg() and
reset_deassert_bulk() is propertly propagated to the caller. No other
runtime change is expected with this simplication.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Generic PHY reference counting helps ensure driver ops for init/exit and
power on/off are called at correct state. For this to work the PHY
driver must initialize PHY-id to a persistent value in of_xlate ops.
The Rockchip COMBPHY driver does not initialize the PHY-id field, this
typically lead to use of unshared reference counting among different
struct phy instances.
Initialize the PHY-id in of_xlate ops to ensure use of shared reference
counting among all struct phy instances.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 21 Jul 2025 22:07:11 +0000 (22:07 +0000)]
phy: rockchip: usbdp: Simplify init ops
With working shared reference counting for Generic PHY ops there is no
need for the Rockchip USBDP PHY driver to keep its own status (reference
counting) handling.
Simplify the init ops now that shared reference counting is working.
This also removes the unused mode_change handling as part of the
simplication.
No runtime change is expected with this simplication.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Generic PHY reference counting helps ensure driver ops for init/exit and
power on/off are called at correct state. For this to work the PHY
driver must initialize PHY-id to a persistent value in of_xlate ops.
The Rockchip USBDP PHY driver does not initialize the PHY-id field, this
typically lead to use of unshared reference counting among different
struct phy instances.
Initialize the PHY-id in of_xlate ops to ensure use of shared reference
counting among all struct phy instances.
E.g. on a ROCK 5B following could be observed:
=> usb start
starting USB...
[...]
Bus usb@fc400000: 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
=> usb reset
resetting USB...
[...]
rockchip_udphy phy@fed90000: cmn ana lcpll lock timeout
rockchip_udphy phy@fed90000: failed to init usbdp combophy
rockchip_udphy phy@fed90000: PHY: Failed to init phy@fed90000: -110.
Can't init PHY1
Bus usb@fc400000: probe failed, error -110
scanning usb for storage devices... 0 Storage Device(s) found
With shared reference counting this is fixed:
=> usb reset
resetting USB...
[...]
Bus usb@fc400000: 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andrew Goodbody [Thu, 31 Jul 2025 11:46:10 +0000 (12:46 +0100)]
mmc: rockchip_sdhci: Do not test unsigned for being less than 0
In rockchip_sdhci_execute_tuning the variable tuning_loop_counter is
tested for being less than 0. Ensure that it is a signed type by
declaring it as s8 instead of char.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Wed, 13 Aug 2025 14:07:43 +0000 (16:07 +0200)]
power: rk8xx: allow to customize RK806 reset mode
The RK806 PMIC has a bitfield for configuring the restart/reset behavior
(which I assume Rockchip calls "function") whenever the PMIC is reset
either programmatically (c.f. DEV_RST in the datasheet) or via PWRCTRL
or RESETB pins.
For RK806, the following values are possible for RST_FUN:
0b00 means "Restart PMU"
0b01 means "Reset all the power off reset registers, forcing
the state to switch to ACTIVE mode"
0b10 means "Reset all the power off reset registers, forcing
the state to switch to ACTIVE mode, and simultaneously
pull down the RESETB PIN for 5mS before releasing"
0b11 means the same as for 0b10 just above.
This adds the appropriate logic in the driver to parse the new
rockchip,reset-mode DT property to pass this information. It just
happens that the values in the binding match the values to write in the
bitfield so no mapping is necessary.
For backward compatibility reasons, if the property is missing we set it
to 0b10 (i.e. BIT(7)) like before this commit was merged instead of
leaving it untouched like in the kernel driver.
Note that this does nothing useful for U-Boot at the moment as the ways
to reset the device (e.g. via `reset` command) doesn't interact with the
RK8xx PMIC and simply does a CPU reset.
Considering the upstream Linux kernel left this register untouched until
(assumed) v6.17[1], this is useful for cases in which the U-Boot
bootloader has this patch (and running with a DT with
rockchip,reset-mode property set) and running an upstream kernel before
(assumed) v6.17, or alternatively later without the property in the
kernel DT.
Quentin Schulz [Wed, 13 Aug 2025 14:07:42 +0000 (16:07 +0200)]
arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Tiger
The bootloader for RK3588 Tiger currently forces the PMIC reset behavior
(stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X
which is incorrect for our devices.
It is required to restart the PMU as otherwise the companion
microcontroller cannot detect the PMIC (and by extension the full
product and main SoC) being rebooted which is an issue as that is used
to reset a few things like the PWM beeper and watchdogs.
Let's add the new rockchip,reset-mode property to make sure the PMIC
reset behavior is the expected one.
Quentin Schulz [Wed, 13 Aug 2025 14:07:41 +0000 (16:07 +0200)]
arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Jaguar
The bootloader for RK3588 Jaguar currently forces the PMIC reset
behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC)
to 0b1X which is incorrect for our devices.
It is required to restart the PMU as otherwise the companion
microcontroller cannot detect the PMIC (and by extension the full
product and main SoC) being rebooted which is an issue as that is used
to reset a few things like the PWM beeper and watchdogs.
Let's add the new rockchip,reset-mode property to make sure the PMIC
reset behavior is the expected one.
Quentin Schulz [Wed, 13 Aug 2025 14:07:40 +0000 (16:07 +0200)]
arm64: dts: rockchip: add header for RK8XX PMIC constants
To make it easier to read the device tree, let's add constants for the
rockchip,reset-mode property values that are currently only applicable
to RK806 PMIC.
Quentin Schulz [Wed, 13 Aug 2025 14:07:39 +0000 (16:07 +0200)]
dt-bindings: mfd: rk806: Allow to customize PMIC reset mode
The RK806 PMIC allows to configure its reset/restart behavior whenever
the PMIC is reset either programmatically or via some external pins
(e.g. PWRCTRL or RESETB).
The following modes exist:
- 0; restart PMU,
- 1; reset all power off reset registers and force state to switch to
ACTIVE mode,
- 2; same as mode 1 and also pull RESETB pin down for 5ms,
For example, some hardware may require a full restart (mode 0) in order
to function properly as regulators are shortly interrupted in this mode.
This is the case for RK3588 Jaguar and RK3588 Tiger which have a
companion microcontroller running on an independent power supply and
monitoring the PMIC power rail to know the state of the main system.
When it detects a restart, it resets its own IPs exposed to the main
system as if to simulate its own reset. Failing to perform this fake
reset of the microcontroller may break things (e.g. watchdog not
automatically disabled, buzzer still running until manually disabled,
leftover configuration from previous main system state, etc...).
Some other systems may be depending on the power rails to not be
interrupted even for a small amount of time[1].
This allows to specify how the PMIC should perform on the hardware level
and may differ between hardware designs, so a DT property seems
warranted. I unfortunately do not see how this could be made generic
enough to make it a non-vendor property.
Jonas Karlman [Wed, 30 Jul 2025 23:52:45 +0000 (23:52 +0000)]
rockchip: rk3528: Disable USB3OTG U3 port early
The RK3528 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (COMBPHY).
Some board designs may not use the COMBPHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.
Change to always disable the USB3OTG U3 port early and leave it to the
COMBPHY driver to re-enable the U3 port when a usb3-phy is described in
the board device tree.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
projects / thirdparty / u-boot.git / log
