Fix PR21404 - assertion fail when calculating symbol size
Fix a host of problems related to adjustment of
symbol values and sizes when relaxing for avr.
1. Adjust symbol size first before adjusting symbol
value. Otherwise, a symbol whose value just got adjusted to the
relaxed address also ends up getting resized. See pr21404-1.s.
2. Reduce symbol sizes only if their span is below an
alignment boundary. Otherwise, the size gets decremented once when the
actual instruction is relaxed and padding bytes are added, and again
when the padding bytes are deleted (if padding ends up being unnecessary).
pr21404-2.s addresses that, and this bug is really the root cause of PR21404.
3. Adjust all symbol values before an alignment boundary.
Previous code did not adjust symbol values if they fell in the
would-be padded area, resulting in incorrect symbol values in some
cases (see pr21404-3.s).
4. Increase symbol sizes if alignment directives require so.
As pr21404-4.s shows
.global nonzero_sym
L1:
jmp L1
nonzero_sym:
nop
nop
.p2align 2
.size nonzero_sym, .-nonzero_sym
The two nops satisfy the 4 byte alignment at assembly time and
therefore the size of nonzero_sym is 4. Relaxation shortens
the 4 byte jmp to a 2 byte rjmp, and to satisfy 4 byte alignment
the code places 2 extra padding bytes after the nops, increasing
nonzero_sym's size by 2. This wasn't handled before.
If the assembly code does not have any align directives, then the
boundary is the section size, and symbol values and sizes == boundary
should also get adjusted. To handle that case, add a did_pad variable
and use that to determine whether it should use < boundary or <= boundary.
Also get rid of reloc_toaddr, which is now redundant. toaddr is now not
adjusted to handle the above case - the newly added
did_pad variable does the job.
pr21404-{5,6,7,8} are the same testcases written for local symbols, as
the code handles them slightly differently.
PR ld/21404
* elf32-avr.c (avr_should_move_sym): New function.
(avr_should_reduce_sym_size): Likewise.
(avr_should_increase_sym_size): Likewise.
(elf32_avr_relax_delete_bytes): Adjust symbol values
and sizes by calling new functions.
PR ld/21404
* testsuite/ld-avr/pr21404-1.d: New test.
* testsuite/ld-avr/pr21404-1.s: New test.
* testsuite/ld-avr/pr21404-2.d: New test.
* testsuite/ld-avr/pr21404-2.s: New test.
* testsuite/ld-avr/pr21404-3.d: New test.
* testsuite/ld-avr/pr21404-3.s: New test.
* testsuite/ld-avr/pr21404-4.d: New test.
* testsuite/ld-avr/pr21404-4.s: New test.
* testsuite/ld-avr/pr21404-5.d: New test.
* testsuite/ld-avr/pr21404-5.s: New test.
* testsuite/ld-avr/pr21404-6.d: New test.
* testsuite/ld-avr/pr21404-6.s: New test.
* testsuite/ld-avr/pr21404-7.d: New test.
* testsuite/ld-avr/pr21404-7.s: New test.
* testsuite/ld-avr/pr21404-8.d: New test.
* testsuite/ld-avr/pr21404-8.s: New test.
The use of ra instead of t1 for address construction provides an
opportunity for a microarchitecture to elide the write of the
destination address, and instead read the target address as an
immediate spread across the fused auipc+jalr pair. The link
register ra in the jalr overwrites the target address temporary.
Palmer Dabbelt [Mon, 1 May 2017 17:26:32 +0000 (10:26 -0700)]
RISC-V: Allow 32-bit BFD to handle 64-bit objects
We've been telling people that the riscv32-* and riscv64-* toolchains
are exactly the same, but it turns out we were lying: the riscv32-* BFD
doesn't handle 64-bit objects. This fixes that difference, so the ports
are actually the same.
PR ld/21334: Always call `_bfd_elf_link_renumber_dynsyms' if required
Complement commit e17b0c351f0b ("MIPS/BFD: Respect the ELF gABI dynamic
symbol table sort requirement") and correct an inconsistency in dynamic
symbol accounting data causing an assertion failure in the MIPS backend:
in the course of making a GOT entry in a static binary to satisfy a GOT
relocation present in input, due to the local dynamic symbol count not
having been established.
To do so let backends request `_bfd_elf_link_renumber_dynsyms' to be
always called, rather than where a dynamic binary is linked only, and
then make this request in the MIPS backend.
bfd/
PR ld/21334
* elf-bfd.h (elf_backend_data): Add `always_renumber_dynsyms'
member.
* elfxx-target.h [!elf_backend_always_renumber_dynsyms]
(elf_backend_always_renumber_dynsyms): Define.
(elfNN_bed): Initialize `always_renumber_dynsyms' member.
* elfxx-mips.h (elf_backend_always_renumber_dynsyms): Define.
* elflink.c (bfd_elf_size_dynsym_hash_dynstr): Also call
`_bfd_elf_link_renumber_dynsyms' if the backend has requested
it.
(elf_gc_sweep): Likewise.
ELF/BFD: Limit `_bfd_elf_link_renumber_dynsyms' call in section GC
Consistently call `_bfd_elf_link_renumber_dynsyms' only if linking a
dynamic binary, complementing code in `bfd_elf_size_dynsym_hash_dynstr'
and commit ccabcbe51e85 ("New attempt at fixing MIPS --gc-sections et
al."), <https://sourceware.org/ml/binutils/2005-08/msg00258.html>.
bfd/
* elflink.c (elf_gc_sweep): Only call
`_bfd_elf_link_renumber_dynsyms' if dynamic sections have been
created.
Alan Modra [Thu, 13 Apr 2017 01:14:20 +0000 (10:44 +0930)]
Missing _bfd_error_handler args
* elf32-arm.c (arm_type_of_stub): Supply missing args to "long
branch veneers" error. Fix double space and format message.
* elf32-avr.c (avr_add_stub): Do not pass NULL as %B arg.
* elf64-ppc.c (tocsave_find): Supply missing %B arg.
PR ld/21233: Avoid sweeping forced-undefined symbols in section GC
Complement commit 902e9fc76a0e ("PR ld/20828: Move symbol version
processing ahead of GC symbol sweep"), commit b531344c34b0 ("PR
ld/20828: Reorder the symbol sweep stage of section GC") and commit 81ff47b3a546 ("PR ld/20828: Fix linker script symbols wrongly forced
local with section GC"), and prevent symbols forcibly entered in the
output file with the use of the `--undefined=' or `--require-defined='
linker command line options or the EXTERN linker script command from
being swept in section garbage collection and consequently recorded in
the dynamic symbol table as local entries. This happens in certain
circumstances, where a symbol reference also exists in one of the static
input files, however only in a section which is garbage-collected and
does not make it to the output file, and the symbol is defined in a
dynamic object present in the link.
For example with the `i386-linux' target and the `pr21233.s' and
`pr21233-l.s' sources, and the `pr21233.ld' linker script included with
this change we get:
Symbol table '.dynsym' contains 2 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 00000000 0 OBJECT LOCAL DEFAULT UND bar
$
which makes the run-time `bar' dependency of the `pr21233' executable
different from its corresponding link-time dependency, i.e. the presence
of `libpr21233.so' and its `bar' symbol is required at the link time,
however at the run time a copy of `libpr21233.so' without `bar' will do.
Similarly with `--undefined=' and EXTERN which do not actually require
the reference to the symbol requested to be satisfied with a definition
at the link time, however once the definition has been pulled at the
link time, so it should at the dynamic load time.
as the target is not prepared to handle such a local dynamic symbol.
With this change in effect we get:
$ readelf --dyn-syms pr21233
Symbol table '.dynsym' contains 2 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 00000000 0 OBJECT GLOBAL DEFAULT UND bar
$
instead, for both targets.
ld/
PR ld/21233
* ldlang.c (insert_undefined): Set `mark' for ELF symbols.
Palmer Dabbelt [Wed, 29 Mar 2017 23:05:40 +0000 (16:05 -0700)]
Allow ISA subsets to be disabled
Without this patch, passing "-march=rv64ic -march=rv64i" results in
you getting a "RV64IC" toolchain, which isn't expected.
gas/ChangeLog:
2017-03-30 Palmer Dabbelt <palmer@dabbelt.com>
* config/tc-riscv.c (riscv_clear_subsets): New function.
(riscv_add_subset): Call riscv_clear_subsets and riscv_set_rvc to
clear RVC when it's been previously set.
Palmer Dabbelt [Tue, 21 Mar 2017 15:36:44 +0000 (08:36 -0700)]
Sanitize RISC-V GAS help text, documentation
It looks like I missed the GAS help text when going through all the
documentation last time, so it printed some of the old-format (never
upstream) arguments. I fixed this, and when I went to check doc/ I
noticed it was missing the '-fpic'/'-fno-pic' options.
2017-03-21 Palmer Dabbbelt <palmer@dabbelt.com>
* config/tc-riscv.c (md_show_usage): Remove defuct -m32, -m64,
-msoft-float, -mhard-float, -mno-rvc, and -mrvc options; and don't
print an invalid default ISA string.
* doc/c-riscv.texi (OPTIONS): Add -fpic and -fno-pic options.
Alan Modra [Sun, 26 Mar 2017 21:49:48 +0000 (08:19 +1030)]
PR21303, objdump doesn't show e200z4 insns
PR 21303
opcodes/
* ppc-dis.c (struct ppc_mopt): Comment.
(ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
gas/
* testsuite/gas/ppc/pr21303.d,
* testsuite/gas/ppc/pr21303.s: New test
* testsuite/gas/ppc/ppc.exp: Run it.
Peter Bergner [Thu, 9 Mar 2017 02:49:03 +0000 (20:49 -0600)]
Update -maltivec and -mvsx options to only enable their oldest instructions.
Currently, the -maltivec and -mvsx GAS options enable *all* of the altivec
and vsx instructions respecitively that have ever been added. This is in
constract to GCC's -maltivec and -mvsx options, which only enable the oldest
(ie, first) set of altivec and vsx instructions. This patch changes GAS to
mimic GCC's behaviour with respect to -maltivec and -mvsx and it solves a
problem with trying to assemble the lxvx instruction which is different
between POWER8 and POWER9.
opcodes/
* ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
<vsx>: Do not use PPC_OPCODE_VSX3;
gas/
* testsuite/gas/ppc/altivec2.d (as): Use the -mpower8 option.
(objdump): Use the -Mpower8 option.
Alan Modra [Tue, 7 Mar 2017 00:34:19 +0000 (11:04 +1030)]
PowerPC64 abort due to dynamic relocs on hidden undefweak
ppc64_elf_relocate_section lacked a check which meant that it emitted
dynamic relocs against a hidden undefweak symbol for which no dynamic
relocs had been allocated.
Alan Modra [Mon, 6 Mar 2017 09:09:34 +0000 (19:39 +1030)]
Don't decode powerpc insns with invalid fields
Certain insns have restrictions on fields. For example, the insn
mentioned in the PR, lqarx, must specify an even general purpose
register as its destination and that register cannot appear in
either of the base or index reg fields. This holds even when the RA0
field is 0 (meaning a zero rather than r0).
PR 21124
* ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
(extract_raq, extract_ras, extract_rbx): New functions.
(powerpc_operands): Use opposite corresponding insert function.
(Q_MASK): Define.
(powerpc_opcodes): Apply Q_MASK to all quad insns with even
register restriction.
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