intel_sprite_set_colorkey_ioctl() lives in intel_sprice_uapi.{c,h}
these days. For some reason the old protoype was left behind
in intel_sprite.h and even used by i915_driver.c. Remove the
leftovers and switch to including the correct header for the
prototype.
To reach PC10 when PKG_C_LATENCY is configure we must do the following
things
1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered
2) Allow PSR2 deep sleep when DC5 can be entered
3) DC5 can be entered when all transocoder have either PSR1, PSR2 or
eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are
not happening.
--v2
-Switch condition and do an early return [Jani]
-Do some checks in compute_config [Jani]
-Do not use register reads as a method of checking states for
DPKGC or delayed vblank [Jani]
-Use another way to see is vblank interrupts are disabled or not [Jani]
--v3
-Use has_psr to check if psr can be enabled or not for dc5_entry cond
[Uma]
-Move the dc5 entry computation to psr_compute_config [Jouni]
-No need to change sequence of enabled and activate,
so dont make hsw_psr1_activate return anything [Jouni]
-Use has_psr to stop psr1 activation [Jouni]
-Use lineage no. in WA
-Add the display ver restrictions for WA
--v4
-use more appropriate name for check_vblank_limit() [Jouni]
-Cover the case for idle frames when dpkgc is not configured [Jouni]
-Check psr only for edp [Jouni]
--v5
-move psr1 handling to plane update [Jouni]
-add todo for cases when vblank is enabled when psr enabled [Jouni]
-use intel_display instead of drm_i915_private
--v7
-fix has_psr condition [Uma]
-fix typo in commit subject [Uma]
-put psr1_wa check in its own helper [Uma]
-fix the dc_entry check [Jouni]
-use HAS_PSR() to cover two edp one with psr and one nonpsr [Jouni]
Jani Nikula [Thu, 19 Sep 2024 09:04:27 +0000 (12:04 +0300)]
drm/i915/pps: split intel_pps_reset_all() to vlv and bxt variants
The intel_pps_reset_all() function does similar but not quite the same
things for VLV/CHV and BXT/GLK. Observe that it's called from platform
specific code only, and a split to two functions vlv_pps_reset_all() and
bxt_pps_reset_all() is natural.
Remove the platform checks and warnings from the functions. We don't
usually have them, unless we're unsure. To make this easier to reason
about for BXT/GLK, change the condition on caller side from "!PCH" to
"BXT || GLK".
Jani Nikula [Fri, 20 Sep 2024 11:56:50 +0000 (14:56 +0300)]
drm/i915/dp: convert DP test debugfs to struct intel_display
Prefer struct intel_display over struct drm_i915_private. Do some
drive-by logging conversions to kms category.
Observe that i915_displayport_test_active_write() was using the wrong
type for m->private, but it has worked because struct drm_i915_private
has struct drm_device at offset 0.
drm/i915/display: Prevent DC6 while vblank is enabled for Panel Replay
We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't
prevent DC6 in case of Panel Replay. This causes problems if user-space is
polling for vblank events.
Fix this by setting target DC state as DC_STATE_EN_UPTO_DC5 when both
source and sink are supporting eDP Panel Replay and VBI is enabled.
v4:
- s/vblank_work/vblank_dc_work/
- changed type of block_dc_for_vblank to bool
v3:
- do flush_work for vblank_work on intel_crtc_vblank_off
- no need to use READ_ONCE in bdw_enable_vblank
- check crtc->block_dc_for_vblank in bdw_disable_vblank as well
- move adding block_dc_for_vblank into this patch
v2:
- use READ_ONCE in intel_display_vblank_work
- use DC_STATE_DISABLE instead of DC_STATE_EN_UPTO_DC6
- use intel_crtc->block_dc6_needed
drm/i915/psr: Add intel_psr_needs_block_dc_vblank for blocking dc entry
We need to block DC6 entry in case of Panel Replay as enabling VBI doesn't
prevent it in case of Panel Replay. Panel Replay switches main link off on
DC entry. This means vblank interrupts are not fired and is a problem if
user-space is polling for vblank events. For this purpose add new function
to query need for dc entry blocking on.
Jani Nikula [Tue, 17 Sep 2024 16:14:01 +0000 (19:14 +0300)]
drm/xe: eradicate -Ddrm_i915_gem_object=xe_bo
We've now completely stopped using drm_i915_gem_object in display code
that gets built for xe. Kill off the -Ddrm_i915_gem_object=xe_bo
hack. Good riddance.
Jani Nikula [Tue, 17 Sep 2024 16:13:58 +0000 (19:13 +0300)]
drm/i915/display: clean up some gem/ includes
Drop some unnecessary gem/ includes.
We seem to include xe_device.h through some compat gem headers, so we
need to include it directly in compat i915_drv.h to get
xe_device_has_flat_ccs().
Jani Nikula [Tue, 17 Sep 2024 16:13:57 +0000 (19:13 +0300)]
drm/i915/fb: remove intel_fb_obj()
Convert remaining users of the struct drm_i915_gem_object based
intel_fb_obj() to the struct drm_gem_object based intel_fb_bo(), and
remove intel_fb_obj().
Jani Nikula [Tue, 17 Sep 2024 16:13:51 +0000 (19:13 +0300)]
drm/xe/display: stop using intel_fb_obj() in xe_fb_pin.c
intel_fb_obj() returns struct drm_i915_gem_object, which is not right
for xe, and only works because xe defines
-Ddrm_i915_gem_object=xe_bo. Switch to intel_fb_bo() and convert to
struct xe_bo from there.
Jani Nikula [Tue, 17 Sep 2024 16:13:44 +0000 (19:13 +0300)]
drm/i915/display: convert skl_universal_plane.c to struct drm_gem_object
Prefer the driver agnostic struct drm_gem_object over i915 specific
struct drm_i915_gem_object. Add new intel_bo_* functions as
needed. Convert intel_pxp_key_check() to struct drm_gem_object.
Jani Nikula [Tue, 17 Sep 2024 16:13:40 +0000 (19:13 +0300)]
drm/i915/display: start a buffer object abstraction layer
The display code needs to deal with gem objects, and mostly uses struct
drm_i915_gem_object. That's not great, because for xe we need to
redefine it struct xe_bo during build.
Start a common interface using struct drm_gem_object, with separate
implementations for i915 and xe. For starters, convert i9xx_wm.c to use
it.
Jani Nikula [Mon, 8 Apr 2024 12:54:44 +0000 (15:54 +0300)]
drm/i915/display: remove small micro-optimizations in irq handling
The raw register reads/writes are there as micro-optimizations to avoid
multiple pointer indirections on uncore->regs. Presumably this is useful
when there are plenty of register reads/writes in the same
function. However, the display irq handling only has a few raw
reads/writes. Remove them for simplification.
Clean up the main commit_tail() codepath a bit by pulling
the post plane update steps that need to performed after
readout into their own little function
(intel_post_plane_update_after_readout()).
Declutters intel_atomic_commit_tail() a bit, and should
hopefully aid in keeping intel_pre_plane_update() vs.
intel_post_plane_update*() in sync.
drm/i915/display: Enhance iterators for modeset en/disable
Joiners have specific enabling and disabling order dependent on primary
and secondary pipes. This becomes more complex with ultrajoiner where we
have ultrajoiner primary/secondary pipes in addition to bigjoiner
primary/secondary pipes. To unify the approach that works for present
and future joiner cases, use primary and secondary pipe masks to
iterate over pipes.
If joiner is used, derive bigoiner primary and secondary pipe masks
and use following sequences:
Disabling : disable primary pipes followed by secondary pipes,
Enabling: enable secondary pipes followed by primary pipes.
This works well with ultrajoiner too, as ultrajoiner has 2 bigjoiner
primary/secondary pairs (AC, BD).
For non joiner case, enable/disable based on usual pipe order A-D, D-A
respectively.
v2:
-Simplify the iterator macro. (Ville)
-Use struct intel_display. (Ville)
-Add prefix _intel to the helper name. (Ville)
drm/i915: Add some essential functionality for joiners
In most of the cases we now try to avoid mentioning things like
"bigjoiner" or "ultrajoiner" trying to unify the API and refer
mostly to all this functionality as "joiner".
In majority cases that should be way to go.
However in some cases we still need to distinguish between
bigjoiner primaries and secondaries(such as DSC register programming).
Create correspondent helper functions and start using them,
in order be prepared for adding ultrajoiner functionality.
v2: Fixed checkpatch warnings (Ankit)
v3: Introduce ultrajoiner helpers in next patch.
v4: Streamline the helpers and add few more. (Ville)
v5: Add comment to clarify that helpers apply to both bigjoiner and
uncompressed joiner configurations. (Ville)
Jani Nikula [Fri, 13 Sep 2024 12:51:55 +0000 (15:51 +0300)]
drm/i915/debugfs: add dedicated intel_display_caps debugfs for display
Add dedicated intel_display_caps for display, with device info and
params. Intentionally prefix the file intel_ instead of i915_. Going
forward, we should do the same for all debugfs files, making them
independent of i915 and xe.
Remove display param dumping from i915 specific i915_capabilities
debugfs.
Note that we don't add node_to_intel_display() functionality in
to_intel_display(). It's too specific for that.
Jani Nikula [Wed, 18 Sep 2024 17:47:49 +0000 (20:47 +0300)]
drm/i915/pps: move vlv_active_pipe() to intel_pps.c
All the users for vlv_active_pipe() are within intel_pps.c now, and
there are already uses of g4x_dp_port_enabled() and intel_dp->output_reg
in there, so seems fine to reduce interfaces and move vlv_active_pipe()
to intel_pps.c too.
Jani Nikula [Wed, 18 Sep 2024 17:47:45 +0000 (20:47 +0300)]
drm/i915/pps: add vlv_pps_pipe_reset()
We need to track PPS also for non-eDP usage on VLV/CHV. Add new
vlv_pps_pipe_reset() for resetting the related parts, hiding the PPS
pipe details inside PPS code.
Jani Nikula [Wed, 18 Sep 2024 17:47:44 +0000 (20:47 +0300)]
drm/i915/pps: add vlv_pps_pipe_init()
We need to track PPS also for non-eDP usage on VLV/CHV. Add new
vlv_pps_pipe_init() for initializing the related parts, hiding the PPS
pipe details inside PPS code.
Jani Nikula [Wed, 18 Sep 2024 17:47:43 +0000 (20:47 +0300)]
drm/i915/pps: only touch the vlv_ members on VLV/CHV
While the struct intel_pps vlv_pps_pipe and vlv_active_pipe members are
only relevant for VLV/CHV, we still initialize them on all platforms and
check them on BXT/GLK. Wrap all access inside VLV/CHV checks for
consistency.
Ville Syrjälä [Wed, 11 Sep 2024 15:18:36 +0000 (18:18 +0300)]
drm/i915/psr: Fix PSR sink enable sequence
According to the eDP spec, the source must first configure all
PSR related DPCD registers apart from the actual enable bit,
and only then set the enable bit. Split the current single DPCD
write to two to match the spec.
drm/i915/display: Use joined pipes in dsc helpers for slices, bpp
In preparation of ultrajoiner, use number of joined pipes in the dsc
helpers to compute dsc slices and max compressed bpp, instead of using
the joiner flag.
v2: Adjust the formulae to use num of pipes as 1 (no joiner) or 2
(bigjoiner). (Ankit)
drm/i915/display: Simplify intel_joiner_num_pipes and its usage
Currently intel_joiner_num_pipes is used to get num of pipes wrt num of
pipes joined. Simplify this by returning 1 when no joiner is used and
update the checks for no joiner case.
v2: Rename the function to intel_crtc_num_joined_pipes and use helper
intel_crtc_joined_pipe_mask. (Ville)
Jani Nikula [Fri, 13 Sep 2024 13:54:38 +0000 (16:54 +0300)]
drm/i915: move intel_get_pipe_from_crtc_id_ioctl to intel_crtc.c
Reduce the size of and dependencies on intel_display.[ch], and move
intel_get_pipe_from_crtc_id_ioctl() to intel_crtc.[ch]. Rename to
intel_crtc_get_pipe_from_crtc_id_ioctl() while at it.
Let's kill this legacy iand almost unused rq_enabled version
in favor of the real one that is checked at
intel_irqs_enabled().
The commit 'ac1723c16b66 ("drm/i915: Track IRQ state
in local device state")' shows that this was a legacy
DRM level irq_enabled information that got removed.
But the driver one already existed under a different
name.
Yan Zhen [Fri, 13 Sep 2024 06:17:27 +0000 (14:17 +0800)]
drm/i915/display: fix typo in the comment
Correctly spelled comments make it easier for the reader to understand
the code.
Replace 'platformas' with 'platforms' in the comment &
replace 'prefere' with 'prefer' in the comment &
replace 'corresponsding' with 'corresponding' in the comment &
replace 'harizontal' with 'horizontal' in the comment.
Add macros to check if platform supports bigjoiner/uncompressed joiner.
Replace the existing DISPLAY_VER checks with these.
Additionally use it before readout for joiner stuff, where its missing.
Imre Deak [Tue, 10 Sep 2024 11:18:47 +0000 (14:18 +0300)]
drm/i915/dp: Fix AUX IO power enabling for eDP PSR
Panel Self Refresh on eDP requires the AUX IO power to be enabled
whenever the output (main link) is enabled. This is required by the
AUX_PHY_WAKE/ML_PHY_LOCK signaling initiated by the HW automatically to
re-enable the main link after it got disabled in power saving states
(see eDP v1.4b, sections 5.1, 6.1.3.3.1.1).
The Panel Replay mode on non-eDP outputs on the other hand is only
supported by keeping the main link active, thus not requiring the above
AUX_PHY_WAKE/ML_PHY_LOCK signaling (eDP v1.4b, section 6.1.3.3.1.2).
Thus enabling the AUX IO power for this case is not required either.
Based on the above enable the AUX IO power only for eDP/PSR outputs.
Bspec: 49274, 53370
v2:
- Add a TODO comment to adjust the requirement for AUX IO based on
whether the ALPM/main-link off mode gets enabled. (Rodrigo)
Add hwmon support for temp1_input attribute, which will expose package
temperature in millidegree Celsius. With this in place we can monitor
package temperature using lm-sensors tool.
The error state capture still handles display info at a too detailed
level. Start abstracting the whole display snapshot capture and printing
at a higher level. Move overlay to display snapshot first.
Use the same nomenclature and style as in xe devcoredump, in preparation
for perhaps some day bolting the snapshots there as well.
v3: Fix build harder for CONFIG_DRM_I915_CAPTURE_ERROR=n
v2: Fix build for CONFIG_DRM_I915_CAPTURE_ERROR=n (kernel test robot)
Jani Nikula [Thu, 12 Sep 2024 14:34:11 +0000 (17:34 +0300)]
drm/i915: dump display parameters captured in error state, not current
intel_display_params_dump() prints the current display parameters, not
the ones captured during error capture. It's not likely the params get
changed in between, but make it pedantically correct anyway. Pass in the
parameters and driver name to intel_display_params_dump().
drm/xe/display: Do not suspend resume dp mst during runtime
Remove intel_dp_mst_suspend/resume from runtime suspend resume
sequences. It is incorrect as it depends on AUX transfers which
itself depend on the device being runtime resumed. This is
also why we see a lock_dep splat here.
drm/i915: Do not explicilty enable FEC in DP_TP_CTL for UHBR rates
In case of UHBR rates, we do not need to explicitly enable FEC by writing
to DP_TP_CTL register.
For MST use-cases, intel_dp_mst_find_vcpi_slots_for_bpp() takes care of
setting fec_enable to false. However, it gets overwritten in
intel_dp_dsc_compute_config(). This change keeps fec_enable false across
MST and SST use-cases for UHBR rates.
While at it, add a comment explaining why we don't enable FEC in eDP v1.5.
v2: Correct logic to cater to SST use-cases (Jani)
Ville Syrjälä [Fri, 6 Sep 2024 14:33:06 +0000 (17:33 +0300)]
drm/i915/dmc: Convert DMC code to intel_display
struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert the DMC code to
use it (as much as possible at this stage).
Ville Syrjälä [Fri, 6 Sep 2024 14:33:05 +0000 (17:33 +0300)]
drm/i915/power: Convert "i830 power well" code to intel_display
struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert the "i830 power well"
code to use it (as much as possible at this stage).
Ville Syrjälä [Fri, 6 Sep 2024 14:33:04 +0000 (17:33 +0300)]
drm/i915/vga: Convert VGA code to intel_display
struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert the VGA code to
use it (as much as possible at this stage).
Ville Syrjälä [Fri, 6 Sep 2024 14:33:03 +0000 (17:33 +0300)]
drm/i915/power: Convert low level DC state code to intel_display
struct intel_display will replace struct drm_i915_private as
the main thing for display code. Convert the lower level
DC state code to use it (as much as possible at this stage).
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