Jonas Karlman [Mon, 21 Jul 2025 22:07:13 +0000 (22:07 +0000)]
phy: rockchip: naneng-combphy: Simplify init ops
The init ops for Rockchip COMBPHY driver is more complex than it needs
to be, e.g. declaring multiple init functions that only differ in the
error message.
Simplify the init ops based on code from the Linux mainline driver.
This change also ensure that errors returned from combphy_cfg() and
reset_deassert_bulk() is propertly propagated to the caller. No other
runtime change is expected with this simplication.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Generic PHY reference counting helps ensure driver ops for init/exit and
power on/off are called at correct state. For this to work the PHY
driver must initialize PHY-id to a persistent value in of_xlate ops.
The Rockchip COMBPHY driver does not initialize the PHY-id field, this
typically lead to use of unshared reference counting among different
struct phy instances.
Initialize the PHY-id in of_xlate ops to ensure use of shared reference
counting among all struct phy instances.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Mon, 21 Jul 2025 22:07:11 +0000 (22:07 +0000)]
phy: rockchip: usbdp: Simplify init ops
With working shared reference counting for Generic PHY ops there is no
need for the Rockchip USBDP PHY driver to keep its own status (reference
counting) handling.
Simplify the init ops now that shared reference counting is working.
This also removes the unused mode_change handling as part of the
simplication.
No runtime change is expected with this simplication.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Generic PHY reference counting helps ensure driver ops for init/exit and
power on/off are called at correct state. For this to work the PHY
driver must initialize PHY-id to a persistent value in of_xlate ops.
The Rockchip USBDP PHY driver does not initialize the PHY-id field, this
typically lead to use of unshared reference counting among different
struct phy instances.
Initialize the PHY-id in of_xlate ops to ensure use of shared reference
counting among all struct phy instances.
E.g. on a ROCK 5B following could be observed:
=> usb start
starting USB...
[...]
Bus usb@fc400000: 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
=> usb reset
resetting USB...
[...]
rockchip_udphy phy@fed90000: cmn ana lcpll lock timeout
rockchip_udphy phy@fed90000: failed to init usbdp combophy
rockchip_udphy phy@fed90000: PHY: Failed to init phy@fed90000: -110.
Can't init PHY1
Bus usb@fc400000: probe failed, error -110
scanning usb for storage devices... 0 Storage Device(s) found
With shared reference counting this is fixed:
=> usb reset
resetting USB...
[...]
Bus usb@fc400000: 2 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andrew Goodbody [Thu, 31 Jul 2025 11:46:10 +0000 (12:46 +0100)]
mmc: rockchip_sdhci: Do not test unsigned for being less than 0
In rockchip_sdhci_execute_tuning the variable tuning_loop_counter is
tested for being less than 0. Ensure that it is a signed type by
declaring it as s8 instead of char.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Wed, 13 Aug 2025 14:07:43 +0000 (16:07 +0200)]
power: rk8xx: allow to customize RK806 reset mode
The RK806 PMIC has a bitfield for configuring the restart/reset behavior
(which I assume Rockchip calls "function") whenever the PMIC is reset
either programmatically (c.f. DEV_RST in the datasheet) or via PWRCTRL
or RESETB pins.
For RK806, the following values are possible for RST_FUN:
0b00 means "Restart PMU"
0b01 means "Reset all the power off reset registers, forcing
the state to switch to ACTIVE mode"
0b10 means "Reset all the power off reset registers, forcing
the state to switch to ACTIVE mode, and simultaneously
pull down the RESETB PIN for 5mS before releasing"
0b11 means the same as for 0b10 just above.
This adds the appropriate logic in the driver to parse the new
rockchip,reset-mode DT property to pass this information. It just
happens that the values in the binding match the values to write in the
bitfield so no mapping is necessary.
For backward compatibility reasons, if the property is missing we set it
to 0b10 (i.e. BIT(7)) like before this commit was merged instead of
leaving it untouched like in the kernel driver.
Note that this does nothing useful for U-Boot at the moment as the ways
to reset the device (e.g. via `reset` command) doesn't interact with the
RK8xx PMIC and simply does a CPU reset.
Considering the upstream Linux kernel left this register untouched until
(assumed) v6.17[1], this is useful for cases in which the U-Boot
bootloader has this patch (and running with a DT with
rockchip,reset-mode property set) and running an upstream kernel before
(assumed) v6.17, or alternatively later without the property in the
kernel DT.
Quentin Schulz [Wed, 13 Aug 2025 14:07:42 +0000 (16:07 +0200)]
arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Tiger
The bootloader for RK3588 Tiger currently forces the PMIC reset behavior
(stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X
which is incorrect for our devices.
It is required to restart the PMU as otherwise the companion
microcontroller cannot detect the PMIC (and by extension the full
product and main SoC) being rebooted which is an issue as that is used
to reset a few things like the PWM beeper and watchdogs.
Let's add the new rockchip,reset-mode property to make sure the PMIC
reset behavior is the expected one.
Quentin Schulz [Wed, 13 Aug 2025 14:07:41 +0000 (16:07 +0200)]
arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Jaguar
The bootloader for RK3588 Jaguar currently forces the PMIC reset
behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC)
to 0b1X which is incorrect for our devices.
It is required to restart the PMU as otherwise the companion
microcontroller cannot detect the PMIC (and by extension the full
product and main SoC) being rebooted which is an issue as that is used
to reset a few things like the PWM beeper and watchdogs.
Let's add the new rockchip,reset-mode property to make sure the PMIC
reset behavior is the expected one.
Quentin Schulz [Wed, 13 Aug 2025 14:07:40 +0000 (16:07 +0200)]
arm64: dts: rockchip: add header for RK8XX PMIC constants
To make it easier to read the device tree, let's add constants for the
rockchip,reset-mode property values that are currently only applicable
to RK806 PMIC.
Quentin Schulz [Wed, 13 Aug 2025 14:07:39 +0000 (16:07 +0200)]
dt-bindings: mfd: rk806: Allow to customize PMIC reset mode
The RK806 PMIC allows to configure its reset/restart behavior whenever
the PMIC is reset either programmatically or via some external pins
(e.g. PWRCTRL or RESETB).
The following modes exist:
- 0; restart PMU,
- 1; reset all power off reset registers and force state to switch to
ACTIVE mode,
- 2; same as mode 1 and also pull RESETB pin down for 5ms,
For example, some hardware may require a full restart (mode 0) in order
to function properly as regulators are shortly interrupted in this mode.
This is the case for RK3588 Jaguar and RK3588 Tiger which have a
companion microcontroller running on an independent power supply and
monitoring the PMIC power rail to know the state of the main system.
When it detects a restart, it resets its own IPs exposed to the main
system as if to simulate its own reset. Failing to perform this fake
reset of the microcontroller may break things (e.g. watchdog not
automatically disabled, buzzer still running until manually disabled,
leftover configuration from previous main system state, etc...).
Some other systems may be depending on the power rails to not be
interrupted even for a small amount of time[1].
This allows to specify how the PMIC should perform on the hardware level
and may differ between hardware designs, so a DT property seems
warranted. I unfortunately do not see how this could be made generic
enough to make it a non-vendor property.
Jonas Karlman [Wed, 30 Jul 2025 23:52:45 +0000 (23:52 +0000)]
rockchip: rk3528: Disable USB3OTG U3 port early
The RK3528 SoC comes with USB OTG support using a DWC3 controller with
a USB2 PHY and a USB3 PHY (COMBPHY).
Some board designs may not use the COMBPHY for USB3 purpose. For these
board to use USB OTG the input clock source must change to use UTMI clk
instead of PIPE clk.
Change to always disable the USB3OTG U3 port early and leave it to the
COMBPHY driver to re-enable the U3 port when a usb3-phy is described in
the board device tree.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 30 Jul 2025 23:52:42 +0000 (23:52 +0000)]
rockchip: rk3528-generic: Fix boot after dts/upstream v6.16-dts merge
The rk3528-generic target can no longer boot after v6.16-dts was merged
into dts/upstream, and instead end up in a boot loop:
No serial driver found
resetting ...
After Linux commit 34d2730fbbdd ("arm64: dts: rockchip: move rk3528
i2c+uart aliases to board files") there is no longer an alias for
serial0 defined for the U-Boot only rk3528-generic device tree.
Add a board specific aliases node that include the missing serial0 alias
to resolve the boot issue and ensure that stdout-path = "serial0:..."
can be resolved by U-Boot.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Marius Dinu [Wed, 11 Jun 2025 11:04:54 +0000 (11:04 +0000)]
rk3288: add fdtoverlay_addr_r to default env
rk3288 is missing fdtoverlay_addr_r.
The new addresses match those used by rk3308.
Tested on Asus TinkerBoard S.
Signed-off-by: Marius Dinu <m95d+git@psihoexpert.ro> Cc: Simon Glass <sjg@chromium.org> Cc: Philipp Tomsich <philipp.tomsich@vrull.eu> Cc: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Fri, 27 Jun 2025 13:30:19 +0000 (15:30 +0200)]
rockchip: puma-rk3399: enable "env erase" command
Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Erasing the environment to start from scratch is actually very useful
and "env erase" is the proper way to do it instead of using "env
default -a && env save", so let's enable support for it.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 1 Aug 2025 20:43:39 +0000 (20:43 +0000)]
board: rockchip: Add ArmSoM Sige5
ArmSoM-Sige5 adopts the second-generation 8nm high-performance AIOT
platform Rockchip RK3576, with a 6 TOPS computing power NPU and support
for up to 16GB of large memory. It supports 4K video encoding and
decoding, offers rich interfaces including dual gigabit Ethernet ports,
WiFi 6 & BT5, and various video outputs.
Features tested on a ArmSoM Sige5 v1.1:
- SD-card boot
- eMMC boot
- Ethernet
- PCIe NVMe
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Frank Wang [Fri, 1 Aug 2025 20:32:44 +0000 (20:32 +0000)]
phy: rockchip: usbdp: Add support for RK3576
Add support for the USB3.0+DP PHY used in the RK3576 SoC.
Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Frank Wang [Fri, 1 Aug 2025 20:32:43 +0000 (20:32 +0000)]
phy: rockchip-inno-usb2: Add support for RK3576
Add support for the USB2.0 PHYs used in the RK3576 SoC.
Config values are taken from vendor U-Boot linux-6.1-stan-rkr5 tag.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 1 Aug 2025 20:32:41 +0000 (20:32 +0000)]
arm: dts: rockchip: Include OTP in U-Boot pre-reloc phase for RK3576
Update rk3576-u-boot.dtsi to include OTP in U-Boot pre-reloc phase for
checkboard() to be able to read information about the running SoC model
and variant from OTP and print it during boot:
U-Boot 2025.04 (Apr 22 2025 - 20:43:17 +0000)
Model: Generic RK3576
SoC: RK3576
DRAM: 8 GiB
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 1 Aug 2025 20:32:39 +0000 (20:32 +0000)]
board: rockchip: Add minimal generic RK3576 board
Add a minimal generic RK3576 board that only have eMMC, SDMMC and USB
OTG enabled. This defconfig can be used to boot from eMMC or SD-card on
most RK3576 boards that follow reference board design.
Da Xue [Tue, 10 Jun 2025 19:08:20 +0000 (19:08 +0000)]
arm64: dts: rockchip: roc-3328-cc: use 1600 ddr4 timing
Swap the ROC-3328-CC from DDR4 666 to 1600 timing to boost performance.
Signed-off-by: Da Xue <da@libre.computer> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Da Xue [Tue, 10 Jun 2025 19:08:19 +0000 (19:08 +0000)]
ram: rk3328: add ddr4-1600 sdram timing
Add DDR4 1600MHz SDRAM timing data from LibreComputer u-boot sources
for the ROC-3328-CC board.
Signed-off-by: Da Xue <da@libre.computer> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The information is read from the OTP and also the DDR_GRF. There's no
public information as far as I know about the layout and stored
information on OTP but this was provided by Rockchip themselves through
their support channel.
The OTP stores the information of whether the SoC is PX30K or something
else. To differentiate between PX30/RK3326 and PX30S/RK3326S, one needs
to read some undocumented bitfield in a DDR_GRF register as done in
vendor kernel,
c.f. https://github.com/armbian/linux-rockchip/blob/rk-6.1-rkr5.1/drivers/soc/rockchip/rockchip-cpuinfo.c#L118-L133.
I do not own a PX30S, nor RK3326/RK3326S so cannot test it works
properly.
Also add the OTP node to the pre-relocation phase of U-Boot proper so
that the SoC variant can be printed when DISPLAY_BOARDINFO is enabled.
This is not required if DISPLAY_BOARDINFO_LATE is enabled because this
happens after relocation. If both are enabled, then the SoC variant will
be printed twice in the boot log, e.g.:
Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit
SoC: PX30 <---- due to DISPLAY_BOARDINFO
DRAM: 2 GiB
PMIC: RK809 (on=0x40, off=0x00)
Core: 293 devices, 27 uclasses, devicetree: separate
MMC: mmc@ff370000: 1, mmc@ff390000: 0
Loading Environment from MMC... Reading from MMC(1)... OK
In: serial@ff030000
Out: serial@ff030000
Err: serial@ff030000
Model: Theobroma Systems PX30-uQ7 SoM on Haikou devkit
SoC: PX30 <----- due to DISPLAY_BOARDINFO_LATE
Net: eth0: ethernet@ff360000
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Alex Shumsky [Thu, 3 Jul 2025 06:04:48 +0000 (09:04 +0300)]
rockchip: rockchip-inno-usb2: Fix Synchronous Abort on usb start
Fix NULL pointer dereference that happen when rockchip-inno-usb2 clock
enabled before device probe. This early clock enable call happen in process
of parent clock activation added in ac30d90f3367.
Fixes: 229218373c22 ("phy: rockchip-inno-usb2: Add support for clkout_ctl_phy"). Fixes: ac30d90f3367 ("clk: Ensure the parent clocks are enabled while reparenting") Co-authored-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Alex Shumsky <alexthreed@gmail.com> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andrew Goodbody [Wed, 13 Aug 2025 16:30:12 +0000 (17:30 +0100)]
usb: cdns3: Do not access memory after free
The call to cdns3_gadget_ep_free_request will free priv_req so do the
call to list_del_init which accesses the memory pointed to by priv_req
before the free.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
- Enable OF_UPSTREAM_BUILD_VENDOR for stm32mp25_defconfig
- Fix to avoid inifite loop in stm32_sdmmc2 driver
- Populate oobavail field of nand_ecclayout in stm32_fmc2_nand driver
Anshul Dalal [Thu, 14 Aug 2025 15:21:43 +0000 (20:51 +0530)]
remoteproc: k3: update compatible for am654 syscon
The existing compatible name for U-Boot's k3 system controller driver
i.e "ti,am625-system-controller" has been added to linux[1] device-tree.
This compatible in kernel is meant for configuring the Control Module
registers (CTRL_MMR0).
However in U-Boot, the matching driver was being used to load the system
firmware on the secure M-cores by the R5 SPL and therefore must be
updated to a different compatible to avoid conflicts.
Therefore, this patch renames all references of the compatible to
"ti,am654-tisci-rproc-r5". The "-r5" is appended so as to avoid any
future conflicts since r5 specific compatibles should only be useful for
U-Boot.
Initially, only one STM32MP25 based board was available, the
stm32mp257f-ev1 board which was set by default in stm32mp25_defconfig.
Since commit 79f3e77133bd ("Subtree merge tag 'v6.16-dts' of dts repo [1] into dts/upstream")
we inherited of a second MP25 based board which is the stm32mp257f-dk board.
Enable OF_UPSTREAM_BUILD_VENDOR and set OF_UPSTREAM_VENDOR to allow all
STMicroelectronics DT compilation.
Avoid unlimited while loop by adding a timeout. The timeout is
calculated based on a minimal throughput of 256 KB/s.
The timeout is set at least to 2 seconds.
mtd: rawnand: stm32_fmc2: set available OOB bytes per page
File system such as YAFFS2 need to know the number of available
OOB bytes per page to be able to choose if they should locate their
metadata in the data area or in the spare area.
configs: versal2: Add usb_pgood_delay for versal2 boards
Add usb_pgood_delay to ensure proper detection of USB devices.
Increase the USB power good delay for versal2 specific boards,
as certain USB sticks may not be detected without it.
Andrew Goodbody [Mon, 18 Aug 2025 09:24:36 +0000 (10:24 +0100)]
net: axi_emac: Fix timeout test
The timeout test in axi_dma_init is not correct due to the
post-decrement used on the timeout variable which will mean timeout is
not 0 if the timeout occurs. Make the timeout variable an int instead of
a u32 and then test for timeout being -1.
Michal Simek [Tue, 29 Jul 2025 13:55:20 +0000 (15:55 +0200)]
arm64: zynqmp: Add missing ethernet alias for kr260-revB
Ethernet aliases are used in fdt_fixup_ethernet() to inject
local-mac-address in every boot for OS. Similar change has been done for
other carrier cards by commit c4a711253613 ("arm64: zynqmp: Describe
ethernet controllers via aliases on SOM").
Michal Simek [Mon, 28 Jul 2025 07:07:54 +0000 (09:07 +0200)]
fpga: lattice: Remove unused support
There is no single platform which is using this driver that's why remove it
completely. Some issues regarding this code are also reported by Coverity
(CID 583143, 583144, 583145, 583146).
Frank Böwingloh [Fri, 8 Aug 2025 12:31:34 +0000 (14:31 +0200)]
soc: xilinx: zynqmp: Fix zu1cg device detection
Currently u-boot displayed a zu1cg soc as "Chip: zu1eg".
A value of 0468_8093h in the IDCODE (CSU) Register defines a ZU1 soc
not only for the EG family but also for the CG family as described
in the Xilinx Zynq UltraScale+ UG1085 documentation in Table 1-2.
Andrew Goodbody [Thu, 7 Aug 2025 10:04:05 +0000 (11:04 +0100)]
pinctrl: zynqmp: Avoid using uninitialised variable
In zynqmp_pinconf_set if param is PIN_CFG_IOSTANDARD or
PIN_CONFIG_POWER_SOURCE and zynqmp_pm_pinctrl_get_config returns an
error then value will not be assigned to when its value is tested to be
not equal to arg. Add code to only test value not equal to arg if ret is
false.
Andrew Goodbody [Thu, 7 Aug 2025 10:04:04 +0000 (11:04 +0100)]
pinctrl: zynqmp: Ensure ret is initialised
In zynqmp_pinctrl_prepare_func_groups if called with func->ngroups == 0
then ret will not be assigned to before its value is returned on exit.
Initialise ret to ensure it is always valid.
- Fix the environment location when booting from USB on i.MX93.
- Fix env location when booting from USB on phycore-imx93.
- Fix conflict early SPL malloc address on imx93 boards.
Patrick Delaunay [Wed, 23 Jul 2025 15:09:16 +0000 (17:09 +0200)]
usb: dwc2: fix reset logic in dwc2_core_reset
Use GUSBCFG_FORCEHOSTMODE to detected the HOST forced mode as it is done
in the Linux driver drivers/usb/dwc2/core.c:dwc2_core_reset().
The host polling must be executed only if the current mode is host,
either due to the force HOST mode (which persists after core reset)
or the connector id pin.
The GUSBCFG_FORCEDEVMODE bits is used to force the device mode (for
example used on STM32MP1x platform) and when it is activated the DWC2 reset
failed with the trace:
"dwc2_core_reset: Waiting for GINTSTS_CURMODE_HOST timeout"
Fixes: c5d685b8993c ("usb: dwc2: Unify flush and reset logic with v4.20a support") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Junhui Liu <junhui.liu@pigmoral.tech> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Tim Harvey [Mon, 21 Jul 2025 18:02:05 +0000 (11:02 -0700)]
usb: ehci-mx6: Add i.MX95 OTG support
When the usb node is defined dr_mode="otg" ehci_usb_phy_mode() is called
to determine the mode from status registers.
The IMX95RM does not currently define the USBNC STATUS register but it is
assumed to be an omission as the first three registers are defined.
It has been expirimentally verified that the USBNC_PHY_STATUS register
at offset 0x23C bit4 (USBNC_PHYSTATUS_ID_DIG) reads 0 when USB_ID is GND
and 1 when floating.
Use is_imx9() as this driver works for i.MX91, i.MX93 and i.MX95 and all
of these determine the role based on the USBNC_PHY_STATUS register.
Fixes: 801b5fafd35d "(usb: ehci-mx6: Add i.MX95 support") Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Alice Guo <alice.guo@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Tim Harvey [Wed, 9 Jul 2025 15:24:08 +0000 (08:24 -0700)]
phy: phy-imx8mq-usb: Add support for i.MX95 USB3 PHY
Add initial support for i.MX95 USB.30 PHY, which is similar to
the i.MX8MQ and i.MX8MP USB PHY.
The i.MX95 USB3 PHY has a Type-C Assist block (TCA) consisting of two
functional blocks (XBar assist and VBus assist) and is documented
in the i.MX95 RM Chapter 163.3.8 Type-C assist (TCA) block.
Instead of relying on an external MUX for Type-C plug orientation the
XBar can handle the flip internally.
Add initial support for i.MX95 by:
- allowing the driver to be enabled i.MX95
- resetting the XBar
- configuring the TCA in System Configuration mode (which was determined
to be necessary to enable the PHY in device-mode)
Follow-on support will need to be added to steer the XBar based on
either board design (if only one pair is brought out) or if used with a
Type-C controller.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Alice Guo <alice.guo@nxp.com>
Andrew Goodbody [Thu, 31 Jul 2025 16:21:32 +0000 (17:21 +0100)]
mtd: nand: Do not dereference before NULL check
In nanddev_init mtd and memorg are assigned values that dereference nand
but this happens before a NULL check for nand. Move the assignments
after the NULL check.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Miquel Raynal [Mon, 4 Aug 2025 09:21:37 +0000 (11:21 +0200)]
cmd: mtd: Enable speed benchmarking
Linux features a flash_speed speed test from the mtd-utils suite, U-Boot
does not. Benchmarks are useful for speed improvement developments as
well as troubleshooting or regression testing sometimes.
david regan [Thu, 14 Aug 2025 18:04:55 +0000 (11:04 -0700)]
cmd: nand: bug fix MTD_OOB_AUTO to MTD_OPS_AUTO_OOB
bug fix MTD_OOB_AUTO to MTD_OPS_AUTO_OOB since MTD_OOB_AUTO does not exist
Fixes: dfe64e2c8973 ("mtd: resync with Linux-3.7.1") Signed-off-by: david regan <dregan@broadcom.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
The driver currently does:
mtd->dev->parent = cadence->dev;
This works in Linux because `struct mtd_info` embeds a `struct device`,
so `mtd->dev` is always valid and its `.parent` can be set.
In U-Boot, however, `mtd->dev` is only a pointer to a `struct udevice`.
Dereferencing it before assignment is invalid, which breaks the device
hierarchy. As a result, consumers relying on `mtd->dev` (e.g. partition
parser, reset and re-init paths) operate on a dangling pointer. This
leads to failures during warm reset when the NAND device is accessed
again.
Fix by assigning the device pointer directly:
mtd->dev = cadence->dev;
This matches U-Boot’s device model, preserves a valid hierarchy, and
resolves the warm reset issue on Cadence NAND.
Fixes: ebc41cad ("drivers: mtd: nand: Add driver for Cadence Nand") Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Ye Li [Wed, 20 Aug 2025 13:08:51 +0000 (15:08 +0200)]
imx: imx93_{evk, frdm, qsb}: Fix conflict SPL early malloc address
Because the early malloc pool size is set to 0x18000, so using this
start address may cause conflict with ATF, then corrupt the heap data.
So we delete the definition to use the default early malloc pool from
CONFIG_SPL_STACK to avoid any conflict
Jérémie Dautheribes: applied the same patch to the frdm and qsb
imx93-based boards Signed-off-by: Jérémie Dautheribes <jeremie.dautheribes@bootlin.com>
Primoz Fiser [Tue, 19 Aug 2025 05:39:41 +0000 (07:39 +0200)]
board: phytec: phycore-imx93: Fix EEPROM bus mismatch in SPL
Fix PHYTEC EEPROM bus mismatch between SPL and U-Boot proper by enabling
CONFIG_SPL_DM_SEQ_ALIAS=y on phyCORE-i.MX93 boards. This way, both the
SPL and U-Boot proper will respect the device-tree aliases for I2C devs
and use the same I2C bus number for phytec_eeprom_data_setup() function
calls. This makes code less confusing and more robust.
Fixes an issue apparent since commit 79f3e77133bd ("Subtree merge tag
'v6.16-dts' of dts repo [1] into dts/upstream") where SPL would spew the
following error:
phytec_eeprom_read: i2c EEPROM not found: -110.
phytec_eeprom_data_setup: EEPROM data init failed
While later in U-Boot proper, EEPROM would be successfully read out.
This happens because Linux device-tree for phyBOARD-Segin-i.MX93 since
aforementioned commit enables I2C bus 2 (lpi2c2 is used for audio codec
and RTC) which breaks SPL I2C bus number ordering and I2C EEPROM bus is
shifted by +1. Now, lets prevent this from happening again by utilizing
device-tree aliases also in the SPL.
arm: imx: imx9: soc: Fix env location when booting from USB
On i.MX9 platforms, when booting from USB, the U-Boot environment is
always assumed to be in RAM. However, this causes the boot to hang when
`CONFIG_ENV_IS_NOWHERE` is not enabled. The boot also hangs even if the
environment is present in another storage media (for example, eMMC). Fix
the issue by correctly handling the U-Boot environment's location when
booting from USB. Also for i.MX95, set the environment location based on
the ENV config and not solely based on the boot device type.
Suggested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com>
Tom Rini [Thu, 21 Aug 2025 21:05:15 +0000 (15:05 -0600)]
Merge patch series "bootstd: rauc: Fix segfault when scanning device with unsupported layout"
Martin Schwan <m.schwan@phytec.de> says:
This series fixes a segfault, that would occur at the end of scanning a
device, which does not contain the required partition layout scheme for
a RAUC system.
With this series, a "bootflow scan" should now correctly scan the
specified devices with boot method "rauc" without crashing on invalid
partition schemes.
Andrew Goodbody [Fri, 8 Aug 2025 11:32:36 +0000 (12:32 +0100)]
ram: renesas: dbsc5: Fix off by 1 errors
In dbsc5_read_vref_training the arrays dvw_min_byte0_table and
dvw_min_byte1_table have 128 elements per channel. The variable
vref_stop_index is limited to be a maximum of 128. This means that the
index used to access the arrays must use a test of '< vref_stop_index'
rather than '<= vref_stop_index' in order to prevent out of bounds
accesses to the arrays.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This is mostly code cleanup and fixes, mainly for issues reported by the
Smatch tool, plus two small features for NET_LWIP as well as support for
the BCM54612E phy.
net-common:
- Fix a bunch of issues reported by Smatch
- Introduce CONFIG_DNS
- Add support for BCM54612E phy
net-legacy:
- Add missing SPDX-License-Identifier for files originating from LiMon
net-lwip:
- ping: initialize net_try_count to 1
- sntp: remove redundant sys_check_timeouts()
- tftp: resend initial request
- Add Kconfig option to show ICMP unreachable errors
Andrew Goodbody [Mon, 18 Aug 2025 10:44:29 +0000 (11:44 +0100)]
phy: cadence: torrent: Set an error code for return
In cdns_torrent_phy_probe the test for too many lanes configured does
not set an error code before taking the error path. This could lead to a
silent failure if the calling code does not detect the error. Add the
code to return -EINVAL in this case.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Mon, 18 Aug 2025 10:44:28 +0000 (11:44 +0100)]
phy: cadence: sierra: Remove variable that is not assigned to
In cdns_sierra_pll_bind_of_clocks the variable 'i' is declared but never
assigned to before its value is used in a dev_err. Replace clk_names[i]
by the name passed to device_bind(), i.e., "pll_mux_clk". With that, the
clk_names[] array is unused and can therefore be removed.
Andrew Goodbody [Tue, 5 Aug 2025 10:34:29 +0000 (11:34 +0100)]
net: ks8851_mll: Remove unreachable code
In ks8851_mll_detect_chip the if..else code detects the case of (val &
0xfff0) != CIDER_ID and returns if found. So testing for this again will
always fail and the code is unreachable. Just remove the test and code
block.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
The legacy network stack sets net_try_count to 1 at the beginning of the
net_loop() function. This is required for net_start_again() to work
properly. Therefore, set the variable accordingly in the do_ping()
function when NET_LWIP=y. This fixes an issue where a ping to an
unreachable destination would run twice on the same network device. For
example with qemu_arm64_lwip_defconfig:
=> dhcp
DHCP client bound to address 10.0.2.15 (3 ms)
=> ping 10.0.0.1
Using virtio-net#32 device
ping failed; host 10.0.0.1 is not alive
Using virtio-net#32 device
ping failed; host 10.0.0.1 is not alive
=> QEMU: Terminated
Andrew Goodbody [Fri, 1 Aug 2025 11:59:40 +0000 (12:59 +0100)]
net: cortina_ni: Fix typo accessing wrong phy
In ca_phy_probe when checking for an external phy it uses a field from
the internal phy due to what is assumed to be a copy/paste typo. Make
the obvious fix to use the field from the external phy.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
projects / thirdparty / u-boot.git / log
