Andre Vieira [Wed, 20 Nov 2024 17:15:28 +0000 (17:15 +0000)]
arm: Support pac_key_* register operand for MRS/MSR in Armv8.1-M Mainline
Add support for pac_key_[pu]_[0-3](_ns)? register operands for the MRS and MSR
instructions when assembling for Armv8.1-M Mainline, as well as adding the
corresponding support for disassembling instructions that use it.
Andre Vieira [Fri, 8 Nov 2024 10:06:26 +0000 (10:06 +0000)]
arm, objdump: Make objdump use bfd's machine detection to drive disassembly
For any arm elf target, disable an old piece of code that forced disassembly to
disassemble for 'unknown architecture' which once upon a time meant it would
disassemble ANY arm instruction. This is no longer true with the addition of
Armv8.1-M Mainline, as there are conflicting encodings for different thumb
instructions.
BFD however can detect what architecture the object file was assembled for
using information in the notes section. So if available, we use that,
otherwise we default to the old 'unknown' behaviour.
With the changes above code, a mode changing 'bx lr' assembled for armv4 with
the option --fix-v4bx will result in an object file that is recognized by bfd
as one for the armv4 architecture. The disassembler now disassembles this
encoding as a BX even for Armv4 architectures, but warns the user when
disassembling for Armv4 that this instruction is only valid from Armv4T
onwards.
Remove the unused and wrongfully defined ARM_ARCH_V8A_CRC, and
define and use a ARM_ARCH_V8R_CRC to make sure instructions enabled by
-march=armv8-r+crc are disassembled correctly.
Patch up some of the tests cases, see a brief explanation for each below.
inst.d:
This test checks the assembly & disassembly of basic instructions in armv3m. I
changed the expected behaviour for teqp, cmnp cmpp and testp instructions to
properly print p when disassembling, whereas before, in the 'unknown' case it
would disassemble these as UNPREDICTABLE as they were changed in later
architectures.
nops.d:
Was missing an -march, added one to make sure we were testing the right
behavior of NOP<c> instructions.
unpredictable.d:
Was missing an -march, added armv6 as that reproduced the behaviour being
tested.
Sam James [Sat, 16 Nov 2024 07:07:02 +0000 (07:07 +0000)]
ld: fix -std=gnu23 compatibility wrt _Bool
GCC trunk now defaults to -std=gnu23. We return false in a few places
which can't work when true/false are a proper type (_Bool). Return NULL
where appropriate instead of false. All callers handle this appropriately.
Sam James [Sat, 16 Nov 2024 05:12:51 +0000 (05:12 +0000)]
binutils: fix -std=gnu23 compatibility wrt _Bool
GCC trunk now defaults to -std=gnu23. We return false in a few places
which can't work when true/false are a proper type (_Bool). Return NULL
where appropriate instead of false. All callers handle this appropriately.
Sam James [Sat, 16 Nov 2024 05:01:58 +0000 (05:01 +0000)]
bfd: fix -std=gnu23 compatibility wrt _Bool
GCC trunk now defaults to -std=gnu23. We return false in a few places
which can't work when true/false are a proper type (_Bool). Return NULL
where appropriate instead of false. All callers handle this appropriately.
gas/
* config/tc-s390.c (s390_parse_cpu): New entry for arch15.
* doc/c-s390.texi: Document arch15 march option.
* doc/as.texi: Likewise.
* testsuite/gas/s390/s390.exp: Run the arch15 related tests.
* testsuite/gas/s390/zarch-arch15.d: Tests for arch15
instructions.
* testsuite/gas/s390/zarch-arch15.s: Likewise.
Signed-off-by: Andreas Krebbel <krebbel@linux.ibm.com> Reviewed-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit a98a6fa2d8ef5eb61534b07db80850dcdf07bdb4)
This leverages commit ("s390: Simplify (dis)assembly of insn operands
with const bits") to relax the operand constraints of the immediate
operand that contains the constant Z- or T-bit of the following extended
mnemonics:
risbgz, risbgnz, risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt
Previously those instructions were the only ones where the assembler
on s390 restricted the specification of the subject I3/I4 operand values
exactly according to their specification to an unsigned 6- or 5-bit
unsigned integer. For any other instructions the assembler allows to
specify any operand value allowed by the instruction format, regardless
of whether the instruction specification is more restrictive.
Allow to specify the subject I3/I4 operand as unsigned 8-bit integer
with the constant operand bits being ORed during assembly.
Relax the instructions subject significant operand bit masks to only
consider the Z/T-bit as significant, so that the instructions get
disassembled as their *z or *t flavor regardless of whether any reserved
bits are set in addition to the Z/T-bit.
Adapt the rnsbg, rosbg, and rxsbg test cases not to inadvertently set
the T-bit in operand I3, as they otherwise get disassembled as their
rnsbgt, rosbgt, and rxsbgt counterpart.
This aligns GNU Assembler to LLVM Assembler.
opcodes/
* s390-opc.c (U6_18, U5_27, U6_26): Remove.
(INSTR_RIE_RRUUU2, INSTR_RIE_RRUUU3, INSTR_RIE_RRUUU4): Define
as INSTR_RIE_RRUUU while retaining insn fmt mask.
(MASK_RIE_RRUUU2, MASK_RIE_RRUUU3, MASK_RIE_RRUUU4): Treat only
Z/T-bit of I3/I4 operand as significant.
gas/testsuite/
* gas/s390/zarch-z10.s (rnsbg, rosbg, rxsbg): Do not set T-bit.
s390: Simplify (dis)assembly of insn operands with const bits
Simplify assembly and disassembly of extended mnemonics with operands
with constant ORed bits:
Their instruction template already contains the respective constant
operand bits, as they are significant to distinguish the extended from
their base mnemonic. Operands are ORed into the instruction template.
Therefore it is not necessary to OR the constant bits into the operand
value during assembly in s390_insert_operand.
Additionally the constant operand bits from the instruction template
can be used to mask them from the operand value during disassembly in
s390_print_insn_with_opcode. For now do so for non-length unsigned
integer operands only.
The separate instruction formats need to be retained, as their masks
differ, which is relevant during disassembly to distinguish the base
and extended mnemonics from each other.
s390: Document syntax to omit base register operand
Document the s390-specific assembler syntax introduced by commit aacf780bca29 ("s390: Allow to explicitly omit base register operand in
assembly") to omit the base register operand B in D(X,B) and D(L,B) by
coding D(X,) and D(L,).
While at it document the alternative syntax to omit the index register
operand X in D(X,B) by coding D(,B) instead of D(B).
gas/
* doc/c-s390.texi (s390 Operands): Document syntax to omit base
register operand.
Fixes: aacf780bca29 ("s390: Allow to explicitly omit base register operand in assembly") Signed-off-by: Jens Remus <jremus@linux.ibm.com>
(cherry picked from commit e75cfa9f0f81f70389b6d81d22b664c37f2403db)
ELF: Properly group and place orphan note sections
Properly group orphan note sections. When placing orphan note section
as the first note section, place it after the section before all note
sections.
ld properly groups and places orphan note sections. If .note.gnu.build-id
is added to elf.sc, the orphan .note.gnu.property section will be placed
before the .note.gnu.build-id section due to the larger section alignment
and may be placed in the same PT_LOAD segment with text sections. Remove
.note.gnu.build-id from elf.sc to let ld properly group and add all orphan
note sections.
turned PLT32 relocation against section into PC32 relocation. But these
transformations are valid only for PC-relative relocations. Add fx_pcrel
check for PC-relative relocations when performing these transformations
to keep PLT32 relocation in `movq $foo@PLT, %rax`.
gas/
PR gas/32196
* config/tc-i386.c (tc_i386_fix_adjustable): Return fixP->fx_pcrel
for PLT32 relocations.
(i386_validate_fix): Turn PLT32 relocation into PC32 relocation
only if fixp->fx_pcrel is set.
* testsuite/gas/i386/reloc32.d: Updated.
* testsuite/gas/i386/reloc64.d: Likewise.
* testsuite/gas/i386/reloc32.s: Add PR gas/32196 test.
* testsuite/gas/i386/reloc64.s: Likewise.
ld/
PR gas/32196
* testsuite/ld-x86-64/plt3.s: New file.
* testsuite/ld-x86-64/x86-64.exp: Run plt3.
H.J. Lu [Sun, 15 Sep 2024 23:11:39 +0000 (07:11 +0800)]
x86/APX: Don't promote AVX/AVX2 instructions out of APX spec
V{BROADCAST,EXTRACT,INSERT}{F,I}128 and VROUND{P,S}{S,D} aren't promoted
to support EGPR in APX spec. Don't promote them out of APX spec. This
commit effectively reverted:
ec3babb8c10 x86/APX: V{BROADCAST,EXTRACT,INSERT}{F,I}128 can also be expressed 5a635f1f59a x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL} eea4357967b x86/APX: VROUND{P,S}{S,D} can generally be encoded
H.J. Lu [Mon, 9 Sep 2024 00:27:00 +0000 (17:27 -0700)]
bfd: Pass true to ld_plugin_object_p
Since linker calls bfd_plugin_object_p, which calls ld_plugin_object_p,
only for command-line input objects, pass true to ld_plugin_object_p so
that the same input IR file won't be included twice if the new LTO hook,
LDPT_REGISTER_CLAIM_FILE_HOOK_V2 isn't used.
PR ld/32153
* plugin.c (bfd_plugin_object_p): Pass true to ld_plugin_object_p.
projects / thirdparty / binutils-gdb.git / log
