- Initial SPL support for T-Head TH1520 SoC
- Improve usability of TH1520 with mainline SPL
- Support building RV32 & RV64 images
- riscv: Improve jh7110 support
Yao Zi [Fri, 16 May 2025 03:05:25 +0000 (03:05 +0000)]
riscv: dts: th1520: Complete clock tree
Describe the newly-supported clock controller of TH1520 in SoC
devicetree, replace dummy clocks with the controller-supplied ones and
add correct clocks for GPIO controllers.
Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Yao Zi [Fri, 16 May 2025 03:05:23 +0000 (03:05 +0000)]
clk: thead: Port clock controller driver of TH1520 SoC
The driver is adapted from Linux kernel's version of clk-th1520-ap.c,
with only output clocks for external sensors, which are barely useful in
bootloaders, removed.
Same as the mainline driver, it currently lacks of ability to enable and
reconfigure PLLs, which could be implemented later.
Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Yao Zi [Fri, 16 May 2025 03:05:22 +0000 (03:05 +0000)]
riscv: cpu: th1520: Initialize IOPMPs in SPL
TH1520 SoC ships several IOPMPs protecting various on-chip peripherals.
They must be configured before accessing the peripherals. Let's
initialize them in SPL harts_early_init().
Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Yao Zi [Tue, 13 May 2025 09:05:02 +0000 (09:05 +0000)]
board: thead: licheepi4a: Enable SPL support
Adjust Kconfig and defconfig and add SPL initialization code for
Lichee Pi 4A. Then enable SPL support which we've added for TH1520 SoC
earlier. The board devicetree is changed to use TH1520 binman
configuration to generate bootable images.
Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Yao Zi [Tue, 13 May 2025 09:05:01 +0000 (09:05 +0000)]
riscv: dts: th1520: Add binman configuration
Add binman configuration for TH1520 SoC, whose BROM loads the image
combined into SRAM and directly jumps to it. The configuration creates
u-boot-with-spl.bin where the SPL code locates at the start and the DDR
firmware is shipped.
Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Yao Zi [Tue, 13 May 2025 09:04:57 +0000 (09:04 +0000)]
ram: thead: Add initial DDR controller support for TH1520
This patch cleans the vendor code of DDR initialization up, converts the
driver to fit in DM framework and use a firmware[1] packaged by binman to
ship PHY configuration.
Currently the driver is only capable of initializing the controller to
work with dual-rank 3733MHz LPDDR4, which is shipped by 16GiB variants
of LicheePi 4A boards and I could test with. Support for other
configurations could be easily added later.
Yao Zi [Tue, 13 May 2025 09:04:55 +0000 (09:04 +0000)]
configs: th1520_lpi4a: Add UART clock frequency
The BROM of TH1520 always initializes UART0's parent clock and
configures the baudrate to 115200. Describe the clock frequency to make
UART function correctly in SPL without introducing CCF.
Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Yao Zi [Tue, 13 May 2025 09:04:54 +0000 (09:04 +0000)]
riscv: lib: Split out support for T-Head cache management operations
Designed before a standard set of cache management operations defined in
RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the
customized extension XTheadCMO, which has been used in the CV1800B port
of U-Boot.
This patch splits XTheadCMO-related code into a generic module, allowing
SoCs shipping T-Head cores to share the code.
E Shattow [Sat, 10 May 2025 18:42:27 +0000 (11:42 -0700)]
riscv: dts: jh7110: override syscrg assigned clock rates with defaults
JH7110 drivers are missing support for CPU frequency scaling, so override
upstream device-tree to use default clock rates for syscrg. This override
duplicates a portion of jh7110-common-u-boot.dtsi file planned for removal.
Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Leo Liang <ycliang@andestech.com>
E Shattow [Sat, 3 May 2025 11:52:52 +0000 (04:52 -0700)]
riscv: starfive: jh7110: move uart0 clock frequency to config header
Move unnecessary clock frequency assignment out of device-tree and into the
board config header so that the ns16550 serial driver can successfully init
during SPL after failing to resolve the parent clock from upstream dts. The
serial driver will then resolve clock frequency from device-tree node parent
clock at init during Main app as it is expected by upstream.
Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Yao Zi [Sun, 27 Apr 2025 14:50:11 +0000 (14:50 +0000)]
riscv: Access gd with inline assembly when building with LTO or Clang
Similar to AArch64's case, Clang may wrongly fold accesses to gd pointer
which is defined with register qualifier into constants, breaking
various components.
This patch defines gd as a macro when building with Clang or LTO, which
expands to get_gd() that accesses gp pointer in assembly, making RISC-V
ports function properly and preparing for introduction of LTO in the
future. Board initialization code is also adapted for non-assignable gd.
Reported-by: Nathaniel Hourt <I@nathaniel.land> Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Unlike ARM and X86, booting 32-bit images on 64-bit CPUs is currently
not supported for Risc-V. Hence, for bootm, disallow booting a FIT
or a legacy image that was built for an arch type which is different
than the current arch and for booti, set the arch type to be the
same as the current arch.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
mmc: cv1800b: Fix build without MMC_SUPPORTS_TUNING
That's how it looks like without CONFIG_MMC_SUPPORTS_TUNING before the
patch:
aarch64-buildroot-linux-gnu-ld.bfd: drivers/mmc/cv1800b_sdhci.o: in function `cv1800b_execute_tuning':
drivers/mmc/cv1800b_sdhci.c:47:(.text.cv1800b_execute_tuning+0x50): undefined reference to `mmc_send_tuning'
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
net, net-lwip: wget: suppress console output when called by EFI
Functions called from EFI applications should not do console output.
Refactor the wget code to implement this requirement. The wget_http_info
struct is used to hold the boolean that signifies whether the output is
allowed or not.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
net-lwip: change static function wget_loop() to be wget_do_request()
wget_do_request() currently does so little before calling the static
function wget_loop() that we may as well rename wget_loop() to
wget_do_request() and put everything in one function.
Tom Rini [Mon, 12 May 2025 21:51:23 +0000 (15:51 -0600)]
CI, docs: Install test/py/requirements.txt as well
As noted by Quentin, in CI we should be at least versioning the pytest
that we install. To avoid problems later, go with the whole requirements
file being used. Furthermore, our documentation building for readthedocs
must also have pytest so install the requirements file there as well.
Reported-by: Quentin Schulz <quentin.schulz@cherry.de> Signed-off-by: Tom Rini <trini@konsulko.com>
- mvebu_espressobin_ultra-88f3720_defconfig: enable hwrng
- kirkwood: Convert to DM_SERIAL for Kirkwood boards
- kirkwood: Convert to DM_SERIAL for Synology DS109 board
- cmd: tlv_eeprom: return after successful read from EEPROM
cyclic: make cyclic_register safe to call on already-registered info
Now that cyclic_unregister() is safe to call on a not-registered
cyclic_info, we can make cyclic_register() behave like the mod_timer()
and hrtimer_start() APIs in linux, in that they don't distinguish
between whether the timer was already enabled or not; from the point
of the call it is, with whatever timeout/period is set in that most
recent call.
This avoids users of the cyclic API from separately keeping track of
whether their callback is already registered or not, and even if they
know it is, can be used for changing the period (and/or the callback
function) without first doing unregister().
See also this recent'ish message from kernel maintainer Thomas
Gleixner on that API design for timer frameworks:
https://lore.kernel.org/lkml/87ikn6sibi.ffs@tglx/
First of all the question is whether add() and mod() are really
valuable distinctions. I'm not convinced at all. Back then, when we
introduced hrtimers, we came to the conclusion that hrtimer_start()
is sufficient.
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk> Reviewed-by: Stefan Roese <sr@denx.de>
Make cyclic_unregister() safe to call with an already unregistered, or
possibly never registered, struct cyclic_info. This is similar to how
the various timer APIs in the linux kernel work (they all allow
calling delete/cancel/... on an inactive timer object).
This means callers don't have to separately keep track of whether
their cyclic callback is registered or not, and avoids them trying to
peek into the struct cyclic_info for that information - which leads to
somewhat ugly code as it would have to be guarded by ifdef
CONFIG_CYCLIC.
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk> Reviewed-by: Stefan Roese <sr@denx.de>
Martin Schiller [Wed, 16 Apr 2025 06:13:16 +0000 (08:13 +0200)]
cmd: tlv_eeprom: return after successful read from EEPROM
Commit f6eff35b8c19 ("cmd: tlv_eeprom: handle -ENODEV error from
read_eeprom function") removed the needed 'return 0' after a successful
read. As a result, the usage message is shown when 'tlv_eeprom read' is
successfully called.
Let's fix it by adding the needed 'return 0'.
Signed-off-by: Martin Schiller <ms@dev.tdt.de> Reviewed-by: Stefan Roese <sr@denx.de>
This device has a hardware random number generator. Linux can
use this feature to randomize the location of the kernel in
memory for better security. However, that functionality is only
available if the bootloader firmware provides it. Enable support
for it in the default configuration for this device.
Signed-off-by: Benjamin Schneider <ben@bens.haus> Reviewed-by: Stefan Roese <sr@denx.de>
Thomas Schaefer [Mon, 28 Apr 2025 09:59:46 +0000 (11:59 +0200)]
net: fsl_enetc: fix imdio register calculation
With commit cc4e8af2c552, fsl_enetc register accessors have been split to
handle different register offsets on different SoCs. However, for
internal MDIO register calculation, only ENETC_PM_IMDIO_BASE was fixed
without adding the SoC specific MAC register offset.
As a result, the network support for the Kontron SMARC-sAL28 and
probably other boards based on the LS1028A CPU is broken.
Add the SoC specific MAC register offset to calculation of imdio.priv to
fix this.
Fixes: cc4e8af2c552 ("net: fsl_enetc: Split register accessors") Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> # LS1028A Tested-by: Tim Harvey <tharvey@gateworks.com> # imx95_19x19_evk Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Alice Guo <alice.guo@nxp.com>
spi: fspi: involve lut_num for struct nxp_fspi_devtype_data
The flexspi on different SoCs may have different number of LUTs.
So involve lut_num in nxp_fspi_devtype_data to make distinguish.
This patch prepare for the adding of imx8ulp.
Jonas Karlman [Sat, 10 May 2025 15:32:01 +0000 (15:32 +0000)]
clk: Fix clk_set_parent() regression
The commit ac30d90f3367 ("clk: Ensure the parent clocks are enabled
while reparenting") add a call to clk_enable() for the parent clock.
For clock drivers that do not implement the enable() ops, like most
Rockchip clock drivers, this now cause the set_parent() ops to never
be called when CLK_CCF=n (default for Rockchip).
clk_enable() typically return -ENOSYS when the enable() ops is not
implemented by the clock driver, with CLK_CCF=y clk_enable() instead
return 0 when the enable() ops is unimplemented.
Change to ignore -ENOSYS from the newly introduced clk_enable() call to
fix this regression and restore the old behavior of set_parent() ops
being called regardless of if enable() ops is implemented or not.
Fixes: ac30d90f3367 ("clk: Ensure the parent clocks are enabled while reparenting") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: Dang Huynh <danct12@riseup.net> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
* Improve the pytest documentation
* u-boot-test-reset: mention power cycling
* describe u-boot-test-release
* correct link to QEMU
* describe that RISC-V supports semihosting
UEFI:
* link libggc via PLATFORM_LIBGCC to EFI binaries
* allow suppressing ANSI output in dtbdump.efi
* test/py/test_efi_fit: test fdt and initrd
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# gpg: Signature made Sun 11 May 2025 05:54:10 AM CST
# gpg: using RSA key 2BBC0A5EDDFF6ED2FAFF203E84EE2F827137534B
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Adriano Cordova [Thu, 8 May 2025 18:30:33 +0000 (14:30 -0400)]
efi_loader: fix dtbdump output color and format
Imitate in dtbdump what initrddump does for color,
newlines and input handling. The output parsing in
the CI is strict and with the current output the CI
is not recongnizing the prompt '=>'.
Signed-off-by: Adriano Cordova <adriano.cordova@canonical.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tom Rini [Thu, 8 May 2025 21:34:44 +0000 (15:34 -0600)]
doc: pytest: Document the test_bootmenu test
Add this test to the documentation. There was already a function comment
that included the argument, so convert it to the right style to be
rendered correctly in output.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 7 May 2025 23:23:02 +0000 (17:23 -0600)]
doc: pytest: Document the test_efi_loader test
Add this test to the documentation. We need to add a code-block
annotation to the example and indent it correctly. We also need to
document the do_test_efi_helloworld_net function and that in turn means
changing the documentation to test_efi_helloworld_net_http and
test_efi_helloworld_net_tftp to reflect what is and isn't done in those
functions themselves now.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 7 May 2025 23:23:01 +0000 (17:23 -0600)]
doc: pytest: Document the test_bootstage test
Add this test to the documentation. We need to move the import to follow
the main comment so that it renders correctly, and add a code-block
annotation to the example and indent it correctly. Next, neither of the
functions had comments themselves, so document them now.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 7 May 2025 23:23:00 +0000 (17:23 -0600)]
doc: pytest: Document the test_net test
Add this test to the documentation. While the diff appears large at
first, the only changes within the test are to move the imports to
follow the pydoc comment and then to code-block and indent the example
configuration.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 7 May 2025 22:08:19 +0000 (16:08 -0600)]
doc: pytest: Document the test_net_boot test
Add the test_net_boot.py test to the generated documentation. While most
of this was already commented correctly for inclusion the biggest
problem was examples of code without a code-block notation. This in turn
broke parsing. Add the missing notations. We also must have the comment
prior to any import lines or it will not be seen as a comment on the
overall file and thus not included.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 7 May 2025 22:08:18 +0000 (16:08 -0600)]
doc: pytest: Framework for documenting tests and document test_000_version
In order to easily document pytests, we need to include the autodoc
extension. We also need to make sure that for building the docs, CI
includes pytest and that we have PYTHONPATH configured such that it will
find all of the tests and related files. Finally, we need to have our
comments in the test file by in proper pydoc format in order to be
included in the output.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 7 May 2025 22:08:17 +0000 (16:08 -0600)]
doc: Start improving our pytest documentation
Begin the work of documenting all of our pytests. To do this, we should
have a directory under develop for it as there will be a large number of
new files. As the current document is referenced externally in a number
of locations, add the sphinx_reredirects module so that we can redirect
from the old location to the new.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Vincent Stehlé [Tue, 6 May 2025 12:36:22 +0000 (14:36 +0200)]
cmd: nvedit: fix efi env -e -i command help
The help string for the `setenv -e' command shows a comma being used as
the separator between address and size for the -i option, which deals
with UEFI Variables contents passed as a buffer in memory.
This is no longer the case since commit 2b3fbcb59f41 ("efi_loader: use
':' as separator for setenv -i") and commit 8f0ac536d493 ("efi: change
'env -e -i' usage syntax"), which changed the separator from a comma to
a colon.
Therefore fix this last bit of the help string accordingly.
While at it, fix the comment of function do_env_set_efi(), which also
mentions a comma as separator.
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com> Cc: Tom Rini <trini@konsulko.com> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org> Cc: Maxim Uvarov <maxim.uvarov@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Andrew Davis [Mon, 5 May 2025 17:46:01 +0000 (12:46 -0500)]
board: ti: sec-cfg.yaml: Fix OTP write_host_id order
The write_host_id is the last element here and order does matter. This
may have gone unnoticed before as by default all elements are 0, but
if this is updated to a different host, it will not work. Update
the order so write_host_id is the last element in all current secure
board configs.
Reported-by: Prashant Shivhare <p-shivhare@ti.com> Signed-off-by: Andrew Davis <afd@ti.com>
Stephen Warren [Fri, 14 Mar 2025 18:10:31 +0000 (12:10 -0600)]
disable mail for swarren
I haven't been involved in U-Boot development for quite a while, so
CCing me on patches isn't currently useful. Add a .mailmap entry that I
believe will turn off patch CCs. This can always be removed if I become
active again! Remove myself from a few MAINTAINERS failed and the git
mailrc file too.
Tom Rini [Sat, 15 Mar 2025 01:28:45 +0000 (19:28 -0600)]
x86: Correct usage of FSP_VERSION2
As the code is today, we get a warning about "select" statements on
"choice" options not doing anything. In this case, we move to having a
"default FSP_VERSION2 if INTEL_APOLLOLAKE" in order to get the desired
outcome.
Naresh Solanki [Wed, 12 Mar 2025 09:01:15 +0000 (14:31 +0530)]
x86: spl: Add support for NVMe boot device
This change adds `BOOT_DEVICE_NVME` to the `enum` list in
`arch/x86/include/asm/spl.h`,
enabling NVMe as a recognized boot device for SPL (Secondary Program
Loader).
Tested x86 hardware with coreboot + U-Boot payload.
Verified successful boot to NVMe drive.
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Shevchenko [Fri, 18 Oct 2024 15:55:57 +0000 (18:55 +0300)]
x86: cpu: Describe board final hooks in the header
The new two declarations board_final_init() and board_final_cleanup()
need a description. Add it here.
Suggested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
ARM: tegra: set default SYS_CONFIG_NAME from SoC Kconfig
Since most boards now use the same generic device config header, move its
setup to SoC Kconfig instead of setting SYS_CONFIG_NAME in each board's
Kconfig.
The LG Optimus 2X is a touchscreen-based, slate-sized smartphone designed
and manufactured by LG that runs the Android operating system. The
Optimus 2X features a 4" WVGA display, an Nvidia Tegra 2 dual-core chip,
512 MB of RAM and extendable 8 GB of internal storage. UART-B is default
debug port.
Tested-by: Ion Agorria <ion@agorria.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
video: backlight: add Skyworks/Analogictech AAT2870 led controller driver
Add support for Skyworks AAT2870 LED Backlight Driver and Multiple LDO
Lighting Management Unit. Only backlight is supported as for now. Supported
backlight level range is from 2 to 255 with step of 1.
Tested-by: Ion Agorria <ion@agorria.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Hitachi TX10D07VM0BAA is a color active matrix TFT (Thin Film Transistor)
liquid crystal display (LCD). The resolution of a 4" contains 480 x 800
pixels.
Tested-by: Ion Agorria <ion@agorria.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
projects / thirdparty / u-boot.git / log
