arch: arm: agilex5: Enable power manager for Agilex5
Agilex5 FSBL is required to disable the power of unused peripheral SRAM
blocks to reduce power consumption.
Introducing a new power manager driver for Agilex5 which will be called
as part of Agilex5 SPL initialization process.
This driver will read the peripheral handoff data obtained from the
bitstream and will power off the specified peripheral's SRAM from the
handoff data values.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
arm: socfpga: agilex5: Sub-device check enabled for runtime workaround
Sub-device information is retrieved from the JTAG ID in Boot Scratch
Cold 4 Register. This interface is introduced to allow device-specific
errata workarounds to be applied in the future, based on the detected
sub-device type.
Signed-off-by: Tingting Meng <tingting.meng@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
arm: socfpga: agilex5: Coverity issue cleanup in jtag_usercode check
A redundant comparison (jtag_usercode >= 0) was removed from the
condition checking jtag_usercode. Since jtag_usercode is an unsigned
integer, the check for non-negativity was always true. The code was
simplified to resolve the Coverity warning.
Signed-off-by: Tingting Meng <tingting.meng@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Andrew Goodbody [Tue, 29 Jul 2025 11:50:47 +0000 (12:50 +0100)]
socfpga_dtreg: Ensure reg is initialised before use
In socfpga_dtreg_probe it is possible that if mask is 0 then reg will
not be assigned to before first use. Refactor the code slightly to
ensure that reg is always assigned to and remove a piece of duplicated
code.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Thu, 24 Jul 2025 15:19:24 +0000 (16:19 +0100)]
ddr: altera: n5x: size_t cannot be less than 0
The function socfpga_get_handoff_size returns an int so make the struct
fields used to accept the return value also an int so that testing for
less than 0 is then valid.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Wed, 23 Jul 2025 11:32:31 +0000 (12:32 +0100)]
clk: n5x: Fix misplaced paren
Smatch reported an issue about the precedence of shift being higher than
mask in clk_get_emac_clk_hz. This turned out to be a misplaced paren in
one of the calculations. Fix this by placing the paren in the same place
as in the other similar calculations in the same function.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Mon, 28 Jul 2025 11:25:29 +0000 (12:25 +0100)]
arm: socfpga: Remove unnecessary for loop
The for loop in fpgamgr_program_poll_cd will always terminate after a
single pass and so is not necessary. Remove it and all related code and
leave only the code that is effective.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
arch: arm: socfpga: Include BSD-3-Clause as license identifier
All the source code of secure_vab.c and secure_vab.h are from Intel
and Altera. Updating the license to use either GPL-2.0 or
BSD-3-Clause because this copy of code may be used for open source
and internal project.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
arch: arm: dts: agilex5: Set spi-max-freq to 50Mhz
This patch is to set spi-max-freq to 50Mhz. This will add support to the
driver to set the operation speed according to the slave device up to
50Mhz. Without this node, the driver just can adjust the operation speed
to the default speed which is far below the best
operation speed of the SPI slave device.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Patrice Chotard [Fri, 23 May 2025 09:46:58 +0000 (11:46 +0200)]
watchdog: don't autostart watchdog on STM32MP architecture
On STM32MP reference boards, the watchdog is started by a previous
boot stage (e.g. bootrom or secure OS), so the config flag
WATCHDOG_AUTOSTART is not required.
It's preferable to rely on the DT properties "u-boot,autostart" or
"u-boot,noautostart", if needed.
For backward compatibility on defconfigs that are based on SPL,
thus cannot rely on a previous boot stage for starting the
watchdog, enable WATCHDOG_AUTOSTART in their respective defconfig.
The change in stm32mp15_dhsom.config is propagated to:
- configs/stm32mp15_dhcom_basic.config
- configs/stm32mp15_dhcor_basic.config
and then to:
- stm32mp15_dhcom_basic_defconfig
- stm32mp15_dhcom_drc02_basic_defconfig
- stm32mp15_dhcom_pdk2_basic_defconfig
- stm32mp15_dhcom_picoitx_basic_defconfig
- stm32mp15_dhcor_avenger96_basic_defconfig
- stm32mp15_dhcor_basic_defconfig
- stm32mp15_dhcor_drc_compact_basic_defconfig
- stm32mp15_dhcor_testbench_basic_defconfig
Add a mean to check the IWDG status based on the peripheral version.
This is done by either checking the status bit ONF either by updating
the reload register with the same value and check if the reload succeed.
Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Antonio Borneo [Fri, 23 May 2025 09:46:56 +0000 (11:46 +0200)]
watchdog: arm_smc_wdt: get wdt status through SMCWD_GET_TIMELEFT
The optional SMCWD_GET_TIMELEFT command can be used to detect if
the watchdog has already been started.
See the implementation in OP-TEE secure OS [1].
At probe time, check if the watchdog is already started and then
call wdt_set_force_autostart(). This will keep U-Boot pinging the
watchdog even when the property 'u-boot,noautostart' is present.
The watchdog could have been already started by a previous boot
stage (e.g. bootrom or secure OS). U-Boot has to start and kick
the watchdog even when CONFIG_WATCHDOG_AUTOSTART is not enabled
or when the DT property u-boot,noautostart is present.
Add the helper wdt_set_force_autostart() that can be called by the
driver's probe() when it detects that the watchdog has already
been started and is running.
Two small fixes for binman (bintool). The first patch avoids a warning,
the second one makes sure the APT package list is up-to-date when
running apt_install(). That one fixes a CI issue I encountered.
binman: bintool: run 'apt-get update -y' on first invocation of apt_install()
'apt-get update -y' may be required to make sure that the list of
packages is up-to-date and that the subsequent 'apt-get install'
operations can find the requested packages.
The 'apt' command is not meant to be used in scripts or tools. Please
see the man page [1] for details. Therefore, use 'apt-get' instead.
This avoids the following warning:
WARNING: apt does not have a stable CLI interface. Use with caution in scripts.
tools: mips-relocs: replace format string introducers
The statement that prints the ELF object type value assumes that "%lx"
(long unsigned int, hexadecimal) is suitable for printing a uint64_t
typed value. While this may seem to work for some machines, ie. amd64,
it isn't ideal on a 32-bit system, such as x86 where uint64_t is likely
to be equivalent to a long long unsigned int, as indicated by:
../tools/mips-relocs.c:275:34:
warning: format '%lx' expects argument of type 'long unsigned int',
but argument 2 has type 'uint64_t'
{aka 'long long unsigned int'} [-Wformat=]
275 | printf("type 0x%lx\n", ehdr_field(e_type));
| ~~^
| |
| long unsigned int
| %llx
As the ehdr_field function-like macro expands to a uint64_t value,
it is better to use the PRIx64 macro in place of "%lx" to ensure that
the correct format string introducer is specified for the actual type
hiding behind uint64_t.
A similar issue is also present in the report of .rel section overflow,
where "%lx" is used to print a few size_t typed values, and would be
better served by "%zx" instead.
Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za> Fixes: 963014641117 ("MIPS: make size of relocation table fixed but configurable") Fixes: 703ec9ddf965 ("MIPS: Stop building position independent code") Cc: Paul Burton <paulburton@kernel.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Masahiro Yamada <masahiroy@kernel.org>
Andrew Goodbody [Wed, 23 Jul 2025 10:34:36 +0000 (11:34 +0100)]
bios_emulator: Add parens to xorl macro
The xorl macro lacked surrounding parens which meant that it could have
unexpected results when used in expressions. Fix this by adding the
surrounding parens to make its use predictable.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Wed, 23 Jul 2025 10:34:35 +0000 (11:34 +0100)]
bios_emulator: Fix buffer overflow
Using strcpy to copy a 4 character string into a 4 byte field in a
structure will overflow that field as it writes the terminating \0 into
the following field. Correct this by using memcpy instead.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Fri, 18 Jul 2025 12:19:54 +0000 (13:19 +0100)]
spl: NULL check variable before dereference
In boot_from_devices the variable loader is not NULL checked after
assignment and before first use but later code does check it for NULL.
Add a NULL check before first use.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Patrick Delaunay [Mon, 28 Jul 2025 07:19:33 +0000 (09:19 +0200)]
ARM: stm32: fix PRE_CON_BUF_ADDR on STM32MP13
Since SYS_MALLOC_F_LEN increasing to 0x2100000 on STM32MP13, the
pre-console buffer is overlapped by stack (0xC0400000 + 0x2100000),
so the this buffer must be moved just before the bootstage to avoid issue.
After this patch the pre-relocation memory mapping for STM32MP13x is:
C3000000 = Bootstage CONFIG_BOOTSTAGE_STASH_ADDR C2FFF000 = PreConsole CONFIG_PRE_CON_BUF_ADDR
with size CONFIG_PRE_CON_BUF_SZ = 4096 C0400000 = start for stack with CONFIG_CUSTOM_SYS_INIT_SP_ADDR
including CONFIG_SYS_MALLOC_F_LEN C0000000 = Load Address of U-Boot with CONFIG_TEXT_BASE
Fixes: 93c962c7af7e ("configs: stm32mp13: increase SYS_MALLOC_F_LEN to 0x210000") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Patrice Chotard [Thu, 26 Jun 2025 08:08:45 +0000 (10:08 +0200)]
ARM: stm32mp: Add STM32MP23 support
Add STM32MP23 support which is a cost optimized of STM32MP25.
More details available at:
https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html
Marek Vasut [Mon, 30 Jun 2025 00:10:36 +0000 (02:10 +0200)]
ARM: dts: stm32: Switch defconfig to SPL for DH STM32MP13xx DHCOR DHSBC
Update defconfig to make use of U-Boot SPL to initialize DH STM32MP13xx
DHCOM DHSBC SoM and board. This is largely a move of SPL enablement from
DH STM32MP15xx DHSOM defconfigs into generic DH STM32MP1xx defconfig .
Support for SPI NOR chips which are not used on STM32MP13xx DHCOR are
moved into STM32MP15xx DHSOM defconfigs. Changes to STM32MP13xx DHCOR
defconfig then enable SPL support, CCF in SPL to configure clock, pin
configuration support in SPL, and OpTee OS start support in U-Boot.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Add SPL specific DT additions to DH STM32MP13xx DHCOR DHSBC . These
include I2C3 configuration which is required to access the PMIC,
PMIC regulator and QSPI NOR bootph-all properties to allow SPL to
configure PMIC buck regulators and load from QSPI NOR respectively,
etzpc bus switch to simple-bus to prevent interference from TFABOOT
specific configuration, and RCC configuration to define clock tree
configuration used by this platform.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Marek Vasut [Mon, 30 Jun 2025 00:10:34 +0000 (02:10 +0200)]
ARM: dts: stm32: Add STM32MP13x SPL specific DT additions
Add DT additions required by U-Boot SPL to bring up the hardware.
This includes binman node to generate STM32 Image v2.0 which can be
booted by the BootROM, clock entries used by the SPL clock driver
during clock tree initialization, and syscon-reboot node so U-Boot
can reset the system without having to rely on PSCI call.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Marek Vasut [Mon, 30 Jun 2025 00:10:32 +0000 (02:10 +0200)]
ARM: dts: stm32: Add stm32mp13-ddr.dtsi template
Factor out common parts of STM32MP15xx DRAM controller configuration DT
description into stm32mp1-ddr.dtsi and introduce stm32mp13-ddr.dtsi which
describes STM32MP13xx DRAM controller configuration in DT.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Add default STM32MP13xx debug UART initialization. This is similar
to STM32MP15xx debug UART initialization, except the RCC registers
are at different offsets and the UART pinmux pins are different.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Marek Vasut [Mon, 30 Jun 2025 00:10:30 +0000 (02:10 +0200)]
ARM: stm32: Add STM32MP13xx PMIC initialization for DDR3 DRAM type
The STM32MP13xx PMIC initialization for DDR3 DRAM type is similar
to the STM32MP15xx PMIC initialization, except the VTT rail is not
enabled. Fill in the STM32MP13xx support.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Marek Vasut [Mon, 30 Jun 2025 00:10:29 +0000 (02:10 +0200)]
ARM: stm32: Limit early cache enablement in SPL to STM32MP15xx
The STM32MP13xx SRAM size is half that the SRAM size on STM32MP15xx,
disable early dcache start on STM32MP13xx as the TLB itself takes
about a quarter of the SPL size. The dcache will be enabled later,
once DRAM is available and TLB can be placed in DRAM.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Add hardware initialization for the STM32MP13xx in SPL. This is
similar to STM32MP15xx except the code has to enable MCE to bring
DRAM controller up later.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Marek Vasut [Mon, 30 Jun 2025 00:10:27 +0000 (02:10 +0200)]
ARM: stm32: Add STM32MP13xx SPL Kconfig options
Introduce Kconfig options used by SPL on STM32MP13xx and isolate
the Kconfig options only used in case TFA BL2 is used as a SPL
behind CONFIG_TFABOOT dependency.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Andrew Goodbody [Thu, 24 Jul 2025 11:37:38 +0000 (12:37 +0100)]
clk: stm32: Wrong macros used in register read
Smatch reported a warning about a shift macro being used as a mask. Make
the obvious changes to make this register read calculation work the same
as the previous ones.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Alice Guo [Mon, 7 Jul 2025 20:20:34 +0000 (04:20 +0800)]
clk: scmi: Fix clock identifier passed to struct scmi_clk_parent_set_in
Commit aa7bdc1af505 ("clk: scmi: manage properly the clk identifier with
CFF") enables CONFIG_CLK_AUTO_ID, so need to use clk_get_id() to get the
real SCMI CLK ID, otherwise wrong ID is used when set clk parent.
Fixes: aa7bdc1af505 ("clk: scmi: manage properly the clk identifier with
CCF")
Signed-off-by: Alice Guo <alice.guo@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Marek Vasut [Mon, 30 Jun 2025 00:09:07 +0000 (02:09 +0200)]
reset: stm32: Fix header misuse
The stm32-reset-core.h is located in drivers/reset/stm32/ , it has to
be included using "stm32-reset-core.h" and not <stm32-reset-core.h> ,
otherwise the build fails. Fix it.
Cheick Traore [Fri, 20 Jun 2025 15:50:00 +0000 (17:50 +0200)]
configs: stm32mp25: Enable MFD timer and PWM for stm32mp25_defconfig
Enable the following configs:
- CONFIG_MFD_STM32_TIMERS: enables support for the STM32 multifunction
timer
- CONFIG_DM_PWM: enables support for pulse-width modulation devices
- CONFIG_CMD_PWM: enables 'pwm' command to control PWM channels
- CONFIG_PWM_STM32: enables support for the STM32 PWM devices
Cheick Traore [Fri, 20 Jun 2025 15:49:59 +0000 (17:49 +0200)]
pwm: stm32: add support for stm32mp25
Add support for STM32MP25 SoC.
IPIDR register is used to check the hardware configuration register
when available to gather the number of complementary outputs.
Cheick Traore [Fri, 20 Jun 2025 15:49:58 +0000 (17:49 +0200)]
arm: stm32mp2: add multifunction timer support for stm32mp25
Add support for STM32MP25 SoC.
Identification and hardware configuration registers allow to read the
timer version and capabilities (counter width, ...).
So, rework the probe to avoid touching ARR register by simply read the
counter width when available. This may avoid messing with a possibly
running timer.
Also add useful bit fields to stm32-timers header file.
Tom Rini [Wed, 2 Jul 2025 01:04:05 +0000 (19:04 -0600)]
spi: mvebu: Correct dependencies on MVEBU_A3700_SPI
A dependency exposed by "make allyesconfig" is that the logic around
this symbol was not quite correct. It needs to depend on ARCH_MVEBU and
ARM64 and then select CLK_MVEBU.
Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefan Roese <sr@denx.de>
Tony Dinh [Mon, 23 Jun 2025 20:59:43 +0000 (13:59 -0700)]
arm: kirkwood: Enable bootstd and other modernization for ib62x0 board
Enable bootstd.
Update defconfigs to the latest u-boot requirements.
Enable SYS_THUMB_BUILD and LTO and to reduce binary size.
Enable NET_RANDOM_ETHADDR.
Disable JFFS2 support.
Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
In a private fork, it's not unreasonable to commit various binary
files associated to one's project, and thus put a suitable
.gitattributes file next to it to force git to treat that file as
binary. In my case, I have a .xslx spreadsheet used for computing
suitable RAM timing tables, which I wanted to put in
board/<vendor>/<project>. Git duly warned me that it would do LF/CRLF
mangling, so I also added a .gitattributes file next to it with
*.xlsx binary
but upon adding that file, git told me that I'd have to use -f because
it's a dot-file that is by default ignored.
Add .gitattributes to the list of dot-files that should not be
ignored.
While in here, sort the list and update the comment, as there are also
files which git itself does not make use of in the list, cf. linux
commit f46e65da48b2 (".gitignore: exclude .get_maintainer.ignore and
.gitattributes").
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk> Reviewed-by: Tom Rini <trini@konsulko.com>
Andrew Goodbody [Mon, 21 Jul 2025 14:43:36 +0000 (15:43 +0100)]
cmd: elf: Prevent possible buffer overflow
In do_bootvx the environment variable 'bootdev' is fetched and copied
into a buffer without confirming that it will not overflow that buffer.
Use strlcpy to ensure that the buffer will not be overflowed.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Tom Rini [Mon, 28 Jul 2025 14:08:16 +0000 (08:08 -0600)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
These patches add support for the new Allwinner A523/A527/T527 SoC (all
same die), alongside with defconfigs for three boards using one of those
SoCs.
The patches are the usual combination of refactoring (of the SPL clock
code this time), tweaks to existing drivers to support peripherals in
their A523 versions, and new drivers for pincontrol and clocks. A big
chunk is of course the DRAM controller init routines, many thanks to
Jernej and Mikhail for providing this code, after a big reverse
engineering effort.
Since the DTs for the three supported boards have been merged into the
kernel repo recently, this is concluded by cherry-picks of those
patches, and the defconfig files to finally enable booting those boards.
The patches have been sitting around for a while, and folks are already
using them, so it's now time to get them into the tree.
Gitlab CI passed, and I booted that briefly on those three boards, plus
on some other SoCs to spot potential regressions.
Andre Przywara [Tue, 21 Jan 2025 21:55:07 +0000 (21:55 +0000)]
sunxi: A523: add defconfigs for three boards
So far developers seem to use three popular boards:
- Avaota A1: dev board with USB 3.0, dual Ethernet, small display
- X96QPro+: TV box with Gigabit Ethernet, USB 3.0, eMMC
- Radxa A5E: small dev board with USB3/M.2 2230 (muxed), dual Ethernet
Add the defconfig files for those boards, containing the DRAM parameters
and the usual Kconfig options.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Fri, 7 Mar 2025 00:57:08 +0000 (00:57 +0000)]
arm64: dts: allwinner: a523: add Avaota-A1 router support
The Avaota A1 router board is an Open Source hardware board, designed
by YuzukiHD. Pine64 produces some boards and sells them. It uses the
Allwinner A527 or T527 SoC, and comes with the following features:
- Eight ARM Cortex-A55 cores, Mali-G57 MC1 GPU
- 1GiB/2GiB/4GiB LPDDR4 DRAM
- AXP717 + AXP323 PMIC
- Raspberry-Pi-2 compatible GPIO header
- 1 USB 2.0 type A host port, 1 USB 3.0 type A host post
- 1 USB 2.0 type C port (OTG + serial debug)
- MicroSD slot
- eMMC between 16 and 128 GiB
- on-board 16MiB bootable SPI NOR flash
- two 1Gbps Ethernet ports (via RTL8211F PHYs)
- HDMI port
- DP port
- camera and LCD connectors
- 3.5mm headphone jack
- (yet) unsupported WiFi/BT chip
- 1.3" LC display, connected via SPI
- 12 V barrel plug for power supply
Add the devicetree file describing the currently supported features.
Andre Przywara [Fri, 7 Mar 2025 00:57:10 +0000 (00:57 +0000)]
arm64: dts: allwinner: a523: add Radxa A5E support
The Radxa A5E is a development board using the Allwinner A527 SoC, which
is using the same die as the A523 SoC, just exposing the pins of more
peripherals (like HDMI or the 2nd MAC). The board features:
- Allwinner A527/T527 SoC: 8 ARM Cortex-A55 cores, Mali-G57 MC1 GPU
- 1GiB/2GiB/4GiB LPDDR4 DRAM
- AXP717 + AXP323 PMICs
- Raspberry-Pi-2 compatible 40pin GPIO header
- 1 USB 2.0 type C port (OTG), also power supply
- 1 USB 3.0 type A host port (multiplexed with M.2 slot)
- 1 M.2 M-key 2230 slot, with 1 PCIe2.1 lane connected (multiplexed
with USB 3.0 port)
- MicroSD slot
- optional eMMC, 8, 16 or 32GB available
- optional on-board 16MiB bootable SPI NOR flash
- two 1Gbps Ethernet ports (via MAXIO MAE0621A PHYs)
- PoE header for optional supply circuit on one Ethernet port
- WiFi 802.11 a/b/g/n/ac/ax (LB-Link BL-M8800DS2 module using AIC8800)
- HDMI port
- camera and LCD connectors
- power supply via USB-C connector (but no PD) or GPIO header pins
This .dts describes the devices as far as we support them at the moment.
The PMIC rails have been assigned as per the schematics.
Andre Przywara [Fri, 7 Mar 2025 00:57:09 +0000 (00:57 +0000)]
arm64: dts: allwinner: a523: add X96Q-Pro+ support
The X96QPro+ is a TV box using the Allwinner H728 SoC. That SoC seems to
be a package variant of the A523 family, at least it uses the same SoC
ID and is compatible as far as we can assess.
It comes with the following specs:
- Allwinner H728 SoC: 8 Arm Cortex-A55 cores, Mali-G57 MC1 GPU
- 2 or 4GiB DDR3L DRAM
- 32, 64, or 128 GiB eMMC flash
- AXP717 + AXP323 PMICs
- Gigabit Ethernet (using MAXIO PHY)
- HDMI port
- 2 * USB 2.0 ports
- 1 * USB 3.0 port
- microSD card slot
- TOSLINK digital audio output
- 3.5mm A/V port
- infrared sensor
- 7-segment display
- 5V barrel plug power supply
- power button
The PCB provides holes for soldering a UART header or cable, this is
connected to the debug UART0. There is another set of UART pins
available. The board also features a FEL button (accessible through the
3.5mm socket) and a reset button (only accessible when case is open).
This .dts just describes the basic peripherals as far as we support them
at the moment. The PMIC rail assignments are reverse engineered as far
as possible, by dumping them from a running Android system, and correlating
them to other boards using the same SoC.
The Allwinner A523, and its siblings A527 and T527, which share the same
die, are a new family of SoCs introduced in 2023. They features eight
Arm Cortex-A55 cores, and, among the other usual peripherals, a PCIe and
USB 3.0 controller.
Add the basic SoC devicetree .dtsi for the chip, describing the
fundamental peripherals: the cores, GIC, timer, RTC, CCU and pinctrl.
Also some other peripherals are fully compatible with previous IP, so
add the USB and MMC nodes as well.
The other peripherals will be added in the future, once we understand
their compatibility and DT requirements.
Add reverse engineered code to add support for DDR3 DRAM chips on the
Allwinner A523 DRAM controller.
The timings are copying what boot0 set up on the X96QPro+ TV box, though
they seem quite suboptimal, with longer latencies that would be required
for DDR3-1600. The chips are also actually capable of DDR3-1833, so
there is room for future improvement.
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
[Andre: rework to copy from H616 DDR3 driver, calculate timings] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Jernej Skrabec [Sun, 29 Dec 2024 20:13:13 +0000 (21:13 +0100)]
sunxi: A523: add DRAM initialisation routine
DRAM init code, as per reverse engineering and matching against
previous SoCs. As usual no real documentation, and the DRAM controller
is the usual mixture of close-to-previous IP and new inventions.
This version supports LPDDR4 for now only, as seen on the early boards.
This needs improvements, but it can be done later.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Jernej Skrabec [Sat, 24 Aug 2024 16:58:28 +0000 (17:58 +0100)]
sunxi: sun50i_h6: add A523 SPL clock setup code
This adds the early A523 clock setup code, for the basic peripheral PLL
and the basic bus clocks (APB/AHB). This is quite close to the existing
H6 and H616 clock code, so this shares the same file. A few bits and bobs
are different, though, so filter for the A523 in a few occasions.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 2 Jan 2025 00:52:27 +0000 (00:52 +0000)]
sunxi: update cpu_sunxi_ncat2.h
The cpu_sunxi_ncat2.h header file contains addresses of some peripherals
that are needed for the SPL, for chips that belong to the "NCAT2"
generation.
The Allwinner A523 is a member of this group, but a few addresses
differ, and we need a few more addresses, for playing with the core
reset, for instance.
Add the new addresses needed for the A523 and guard existing definitions
that conflict with that new chip.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 12 Sep 2024 01:19:45 +0000 (02:19 +0100)]
sunxi: mmc: add support for Allwinner A523 MMC mod clock
The Allwinner A523 SoC has a slightly changed mod clock, where the P
factor, formerly a shift value, is now a second divider value.
Also the input clock is not PLL_PERIPH0 (600MHz) anymore, but
PLL_PERIPH0_400M (for MMC0/1), so adjust the input rate calculation
accordingly. MMC2 has a different set of parents, so the input clock
is 800 MHz there.
Adjust for all of this.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The new DT pinctrl binding would allow us to read the pinmux values from
the DT, but it is actually easier to just continue with hardcoding the
mux values in the driver, and matching them against the "function" name.
Add the values for the primary and secondary pin controller on the A523.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Fri, 13 Sep 2024 08:01:00 +0000 (09:01 +0100)]
clk: sunxi: Add support for the A523 -R CCU
Add a clock driver for the PRCM clock controller on the Allwinner A523
family of SoCs, often also used with an "r" prefix or suffix.
This just describes the clock gates and reset lines for the few devices
that we would need, most prominently the R_I2C device for the PMIC.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Mon, 9 Sep 2024 00:47:31 +0000 (01:47 +0100)]
clk: sunxi: Add support for the A523 CCU
Add a clock driver for the main clock controller on the Allwinner A523
family of SoCs.
As usual, this just describes the clock gates and reset lines for the
few device that U-Boot cares about: USB, Ethernet, MMC, I2C, SPI.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sun, 29 Dec 2024 20:13:13 +0000 (21:13 +0100)]
sunxi: spl: add support for Allwinner A523 watchdog
The watchdog in the Allwinner A523 SoC differs a bit from the one in the
previous SoCs: it lives in a separate register frame, so no longer
inside some timer device, and it manages to shuffle around some
registers a bit. But it also conveniently adds a direct reset
functionality, so we don't need to use a dummy timeout period.
Avoid introducing a new MMIO register frame C struct, but just define
the one needed register offset as a macro. Then just trigger this new
direct reset functionality in the A523 specific reset_cpu()
implementation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2025 13:41:37 +0000 (13:41 +0000)]
sunxi: clock: H6: add A523 CPU PLL support
The Allwinner A523 features 8 CPU cores, organised in two clusters, both
driven by separate PLLs. Also there is the DSU PLL, which clocks the
hardware that connects the cores to the rest of the system.
And while the PLL registers itself are very similar, they are located in
a separate register frame, outside the main CCU, and also the register
controlling the CPU clock source (mux) is different.
Provide a separate function that reparents the two clusters and the DSU,
while their PLLs are programmed. For the actual PLL programming, we rely
on the existing shared routine.
The selection between the new A523 routine and the existing code is made
with C if statements, but since the choice is effectively made at compile
time already, the compiler optimises away the other code paths, leaving
just the one required function in.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2025 13:40:05 +0000 (13:40 +0000)]
sunxi: clock: H6: factor out H6/H616 CPU clock setup
When we program the CPU PLL, we need to switch the CPU clock source away
from the PLL temporarily, then switch it back, once the PLL has
stabilised.
The CPU CLK register will be different on the A523, so move the current
code into a separate function, to allow using a different version of
that later for the A523.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2025 13:29:34 +0000 (13:29 +0000)]
sunxi: clock: H6: factor out clock_set_pll()
The SPL initial clock setup code for the Allwinner H6 and H616 SoCs uses
a simple CPU PLL setup routine, which programs all register bits at once,
then waits for the LOCK bit to clear.
The manual suggests to follow a certain procedure for bringing up any
PLLs, which involves several register writes, one at a time, and some
delays. Also the H616 and the new A523 require some tiny changes in this
sequence, and the different SoCs also feature some extra bits here and
there, which we should not just clear.
So factor out the PLL setup routine, and make it follow the manual's
suggestion. This will read the PLL register at the beginning, then tweak
the bits we need to manipulate, and writes the register several times on
the way. This allows to cover the specific bits for different SoCs.
Besides improving the reliability of the PLL setup, this helps with the
A523, which requires *three* CPU PLLs to be programmed.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* update FIT signature testing instructions
* describe defconfigs for AM69-SK
UEFI:
* provide unit test for system table pointer
* efi_realloc() must check efi_alloc() return value
* correct EFI_DEBUG_TABLE_ENTRY_SIZE
* avoid NULL dereference in ESRT creation tests
* add missing check in FMP.GetImageInfo()
* rename lib/efi to lib/efi_client
* rename CONFIG_EFI to CONFIG_EFI_CLIENT
* create a new CONFIG_EFI
* update maintainers for EFI_CLIENT
efi_loader: add missing check in FMP.GetImageInfo()
The UEFI 2.11 specification, chapter 23.1.3 requires
EFI_FIRMWARE_MANAGEMENT_PROTOCOL.GetImageInfo() to return
EFI_INVALID_PARAMETER if *ImageInfoSize is not too small
and ImageInfo is NULL.
Fixes: f27c20148511 ("efi_loader: add firmware management protocol for FIT image") Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
With the current code we allocate to little memory when adding entries to
the EFI_DEBUG_INFO_TABLE and we fail to correctly move entries when an
entry is removed.
EFI_DEBUG_TABLE_ENTRY_SIZE must be the size of an entry in the
EFI_DEBUG_INFO_TABLE, not the size of a pointer.
Simon Glass [Wed, 28 May 2025 16:03:16 +0000 (10:03 -0600)]
efi: Create a new CONFIG_EFI
Create a Kconfig which indicates that EFI functionality is in use,
either as a client (EFI app / stub) or provider (EFI loader). This will
make it easier to share code between these two parts of U-Boot
Tom Rini [Fri, 25 Jul 2025 19:03:01 +0000 (13:03 -0600)]
Docker, CI: Update to latest Ubuntu and Dockerfile
- Update to Ubuntu "Jammy" 20250714 tag
- Update to current Dockerfile which brings us QEMU 10.0.2 and newer
coreboot and pulls in lz4 via the non-legacy package name.
Tom Rini [Fri, 25 Jul 2025 16:55:45 +0000 (10:55 -0600)]
Merge patch series "CI: Disable sifive_unleashed_sdcard QEMU testing"
This series from myself brings CI up to using QEMU 10.0.2 for platforms.
We need to disable one test for now while a report to upstream QEMU is
resolved and also need to now update coreboot in order to be able to
build a version of it non-interactively (source locations have changed).
Tom Rini [Wed, 16 Jul 2025 00:15:37 +0000 (18:15 -0600)]
CI: Disable sifive_unleashed_sdcard QEMU testing
Changes in upstream QEMU have lead to this specific configuration of the
sifive_unleashed platform not working in QEMU. Until this can be
root caused and resolved, disable this test for now.
projects / thirdparty / u-boot.git / log
