]> git.ipfire.org Git - thirdparty/u-boot.git/log
thirdparty/u-boot.git
5 months agoufs: core: include missing include/ufs.h
Neil Armstrong [Mon, 30 Dec 2024 10:30:55 +0000 (11:30 +0100)] 
ufs: core: include missing include/ufs.h

Add missing ufs.h causing build warning on some symbols.

Tested-by: Love Kumar <love.kumar@amd.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Link: https://lore.kernel.org/r/20241230-topic-ufs-cleanup-v2-1-4c6d7994a45d@linaro.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
5 months agoboard: odroid-n2: Update docs for signing
Baltazár Radics [Fri, 10 Jan 2025 11:11:24 +0000 (12:11 +0100)] 
board: odroid-n2: Update docs for signing

The previous instructions resulted in a bootloader that wouldn't fit in
an MBR gap. I have updated the docs based on upstream's build process.

Signed-off-by: Baltazár Radics <baltazar.radics@gmail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250110111335.9221-1-baltazar.radics@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
5 months agoarch: arm: meson: support Amlogic chip_id v1 and v2
Evgeny Bachinin [Mon, 10 Feb 2025 17:50:16 +0000 (20:50 +0300)] 
arch: arm: meson: support Amlogic chip_id v1 and v2

Patch introduces:
* chip_id API - useful for various things, but used now for
  device_id (did) generation as mentioned in [1] on our private board
  code. Our device_id is calculated by means of permutations of
  chip_id value.
* new SoCs (a1, s4, etc) are usually coming with the support of chip_id
  v2 right away, whereas secure monitors on old SoCs (like axg, g12b,
  g12a, etc) may support only chip_id v1. Chip_id API handles both
  cases
* meson_sm_get_serial() is described via chip_id API.

Links:
[1] https://lore.kernel.org/linux-arm-kernel/202311242104.RjBPI3uI-lkp@intel.com/T/#m630fbeea6a6e7d531290b5c0af205af4fb979757

Signed-off-by: Viacheslav Bocharov <adeep@lexina.in>
Co-developed-by: Arseniy Krasnov <avkrasnov@salutedevices.com>
Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com>
Signed-off-by: Evgeny Bachinin <EABachinin@salutedevices.com>
Link: https://lore.kernel.org/r/20250210-meson_chip_id_all_vers-v1-3-b98f8b6880b8@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
5 months agoarm: meson: sm: get rid of SM_CHIP_ID_SIZE
Evgeny Bachinin [Mon, 10 Feb 2025 17:50:15 +0000 (20:50 +0300)] 
arm: meson: sm: get rid of SM_CHIP_ID_SIZE

SM_CHIP_ID_SIZE is used nowhere. Moreover, it specifies wrong
chip_id size: Amlogic chip_id v1 and v2 is always 16 bytes long.

Signed-off-by: Evgeny Bachinin <EABachinin@salutedevices.com>
Link: https://lore.kernel.org/r/20250210-meson_chip_id_all_vers-v1-2-b98f8b6880b8@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
5 months agoarm: meson: unify type being used for socinfo
Evgeny Bachinin [Mon, 10 Feb 2025 17:50:14 +0000 (20:50 +0300)] 
arm: meson: unify type being used for socinfo

socinfo_ API uses u32 type, hence let's use it everywhere
for consistency.

Signed-off-by: Evgeny Bachinin <EABachinin@salutedevices.com>
Link: https://lore.kernel.org/r/20250210-meson_chip_id_all_vers-v1-1-b98f8b6880b8@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
5 months agocheckpatch.pl: Report an error for CONFIG_xPL_BUILD in device trees
Hendrik Donner [Thu, 6 Mar 2025 20:15:39 +0000 (21:15 +0100)] 
checkpatch.pl: Report an error for CONFIG_xPL_BUILD in device trees

The defines for the different build phases shouldn't be used in device
trees, currently they aren't even defined for device tree pre processing,
resulting in build errors.

Link: https://lists.denx.de/pipermail/u-boot/2025-March/582787.html
Signed-off-by: Hendrik Donner <hd@os-cillation.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
5 months agodumpimage: fix handling of StarFive SPL too long
Heinrich Schuchardt [Tue, 4 Mar 2025 16:04:03 +0000 (17:04 +0100)] 
dumpimage: fix handling of StarFive SPL too long

The header of the StarFive U-Boot SPL file u-boot-spl.normal.out has a
field indicating the payload size. When copying U-Boot SPL from a
partition the copied file might be too long.

Currently in this situation a misleading error message 'Incorrect CRC32' is
written.

We must use the payload size and not the file size when calculating the
CRC32.

Write a warning if the file is too long indicating the correct size. This
enables the user to truncate the file accordingly.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
5 months agoqconfig: Correct unhashable-type error with --scan-source
Simon Glass [Thu, 27 Feb 2025 19:27:19 +0000 (12:27 -0700)] 
qconfig: Correct unhashable-type error with --scan-source

This gives an error with newer Python version, so fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 months agoscripts: typos in event_dump.py
Heinrich Schuchardt [Thu, 20 Feb 2025 10:00:13 +0000 (11:00 +0100)] 
scripts: typos in event_dump.py

%s/even spies/event spies/
%s/EFL/ELF/

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
5 months agoconfigs: phycore_am62ax_a53_defconfig: Add SoM overlays to OF_OVERLAY_LIST
Wadim Egorov [Wed, 5 Mar 2025 04:58:38 +0000 (05:58 +0100)] 
configs: phycore_am62ax_a53_defconfig: Add SoM overlays to OF_OVERLAY_LIST

Include SoM dt-overlays for DT control so we can include them
into our u-boot FIT image.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
5 months agoarm: dts: k3-am62a-phycore-som-binman: Add SoM overlays
Wadim Egorov [Wed, 5 Mar 2025 04:58:37 +0000 (05:58 +0100)] 
arm: dts: k3-am62a-phycore-som-binman: Add SoM overlays

Include SoM dt-overlays that handle variants of our SoMs into
u-boot's FIT image.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
5 months agoboard: phytec: common: Add phyCORE-AM62Ax
Daniel Schultz [Wed, 5 Mar 2025 04:58:36 +0000 (05:58 +0100)] 
board: phytec: common: Add phyCORE-AM62Ax

Add the phyCORE-AM62Ax to our common board directory to
enable our SOM detection for this product.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
5 months agoboard: phytec: common: k3: Make configure_capsule_updates() static
Wadim Egorov [Wed, 5 Mar 2025 04:58:35 +0000 (05:58 +0100)] 
board: phytec: common: k3: Make configure_capsule_updates() static

This function is only used in the board.c file. Make it static.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
5 months agoarch: arm: dts: k3-am625-phyboard-lyra: Add missing boot phase tag
Wadim Egorov [Wed, 5 Mar 2025 04:58:34 +0000 (05:58 +0100)] 
arch: arm: dts: k3-am625-phyboard-lyra: Add missing boot phase tag

Add the bootph-all tag to usb0_phy_ctrl node to ensure it is
properly initialized during the boot process. This fixes the
following issue:

  dwc3-am62 dwc3-usb@f900000: unable to get ti,syscon-phy-pll-refclk regmap

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
5 months agoarch: arm: dts: k3-am62a7-phyboard-lyra: Add missing boot phase tag
Wadim Egorov [Wed, 5 Mar 2025 04:58:33 +0000 (05:58 +0100)] 
arch: arm: dts: k3-am62a7-phyboard-lyra: Add missing boot phase tag

Add the bootph-all tag to usb0_phy_ctrl node to ensure it is
properly initialized during the boot process. This fixes the
following issue:

  dwc3-am62 dwc3-usb@f900000: unable to get ti,syscon-phy-pll-refclk regmap

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
5 months agoboard: phytec: phycore_am62ax: Add Network/SPI/DFU env variables
Wadim Egorov [Wed, 5 Mar 2025 04:58:32 +0000 (05:58 +0100)] 
board: phytec: phycore_am62ax: Add Network/SPI/DFU env variables

Include the boot logic to boot via Network, from a OSPI/QSPI
NOR flash or via USB DFU.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
5 months agoboard: phytec: phycore_am62x: Use custom k3_dfu.env fragment
Wadim Egorov [Wed, 5 Mar 2025 04:58:31 +0000 (05:58 +0100)] 
board: phytec: phycore_am62x: Use custom k3_dfu.env fragment

TI's k3_dfu.env includes redundant dfu_alt_info_* data, some of which
is incompatible with our board configuration. Replace it with a custom
variant that better aligns with our setup, ensuring correct offsets and
eliminating unnecessary entries.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
5 months agoconfigs: Add phycore_am62ax_r5_usbdfu_defconfig
Wadim Egorov [Wed, 5 Mar 2025 04:58:30 +0000 (05:58 +0100)] 
configs: Add phycore_am62ax_r5_usbdfu_defconfig

This config includes the phycore_am62ax_r5_defconfig file as well as
the am62x_r5_usbdfu.config fragment. We need another defconfig
because the AM62Ax has not enough internal SRAM to support all boot
sources. The normal phycore_am62ax_r5_defconfig should allow to boot
from MMC and OSPI while this new defconfig allows to boot from USB.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
5 months agodoc: phytec: k3: Add a common part for Environment and EFI Capsules
Wadim Egorov [Wed, 5 Mar 2025 04:58:29 +0000 (05:58 +0100)] 
doc: phytec: k3: Add a common part for Environment and EFI Capsules

Provide a common part for our K3 based boards including general details
about environment handling and EFI capsule updates.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
5 months agoconfigs: phycore_am62ax_a53_defconfig: Enable capsule update
Wadim Egorov [Wed, 5 Mar 2025 04:58:28 +0000 (05:58 +0100)] 
configs: phycore_am62ax_a53_defconfig: Enable capsule update

Enable raw & on disk capsule updates and provide configs required
for updating MTD devices. Also resync after savedefconfig.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
5 months agoinclude: configs: phycore-am62ax: Define capsule FW names
Wadim Egorov [Wed, 5 Mar 2025 04:58:27 +0000 (05:58 +0100)] 
include: configs: phycore-am62ax: Define capsule FW names

Define firmware names for phycore-am62ax capsules.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
5 months agoarm: dts: k3-am62a-phycore-som-binman: Provide capsule nodes
Wadim Egorov [Wed, 5 Mar 2025 04:58:26 +0000 (05:58 +0100)] 
arm: dts: k3-am62a-phycore-som-binman: Provide capsule nodes

Fill in phycore-am62ax capsule GUID properties of the base
binman capsule nodes.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
5 months agovepxress64: add guide for running FVP with TF-A
Harrison Mutai [Tue, 4 Mar 2025 16:52:02 +0000 (16:52 +0000)] 
vepxress64: add guide for running FVP with TF-A

Add documentation on how to run FVP with U-Boot and TF-A. This helps
users configure and run U-Boot correctly on Arm models.

Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 months agovepxress64: disable CRC32 by default to prevent aborts
Harrison Mutai [Tue, 4 Mar 2025 16:52:01 +0000 (16:52 +0000)] 
vepxress64: disable CRC32 by default to prevent aborts

On fast models, the CRC32 feature is disabled by default. When enabled
in U-Boot, it leads to synchronous aborts due to unrecognized
instructions. This change ensures CRC32 is disabled by default to
maintain compatibility.

Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
5 months agosandbox_vpl: Enable missing TPL_DM_I2C symbol
Tom Rini [Tue, 4 Mar 2025 20:32:35 +0000 (14:32 -0600)] 
sandbox_vpl: Enable missing TPL_DM_I2C symbol

Currently this platform implicity builds CONFIG_TPL_DM_I2C support
without setting the symbol. Add it for clarity.

Signed-off-by: Tom Rini <trini@konsulko.com>
5 months agoserial: Add missing TPL_SYS_NS16550_SERIAL symbol
Tom Rini [Tue, 4 Mar 2025 20:24:36 +0000 (14:24 -0600)] 
serial: Add missing TPL_SYS_NS16550_SERIAL symbol

On PowerPC platforms with TPL enabled and SPL_SYS_NS16550_SERIAL
enabled, today this builds under TPL as well due to how $(XPL_) is
defined. Add the TPL_SYS_NS16550_SERIAL itself for consistency and
clarity.

Signed-off-by: Tom Rini <trini@konsulko.com>
5 months agoboard: beagle: Add support for BeagleY-AI
Robert Nelson [Mon, 3 Mar 2025 19:15:15 +0000 (13:15 -0600)] 
board: beagle: Add support for BeagleY-AI

Basic board support for BeagleY-AI. Information on this
board can be found at https://beagleboard.org/beagley-ai

Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew Davis <afd@ti.com>
5 months agomach-snapdragon: always select SYSRESET_PSCI for ARCH_SNAPDRAGON
Caleb Connolly [Tue, 18 Mar 2025 11:55:14 +0000 (11:55 +0000)] 
mach-snapdragon: always select SYSRESET_PSCI for ARCH_SNAPDRAGON

Since removing reset_cpu() in mach-snapdragon, all Qualcomm platforms
now depend on CONFIG_SYSRESET and will fail to build without it.

Move the dependency from qcom_defconfig to kconfig so that we use
SYSRESET for all platforms.

Fixes: 61a1a1b8ca73 ("mach-snapdragon: use PSCI sysreset driver")
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agoMerge patch series "lmb: miscellaneous fixes and improvements"
Tom Rini [Tue, 18 Mar 2025 01:39:36 +0000 (19:39 -0600)] 
Merge patch series "lmb: miscellaneous fixes and improvements"

Sughosh Ganu <sughosh.ganu@linaro.org> says:

The patch series contains some fixes and improvements in the lmb
code, along with addition of corresponding test cases for the changes
made.

The lmb_reserve() function currently does not check if the requested
reservation would overlap with existing reserved regions. While some
scenarios are being handled, some corner cases still exist. These are
being handled by patch 1, along with adding test cases for these
scenarios.

Patch 2 is handling the case of reserving a new region of memory, but
that region overlaps with an existing region. The current code only
handles one particular scenario, but prints a message for the other
scenario of an encompassing overlap and returns back. The patch
handles the encompassing overlap.

Patch 3 is an improvement whereby we allow coalescing a newly reserved
region with an existing region. The current code exits this check
prematurely.

Patch 4 is removing a now superfluous check for overlapping regions
with flag other than LMB_NONE. This now gets handled at an earlier
point in lmb_reserve().

Patch 5 is clubbing the functionality to check if two regions are
adjacent, or overlap, allowing some code re-use.

Patch 6 is optimising the lmb_alloc() function by having it call
_lmb_alloc_base() directly.

Link: https://lore.kernel.org/r/20250303133231.405279-1-sughosh.ganu@linaro.org
5 months agolmb: optimise the lmb allocation functions
Sughosh Ganu [Mon, 3 Mar 2025 13:32:31 +0000 (19:02 +0530)] 
lmb: optimise the lmb allocation functions

The actual logic to allocate a region of memory is in the
_lmb_alloc_base() function. The lmb_alloc() API function calls
lmb_alloc_base(), which then calls _lmb_alloc_base() to do the
allocation. Instead, call the _lmb_alloc_base() directly from both the
allocation API's, and move the error message to the _lmb_alloc_base().

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
5 months agolmb: use a common function to check if regions overlap or are adjacent
Sughosh Ganu [Mon, 3 Mar 2025 13:32:30 +0000 (19:02 +0530)] 
lmb: use a common function to check if regions overlap or are adjacent

The functions to check if the two said regions are adjacent or overlap
are pretty similar in nature. Club the functionality into a single
function lmb_regions_check() and return the appropriate return value
to signify this aspect.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
5 months agolmb: remove superfluous address overlap check from lmb_add_region_flags()
Sughosh Ganu [Mon, 3 Mar 2025 13:32:29 +0000 (19:02 +0530)] 
lmb: remove superfluous address overlap check from lmb_add_region_flags()

U-Boot allows re-use of already reserved memory through the
lmb_reserve() and lmb_alloc_addr() API's. This memory re-use is
allowed only when the flag of the existing reserved region and that of
the requested region is LMB_NONE. A check was put in the
lmb_add_region_flags() in commit 8b8b35a4f5e to handle the scenario
where an already reserved region was re-requested with region flag
other than LMB_NONE -- the function then returns -EEXIST in such a
scenario.

The lmb_reserve() function now does a check for a reservation request
with existing reserved regions, and returns -EEXIST in case of an
overlap but when the flag check fails. Remove this now redundant check
from lmb_add_region_flags().

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
5 months agolmb: check for a region's coalescing with all existing regions
Sughosh Ganu [Mon, 3 Mar 2025 13:32:28 +0000 (19:02 +0530)] 
lmb: check for a region's coalescing with all existing regions

The lmb_add_region_flags() first checks if the new region to be added
can be coalesced with existing regions. The check stops if the two
regions are adjecent but their flags do not match. However, it is
possible that the newly added region might be adjacent with the next
existing region and with matching flags. Check for this possibility by
not breaking out of the loop.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
5 months agolmb: handle scenario of encompassing overlap
Sughosh Ganu [Mon, 3 Mar 2025 13:32:27 +0000 (19:02 +0530)] 
lmb: handle scenario of encompassing overlap

The lmb_fix_over_lap_regions() function is called if the added region
overlaps with an existing region. The function then fixes the overlap
and removes the redundant region. However, it makes certain
assumptions. One assumption is that the overlap would not encompass
the existing region. Another assumption is that the overlap only
occurs between two regions -- the scenario of the added region
overlapping multiple existing regions is not being handled. Handle
these cases by instead calling lmb_resize_regions(). Also remove the
now superfluous lmb_fix_over_lap_regions().

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
5 months agolmb: check if a region can be reserved by lmb_reserve()
Sughosh Ganu [Mon, 3 Mar 2025 13:32:26 +0000 (19:02 +0530)] 
lmb: check if a region can be reserved by lmb_reserve()

The logic used in lmb_alloc() takes into consideration the existing
reserved regions, and ensures that the allocated region does not
overlap with any existing allocated regions. The lmb_reserve()
function is not doing any such checks -- the requested region might
overlap with an existing region. This also shows up with
lmb_alloc_addr() as this function ends up calling lmb_reserve().

Add a function which checks if the region requested is overlapping
with an existing reserved region, and allow for the reservation to
happen only if both the regions have LMB_NONE flag, which allows
re-requesting of the region. In any other scenario of an overlap, have
lmb_reserve() return -EEXIST, implying that the requested region is
already reserved.

Add corresponding test cases which check for overlapping reservation
requests made through lmb_reserve() and lmb_alloc_addr(). And while
here, fix some of the comments in the test function being touched.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
5 months agoMerge branch 'next' of git://source.denx.de/u-boot-usb into next
Tom Rini [Mon, 17 Mar 2025 16:18:59 +0000 (10:18 -0600)] 
Merge branch 'next' of git://source.denx.de/u-boot-usb into next

- Add USB support on Starfive JH7110

5 months agoMerge branch 'nand-next' of https://source.denx.de/u-boot/custodians/u-boot-nand...
Tom Rini [Mon, 17 Mar 2025 16:18:18 +0000 (10:18 -0600)] 
Merge branch 'nand-next' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash into next

CI: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/25178

This merge request add support for cadence raw nand driver for agilex
board and add a fix to meson driver.

5 months agoclk/stub: add sc7280-rpmh clock
Caleb Connolly [Mon, 17 Mar 2025 15:54:36 +0000 (15:54 +0000)] 
clk/stub: add sc7280-rpmh clock

Stub the RPMh clock controller on SC7280

Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agopinctrl/qcom: fix kconfig option names
Caleb Connolly [Mon, 17 Mar 2025 13:25:14 +0000 (13:25 +0000)] 
pinctrl/qcom: fix kconfig option names

A copy-paste error is starting to get out of hand... Fix all these so
they don't look like clock drivers in menuconfig.

Link: https://lore.kernel.org/r/20250317132519.46080-1-caleb.connolly@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agoclk/qcom: sc7280: add GENI, PCIe, and more USB clocks
Caleb Connolly [Fri, 14 Mar 2025 15:31:21 +0000 (15:31 +0000)] 
clk/qcom: sc7280: add GENI, PCIe, and more USB clocks

Add support for a bunch of new clocks, including PCIe, GENI (for all
peripherals used on the RB3 Gen 2), and some missing USB clocks.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250314-sc7280-more-clocks-v1-3-ead54487c38e@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agoclk/qcom: sc7280: add some debug data
Caleb Connolly [Fri, 14 Mar 2025 15:31:20 +0000 (15:31 +0000)] 
clk/qcom: sc7280: add some debug data

Dump a few PCIe and USB clocks

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250314-sc7280-more-clocks-v1-2-ead54487c38e@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agoclk/qcom: bubble up qcom_gate_clk_en() errors
Caleb Connolly [Fri, 14 Mar 2025 15:31:19 +0000 (15:31 +0000)] 
clk/qcom: bubble up qcom_gate_clk_en() errors

If we try to enable a gate clock that doesn't exist, we used to just
fail silently. This may make sense for early bringup of some core
peripherals that we know are already enabled, but it only makes
debugging missing clocks more difficult.

Bubble up errors now that qcom_gate_clk_en() can return an error code to
catch any still-missing clocks and make it easier to find missing ones
as more complicated peripherals are enabled.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250314-sc7280-more-clocks-v1-1-ead54487c38e@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agocmd: version: Get information about GCC and LD back
Michal Simek [Thu, 6 Mar 2025 10:12:30 +0000 (11:12 +0100)] 
cmd: version: Get information about GCC and LD back

U-Boot version command is no longer showing information about GCC and LD.
The reason is that version.h has been removed that's why CC_VERSION_STRING
and LD_VERSION_STRING are not pass.
Values are generated to generated/version_autogenerated.h which is sourced
in version.h.

Fixes: 54ecce2cbf90 ("version: Separate our version string from the version command")
Signed-off-by: Michal Simek <michal.simek@amd.com>
5 months agoMerge tag 'efi-2025-04-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi
Tom Rini [Mon, 17 Mar 2025 14:00:40 +0000 (08:00 -0600)] 
Merge tag 'efi-2025-04-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request efi-2025-04-rc5

CI:

* https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/25196

UEFI:

* Export _start symbol from crt0_*_efi stubs
* Move .dynamic out of .text in EFI
* scripts/Makefile.lib: Preserve the .dynstr section as well

Documentation:

* net: miiphybb: Convert documentation to rst

5 months agoMerge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh
Tom Rini [Mon, 17 Mar 2025 13:59:39 +0000 (07:59 -0600)] 
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sh

These are mainly DBSC5 DRAM controller specific fixes and updates for
current release. There is the long overdue BL31 start V4H board code as
well, that should be in the current release to make the V4H White Hawk
board usable with SPL, and a fallback U-Boot PSCI implementation
enablement to make sure the board always boots. And finally, there are
two comment fixes.

5 months agoqcom_defconfig: enable SYSRESET_QCOM_PSHOLD
Sam Day [Sat, 25 Jan 2025 19:59:27 +0000 (19:59 +0000)] 
qcom_defconfig: enable SYSRESET_QCOM_PSHOLD

MSM8916 devices use this instead of PSCI.

Signed-off-by: Sam Day <me@samcday.com>
Link: https://lore.kernel.org/r/20250125-msm8916-sysreset-v1-3-62073932ff0e@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agosysreset: qcom-pshold: remove ARCH_IPQ40XX dependency
Sam Day [Sat, 25 Jan 2025 19:59:20 +0000 (19:59 +0000)] 
sysreset: qcom-pshold: remove ARCH_IPQ40XX dependency

Depending on ARCH_IPQ40XX is too restrictive, as this architecture is
explicitly armv7. This driver is also used on msm8916 devices, which
have cortex-a53 armv8 cores.

Signed-off-by: Sam Day <me@samcday.com>
Link: https://lore.kernel.org/r/20250125-msm8916-sysreset-v1-2-62073932ff0e@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agomach-snapdragon: use PSCI sysreset driver
Sam Day [Sat, 25 Jan 2025 19:59:15 +0000 (19:59 +0000)] 
mach-snapdragon: use PSCI sysreset driver

Drop the `board_reset` function from mach-snapdragon board code, and
instead use the standard PSCI sysreset driver.

Signed-off-by: Sam Day <me@samcday.com>
Link: https://lore.kernel.org/r/20250125-msm8916-sysreset-v1-1-62073932ff0e@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agoqcom_defconfig: enable PINCTRL_QCOM_SC7280
Caleb Connolly [Wed, 22 Jan 2025 15:02:52 +0000 (16:02 +0100)] 
qcom_defconfig: enable PINCTRL_QCOM_SC7280

Acked-by: Christopher Obbard <christopher.obbard@linaro.org>
Link: https://lore.kernel.org/r/20250122-pinctrl-sc7280-v1-2-8bdba72e6366@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agopinctrl: qcom: add sc7280 pinctrl driver
Caleb Connolly [Wed, 22 Jan 2025 15:02:51 +0000 (16:02 +0100)] 
pinctrl: qcom: add sc7280 pinctrl driver

Introduce a pinctrl driver for SC7280/QCM6490, this is used by the RB3
Gen 2, FairPhone 5 and other devices.

Tested-by: Christopher Obbard <christopher.obbard@linaro.org>
Link: https://lore.kernel.org/r/20250122-pinctrl-sc7280-v1-1-8bdba72e6366@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agomach-snapdragon: handle platforms without PSCI support
Sam Day [Mon, 27 Jan 2025 14:48:55 +0000 (14:48 +0000)] 
mach-snapdragon: handle platforms without PSCI support

Most MSM8916 devices shipped without PSCI support. The history is quite
nuanced (a good overview can be found in [1]), but the end result is
that the upstream DTs for this SoC pretend that PSCI exists, and it's
expected that the bootloader handles the case where it doesn't. This is
codified by the de-facto bootloader for MSM8916 devices, lk2nd [2].

So we handle it here by deleting the /psci node if we detect the absence
of PSCI. We need to do this early to ensure sysreset works correctly,
since the PSCI firmware driver is PRE_RELOC and binds the PSCI sysreset
driver.

Additionally, show_psci_version is updated to check that PSCI exists.
Currently this banner outputs "PSCI: 65535.65535" on devices without
PSCI support, which isn't very useful :)

[1]: https://github.com/msm8916-mainline/linux/issues/388
[2]: https://github.com/msm8916-mainline/lk2nd/blob/8183ea2/lk2nd/smp/spin-table/spin-table.c#L237

Signed-off-by: Sam Day <me@samcday.com>
Link: https://lore.kernel.org/r/20250127-qcom-handle-absent-psci-v1-1-e762f2db938c@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agomach-snapdragon: support parsing memory info from external FDT
Sam Day [Thu, 23 Jan 2025 12:12:14 +0000 (12:12 +0000)] 
mach-snapdragon: support parsing memory info from external FDT

qcom_parse_memory is updated to return a -ENODATA error if the passed
FDT does not contain a /memory node, or that node is incomplete (size=0)

board_fdt_blob_setup first tries to call qcom_parse_memory with the
internal FDT (if present+valid). If that fails, it tries again with the
external FDT (again, if present+valid).

When booting with an internal FDT from upstream, it's likely that this
change results in a slight performance hit, since virtually all upstream
qcom DTs lack a fully specified memory node. The impact should be
negligible, though.

qcom_parse_memory was given a detailed docstring adapted from Caleb's
original commit message that introduced the function.

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Sam Day <me@samcday.com>
Link: https://lore.kernel.org/r/20250123-qcom-parse-memory-updates-v3-1-c5332b81ea9f@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agorng: msm: keep core clock disabled when PRNG not in use
Sam Day [Wed, 12 Feb 2025 07:01:55 +0000 (07:01 +0000)] 
rng: msm: keep core clock disabled when PRNG not in use

This is how the kernel does it. APQ8016E TRM also states that this clock
can be turned off when no random numbers are needed.

Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250212-msm-rng-fixes-v2-5-645cf8d3fd3c@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agoclk/qcom: apq8016: improve clk_enable logging
Sam Day [Wed, 12 Feb 2025 07:01:47 +0000 (07:01 +0000)] 
clk/qcom: apq8016: improve clk_enable logging

Properly warn when an unknown clock is enabled.

Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250212-msm-rng-fixes-v2-4-645cf8d3fd3c@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agorng: msm: don't enable PRNG if it's already enabled
Sam Day [Wed, 12 Feb 2025 07:01:39 +0000 (07:01 +0000)] 
rng: msm: don't enable PRNG if it's already enabled

msm_rng_enable is supposed to skip writing to LFSR_CFG + CONFIG
registers in the PRNG_ block if PRNG_CONFIG_HW_ENABLE is already set.
The logic to test for this was inverted.

Without this fix, the driver was causing SError aborts on my MSM8916
device. Stephan Gerhold suggested this was probably because TZ has
marked this as a protected register, since it would also be using it for
RNG.

Fixes: 033ec636fcb ("rng: Add Qualcomm MSM PRNG driver")
Suggested-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250212-msm-rng-fixes-v2-3-645cf8d3fd3c@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agoclk/qcom: apq8016: add PRNG_AHB_CLK
Sam Day [Wed, 12 Feb 2025 07:01:33 +0000 (07:01 +0000)] 
clk/qcom: apq8016: add PRNG_AHB_CLK

This clock needs to be enabled for the msm-rng driver to work on
MSM8916, otherwise accessing the PRNG register block causes a data
abort.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250212-msm-rng-fixes-v2-2-645cf8d3fd3c@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agoclk/qcom: apq8016: use BIT macro for clk en_vals
Sam Day [Wed, 12 Feb 2025 07:01:27 +0000 (07:01 +0000)] 
clk/qcom: apq8016: use BIT macro for clk en_vals

This reads a little bit nicer (IMO), and is consistent with the kernel.

Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250212-msm-rng-fixes-v2-1-645cf8d3fd3c@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agoconfigs: add qcom_ipq9574_mmc_defconfig
Varadarajan Narayanan [Wed, 26 Feb 2025 06:45:05 +0000 (12:15 +0530)] 
configs: add qcom_ipq9574_mmc_defconfig

Introduce a defconfig for the Qualcomm IPQ9574 SoC based RDPs.
Presently supports eMMC.

Per the flash memory layout, U-Boot size cannot exceed 756KB. With this
defconfig, u-boot.mbn size is ~480KB.

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250226064505.1178054-8-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agommc: msm_sdhci: Reset clocks before reconfiguration
Varadarajan Narayanan [Wed, 26 Feb 2025 06:45:04 +0000 (12:15 +0530)] 
mmc: msm_sdhci: Reset clocks before reconfiguration

U-Boot has to reconfigure the clocks that were set in the boot
loaders. However, in IPQ9574, the clocks have to be reset before
they can be reconfigured. Hence add code to do the relevant
resets.

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250226064505.1178054-7-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agopinctrl: qcom: Add ipq9574 pinctrl driver
Varadarajan Narayanan [Wed, 26 Feb 2025 06:45:03 +0000 (12:15 +0530)] 
pinctrl: qcom: Add ipq9574 pinctrl driver

Add pinctrl driver for the TLMM block found in the ipq9574 SoC.

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250226064505.1178054-6-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agopinctrl: qcom: Handle get_function_mux failure
Varadarajan Narayanan [Wed, 26 Feb 2025 06:45:02 +0000 (12:15 +0530)] 
pinctrl: qcom: Handle get_function_mux failure

Presently, get_function_mux returns an unsigned int and cannot
differentiate between failure and correct function value. Change its
return type to int and check for failure in the caller.

Additionally, updated drivers/pinctrl/qcom/pinctrl-*.c to accommodate the
above return type change. Only compile test done.

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250226064505.1178054-5-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agoclk/qcom: add initial clock driver for ipq9574
Varadarajan Narayanan [Wed, 26 Feb 2025 06:45:01 +0000 (12:15 +0530)] 
clk/qcom: add initial clock driver for ipq9574

Add initial set of clocks and resets for enabling U-Boot on ipq9574
based RDP platforms.

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250226064505.1178054-4-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agodts: ipq9574-rdp433-u-boot: add override dtsi
Varadarajan Narayanan [Wed, 26 Feb 2025 06:45:00 +0000 (12:15 +0530)] 
dts: ipq9574-rdp433-u-boot: add override dtsi

Add initial support for the IPQ9574 MMC based RDP platforms.
Define memory layout statically.

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250226064505.1178054-3-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agodoc: board/qualcomm: document RDP building/flashing
Varadarajan Narayanan [Wed, 26 Feb 2025 06:44:59 +0000 (12:14 +0530)] 
doc: board/qualcomm: document RDP building/flashing

Introducing basic support for Qualcomm IPQxxx based RDPs.
Document the build and flashing steps.

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250226064505.1178054-2-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
5 months agoscripts/Makefile.lib: efi: Preserve the .dynstr section as well
Sam Edwards [Sat, 15 Mar 2025 22:18:11 +0000 (15:18 -0700)] 
scripts/Makefile.lib: efi: Preserve the .dynstr section as well

This section is required by .dynamic and llvm-objcopy will exit with a
fatal error if it is not also preserved in the output.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
5 months agoefi_loader: Move .dynamic out of .text in EFI
Sam Edwards [Sat, 15 Mar 2025 22:18:10 +0000 (15:18 -0700)] 
efi_loader: Move .dynamic out of .text in EFI

EFI applications need to be relocatable. Ordinarily, this is achieved
through a PE-format .reloc section, but since that requires toolchain
tricks to achieve, U-Boot's EFI applications instead embed ELF-flavored
relocation information and use it for self-relocation; thus, the
.dynamic section needs to be preserved.

Before this patch, it was tacked on to the end of .text, but this was
not proper: A .text section is SHT_PROGBITS, while the .dynamic section
is SHT_DYNAMIC. Attempting to combine them like this creates a section
type mismatch. While GNU ld doesn't seem to complain, LLVM's lld
considers this a fatal linking error.

This patch moves .dynamic out to its own section, so that the output ELF
has the correct types. (They're all mashed together when converting to
binary anyway, so this patch causes no change in the final .efi output.)

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
5 months agoarm: riscv: efi: Export _start symbol from crt0_*_efi stubs
Sam Edwards [Sat, 15 Mar 2025 22:18:09 +0000 (15:18 -0700)] 
arm: riscv: efi: Export _start symbol from crt0_*_efi stubs

While the _start label is only intended for use locally to populate the
(hand-written) PE header, the linker script includes ENTRY(_start) which
designates it as the entry point in the output ELF, resulting in linker
warnings under some linkers (e.g. LLVM's lld) due to _start not being a
globally-visible symbol. Since  ELF is only an intermediary build
format, and the aforementioned PE header correctly points to _start, the
ENTRY(_start) directive could easily be removed to silence this warning.

However, since some developers who are debugging EFI by analyzing the
intermediary ELF may appreciate having correct entry-point information,
this patch instead promotes the _start labels to global symbols,
silencing the linker warning and making the intermediary ELF reflect the
true entry point.

This patch doesn't affect the final output binaries in any way.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
5 months agonet: miiphybb: Convert documentation to rst
Marek Vasut [Sat, 8 Mar 2025 20:49:42 +0000 (21:49 +0100)] 
net: miiphybb: Convert documentation to rst

Convert the current miiphybb documentation to rst. Rename
the README.bitbangMII to bitbangmii.rst in the process.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
5 months agoconfigs: starfive: Add visionfive2 cadence USB configuration
Minda Chen [Thu, 6 Mar 2025 06:20:31 +0000 (14:20 +0800)] 
configs: starfive: Add visionfive2 cadence USB configuration

Add cadence USB confiuration.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Tested-by: E Shattow <lucent@gmail.com>
5 months agospl: starfive: visionfive2: Disable USB overcurrent pin by default.
Minda Chen [Thu, 6 Mar 2025 06:20:30 +0000 (14:20 +0800)] 
spl: starfive: visionfive2: Disable USB overcurrent pin by default.

For some JH7110 boards, USB host overcurent pin is not reserved,
To make USB host work, overcurrent pin must be disabled. So set the
pin default disabled in spl stage.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Tested-by: E Shattow <lucent@gmail.com>
5 months agousb: cdns: starfive: Add cdns USB driver
Minda Chen [Thu, 6 Mar 2025 06:20:29 +0000 (14:20 +0800)] 
usb: cdns: starfive: Add cdns USB driver

Add Starfive cdns USB3 wrapper driver.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: E Shattow <lucent@gmail.com>
5 months agousb: cdns: starfive: Get dr mode from wrapper device dts node
Minda Chen [Thu, 6 Mar 2025 06:20:28 +0000 (14:20 +0800)] 
usb: cdns: starfive: Get dr mode from wrapper device dts node

Cdns core driver also get dr mode from wrapper devcie dts node
to make it is same with Starfive cdns USB Linux kernel driver,
Starfive 7110 OF_UPSTREAM is enabled

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Marek Vasut <marex@denx.de>
5 months agophy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver
Minda Chen [Thu, 6 Mar 2025 06:20:27 +0000 (14:20 +0800)] 
phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver

Add Starfive JH7110 PCIe 2.0 PHY driver, which is generic
PHY driver and can be used as USB 3.0 driver.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Tested-by: E Shattow <lucent@gmail.com>
5 months agophy: starfive: Add Starfive JH7110 USB 2.0 PHY driver
Minda Chen [Thu, 6 Mar 2025 06:20:26 +0000 (14:20 +0800)] 
phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver

Add Starfive JH7110 USB 2.0 PHY driver, which is generic
PHY driver.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Tested-by: E Shattow <lucent@gmail.com>
5 months agousb: cdns3: Set USB PHY mode in cdns3_drd_update_mode()
Minda Chen [Thu, 6 Mar 2025 06:20:25 +0000 (14:20 +0800)] 
usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode()

USB PHY maybe need to set PHY mode in different USB
dr mode. So translate USB PHY mode to generic PHY mode
and call generic_phy_set_mode().

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Marek Vasut <marex@denx.de>
5 months agoram: renesas: dbsc5: Make struct renesas_dbsc5_board_config public
Marek Vasut [Sun, 16 Mar 2025 13:51:44 +0000 (14:51 +0100)] 
ram: renesas: dbsc5: Make struct renesas_dbsc5_board_config public

Make struct renesas_dbsc5_board_config {} definition public via
include/dbsc5.h, so this structure can be defined in board files
and passed into the DBSC5 DRAM driver by overriding weak function
dbsc5_get_board_data() on board level.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
5 months agoram: renesas: dbsc5: Add V4H-3/V4H-5/V4H-7 OTP based detection
Marek Vasut [Sun, 16 Mar 2025 13:51:43 +0000 (14:51 +0100)] 
ram: renesas: dbsc5: Add V4H-3/V4H-5/V4H-7 OTP based detection

Add auto-detection and handling of Renesas R-Car V4H-3 and V4H-5
in addition to V4H-7 SoC variants based on OTP fuse programming.
The V4H-3 and V4H-5 variants have reduced DRAM frequency options.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
5 months agoram: renesas: dbsc5: Synchronize initialization code to rev.1.10
Marek Vasut [Sun, 16 Mar 2025 13:51:42 +0000 (14:51 +0100)] 
ram: renesas: dbsc5: Synchronize initialization code to rev.1.10

Update the DRAM initialization code to match DBSC5 initialization code
rev.1.10 , which is currently the latest version available. This makes
DRAM initialization operational on Renesas R-Car V4H R8A779G0 rev.3.0.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
5 months agoram: renesas: dbsc5: Fix DBTR11 calculation
Marek Vasut [Sun, 16 Mar 2025 13:51:41 +0000 (14:51 +0100)] 
ram: renesas: dbsc5: Fix DBTR11 calculation

Reinstate missing increment by two in DBTR11 calculation based
on the original DBSC5 initialization code rev.0.80. The original
code did ... ODTLon - (js2[JS2_tODTon_min] - 1) + 1 , which was
incorrectly converted into ODTLon - js2[JS2_tODTon_min], but
should have been converted to ODTLon - js2[JS2_tODTon_min] + 2.
Add the missing +2 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
5 months agoram: renesas: dbsc5: Fix JS1 index calculation
Marek Vasut [Sun, 16 Mar 2025 13:51:40 +0000 (14:51 +0100)] 
ram: renesas: dbsc5: Fix JS1 index calculation

The JS1 index is calculated correctly, but the limiter cannot
be the max() function because the index should be lower than
JS1_USABLEC_SPEC_HI and the max() function would unconditionally
override the JS1 index to JS1_USABLEC_SPEC_HI. Use clamp() to
limit the JS1 index instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
5 months agoram: renesas: dbsc5: Fix bitrate MD pin parsing
Marek Vasut [Sun, 16 Mar 2025 13:51:39 +0000 (14:51 +0100)] 
ram: renesas: dbsc5: Fix bitrate MD pin parsing

Fix copy paste error in MD pin handling for 5500 Mbps and 4800 Mbps case,
each should be handled by MD[19,17] == 2 and MD[19,17] == 3 respectively.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
5 months agoarm64: dts: renesas: Make OTP available in SPL on R8A779G0 V4H
Marek Vasut [Sun, 16 Mar 2025 13:51:38 +0000 (14:51 +0100)] 
arm64: dts: renesas: Make OTP available in SPL on R8A779G0 V4H

The DBSC5 DRAM controller driver needs access to OTP fuses to discern
Renesas R-Car V4H-3, V4H-5 and V4H-7 SoC variants based on OTP fuse
programming. Make OTP block DT node available in U-Boot SPL DT so the
DBSC5 driver can determine its base address and read out the OTP fuses.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
5 months agoarm64: renesas: Drop stale R-Car V4H SPL implementation description
Marek Vasut [Sun, 16 Mar 2025 13:51:09 +0000 (14:51 +0100)] 
arm64: renesas: Drop stale R-Car V4H SPL implementation description

The R-Car V4H SPL implementation was originally running on the Cortex-R52
core, but this is no longer the case. Majority of the SPL now runs on the
Cortex-A76 core. Drop the stale description.

Fixes: ec53fdee5bec ("arm64: renesas: Add Renesas R-Car V4H SPL implementation")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
5 months agoARM: renesas: Drop stale common Makefile description
Marek Vasut [Sun, 16 Mar 2025 13:50:41 +0000 (14:50 +0100)] 
ARM: renesas: Drop stale common Makefile description

Remove stale Makefile description, this used to be valid for the
original Makefile from which the common Makefile was made generic,
but is no longer applicable to the common Makefile.

Fixes: c7d2d7f90a91 ("ARM: renesas: Simplify board Makefiles")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
5 months agoarm64: renesas: Enable fallback PSCI on Renesas R-Car R8A779G0 V4H White Hawk
Marek Vasut [Sun, 2 Mar 2025 22:30:02 +0000 (23:30 +0100)] 
arm64: renesas: Enable fallback PSCI on Renesas R-Car R8A779G0 V4H White Hawk

Enable fallback PSCI provider on Renesas R-Car R8A779G0 V4H White Hawk board.

This fallback PSCI provider provides basic PSCI interface which can be used
by the Linux kernel, but does not provide support for bringing up additional
CPU cores or any other functionality, except for SoC level reset.

This fallback PSCI provider is intended as a fallback in case a proper PSCI
provider is not started before the Linux kernel is started. Linux kernel on
ARMv8a will fail to boot in case a PSCI provider is not available, and this
basic fallback PSCI provider assures such a boot failure cannot occur, even
if that means the system will boot in degraded mode with only one CPU core
available, that is still sufficient to perform recovery.

In the common case, a proper PSCI provider should be started as part of
the Linux kernel fitImage, as the BL31 loadable, and replace this basic
fallback PSCI provider before the Linux kernel is started.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
5 months agoarm64: renesas: Add TFA BL31 handoff support on Renesas R-Car Gen4
Marek Vasut [Sun, 2 Mar 2025 20:59:11 +0000 (21:59 +0100)] 
arm64: renesas: Add TFA BL31 handoff support on Renesas R-Car Gen4

Implement custom U_BOOT_FIT_LOADABLE_HANDLER and armv8_switch_to_el2_prep()
handling in case the TFA was loaded. The loadables handler sets up custom
handoff structure used by Renesas TFA fork in fixed location in DRAM and
indicates the TFA has been loaded.

The custom armv8_switch_to_el2_prep() handling tests whether the TFA BL31
was previously loaded and the custom handoff structure was set up, and if
so, jumps to TFA BL31 which switches from EL3 to EL2 and then returns to
U-Boot just past bl in armv8_switch_to_el2() to finish starting the Linux
kernel.

The jump to Linux through TFA works in such a way that the custom
armv8_switch_to_el2_prep() handler configures the custom handoff structure
such that the target jump address of the TFA BL31 on exit is set to the
armv8_switch_to_el2() + 4, which is just past the bl, and just before the
U-Boot code which implements the Linux kernel boot from either EL. The
registers passed through the TFA BL31 are all the registers passed into
armv8_switch_to_el2_prep() to assure maximum compatibility with all the
boot modes. The armv8_switch_to_el2_prep() handler jumps to the TFA BL31,
which does its setup, drops EL from EL3 to EL2 and finally jumps to the
armv8_switch_to_el2() + 4 entry point, which then allows U-Boot to boot
the Linux kernel the usual way.

In order to build suitable kernel fitImage, build TFA first, upstream
is currently under review:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/35799
Or if necessary, downstream repository:
remote: https://github.com/renesas-rcar/arm-trusted-firmware.git
branch: rcar_gen4_v2.7_v4x

```
$ git clean -fqdx
$ MBEDTLS_DIR=/path/to/mbedtls/ make -j$(nproc) bl31 \
PLAT=rcar_gen4 ARCH=aarch64 LSI=V4H SPD=none \
CTX_INCLUDE_AARCH32_REGS=0 MBEDTLS_COMMON_MK=1 \
PTP_NONSECURE_ACCESS=1 LOG_LEVEL=20 DEBUG=0 \
ENABLE_ASSERTIONS=0 E=0
```

Build Linux kernel Image and device tree from current mainline Linux
kernel repository, obtain 'Image' and 'r8a779g0-white-hawk.dtb' .

Bundle the files together using provided fit-image.its fitImage description:
```
$ mkimage -f fit-image.its fitImage
```

To start the kernel fiImage generated in previous step, load fitImage
to DRAM and use the 'bootm' command to start it:
=> load 0x58000000 ... fitImage && bootm 0x58000000

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
5 months agomtd: rawnand: meson: always use OOB bytes during write
Arseniy Krasnov [Sun, 22 Dec 2024 21:23:29 +0000 (00:23 +0300)] 
mtd: rawnand: meson: always use OOB bytes during write

If 'oob_required' is not set by the caller (for example 'oobbuf' is NULL),
then driver doesn't copy OOB data from 'oob_poi' to special controller
structures, so zeroes will be written as OOB. But, generic raw NAND logic
in 'nand_base.c' already handles case when OOB is not required to write by
filling 'oob_poi' with 0xFF's. So let's remove 'oob_required' check to
always read 'oob_poi' data for OOB.

Kernel driver (drivers/mtd/nand/raw/meson_nand.c) works in the same way,
so need to keep same behaviour here.

Fixes: c2e8c4d09a7a ("mtd: rawnand: Meson NAND controller support")
Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
5 months agoMerge tag 'dm-pull-15mar25' of git://git.denx.de/u-boot-dm into next
Tom Rini [Sat, 15 Mar 2025 14:19:31 +0000 (08:19 -0600)] 
Merge tag 'dm-pull-15mar25' of git://git.denx.de/u-boot-dm into next

Sync up on test renames

5 months agotest: Make net tests depend on CONFIG_CMD_NET
Simon Glass [Sun, 9 Feb 2025 16:07:19 +0000 (09:07 -0700)] 
test: Make net tests depend on CONFIG_CMD_NET

This fails on samus_tpl as there is no 'net' command.

   => net list
   Unknown command 'net' - try 'help' !

Fix it by adding a condition for the test.

Add a blank line to keep pylint happy.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 months agotest/py: Show info about module-loading
Simon Glass [Sun, 9 Feb 2025 16:07:18 +0000 (09:07 -0700)] 
test/py: Show info about module-loading

It is sometimes tricky to figure out what modules test.py is loading
when it starts up. The result can be a silent failure with no clue as to
what when wrong.

Add a section which lists the modules loaded as well as those not
found.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 months agotest/py: Drop assigning ubman to cons
Simon Glass [Sun, 9 Feb 2025 16:07:17 +0000 (09:07 -0700)] 
test/py: Drop assigning ubman to cons

Now that we have a shorter name, we don't need this sort of thing. Just
use ubman instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
5 months agotest/py: Drop importing utils as util
Simon Glass [Sun, 9 Feb 2025 16:07:16 +0000 (09:07 -0700)] 
test/py: Drop importing utils as util

Now that we have a shorter name, we don't need this sort of thing.
Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # test_android
5 months agotest/py: Drop u_boot_ prefix on test files
Simon Glass [Sun, 9 Feb 2025 16:07:15 +0000 (09:07 -0700)] 
test/py: Drop u_boot_ prefix on test files

We know this is U-Boot so the prefix serves no purpose other than to
make things longer and harder to read. Drop it and rename the files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> # test_android / test_dfu
5 months agotest/py: Shorten u_boot_console
Simon Glass [Sun, 9 Feb 2025 16:07:14 +0000 (09:07 -0700)] 
test/py: Shorten u_boot_console

This fixture name is quite long and results in lots of verbose code.
We know this is U-Boot so the 'u_boot_' part is not necessary.

But it is also a bit of a misnomer, since it provides access to all the
information available to tests. It is not just the console.

It would be too confusing to use con as it would be confused with
config and it is probably too short.

So shorten it to 'ubman'.

Signed-off-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/u-boot/CAFLszTgPa4aT_J9h9pqeTtLCVn4x2JvLWRcWRD8NaN3uoSAtyA@mail.gmail.com/
5 months agoconfigs: nand2_defconfig: Enable configs for nand boot
Dinesh Maniyam [Wed, 26 Feb 2025 16:18:27 +0000 (00:18 +0800)] 
configs: nand2_defconfig: Enable configs for nand boot

Enable configs for nand boot.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
5 months agodrivers: mtd: nand: Kconfig: Add SYS_NAND_PAGE_SIZE dependency
Dinesh Maniyam [Wed, 26 Feb 2025 16:18:32 +0000 (00:18 +0800)] 
drivers: mtd: nand: Kconfig: Add SYS_NAND_PAGE_SIZE dependency

Add SYS_NAND_PAGE_SIZE dependency for cadence NAND.
This config is needed as the SPL driver will use this parameter
to read uboot-proper image in NAND during booting.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
5 months agodrivers: mtd: nand: Enabled Kconfig and Makefile for Cadence-SPL
Dinesh Maniyam [Wed, 26 Feb 2025 16:18:30 +0000 (00:18 +0800)] 
drivers: mtd: nand: Enabled Kconfig and Makefile for Cadence-SPL

Enable the Kconfig and Makefile for the Cadence-Nand
SPL support in agilex5 family device.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
5 months agodrivers: mtd: nand: spl: Add support for nand SPL load image
Dinesh Maniyam [Wed, 26 Feb 2025 16:18:29 +0000 (00:18 +0800)] 
drivers: mtd: nand: spl: Add support for nand SPL load image

Add support for spl nand to load binary image from NAND
to RAM. Leverage the existing nand_spl_load_image from nand_spl_loaders.c

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
5 months agodrivers: mtd: nand: base: Add support for Hardware ECC for check bad block
Dinesh Maniyam [Wed, 26 Feb 2025 16:18:28 +0000 (00:18 +0800)] 
drivers: mtd: nand: base: Add support for Hardware ECC for check bad block

Leverage linux code to support hardware ECC interface
to verify nand bad block.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
5 months agodrivers: nand: Enabled Kconfig and Makefile for cdns-nand
Dinesh Maniyam [Wed, 26 Feb 2025 16:18:26 +0000 (00:18 +0800)] 
drivers: nand: Enabled Kconfig and Makefile for cdns-nand

Enable the Kconfig and Makefile for the
Cadence NAND driver for the agilex5 family device.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>