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ARM: dts: socfpga: fix register entry for timer3 on Arria10
authorDinh Nguyen <dinguyen@kernel.org>
Fri, 31 Jul 2020 15:26:40 +0000 (10:26 -0500)
committerDinh Nguyen <dinguyen@kernel.org>
Mon, 17 Aug 2020 14:07:04 +0000 (09:07 -0500)
commit0ff5a4812be4ebd4782bbb555d369636eea164f7
treed44c742722e0e0a9a59958df831c4f6a90c34e2etree | snapshot
parent9123e3a74ec7b934a4a099e98af6a61c2f80bbf5commit | diff
ARM: dts: socfpga: fix register entry for timer3 on Arria10

Fixes the register address for the timer3 entry on Arria10.

Fixes: 475dc86d08de4 ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
arch/arm/boot/dts/socfpga_arria10.dtsi diff | blob | blame | history
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