RISC-V: Support RVV VFNMSAC rounding mode intrinsic API

RISC-V: Support RVV VFNMSAC rounding mode intrinsic API

This patch would like to support the rounding mode API for the
VFNMSAC for the below samples.

* __riscv_vfnmsac_vv_f32m1_rm
* __riscv_vfnmsac_vv_f32m1_rm_m
* __riscv_vfnmsac_vf_f32m1_rm
* __riscv_vfnmsac_vf_f32m1_rm_m

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-bases.cc
	(class vfnmsac_frm): New class for vfnmsac frm.
	(vfnmsac_frm_obj): New declaration.
	(BASE): Ditto.
	* config/riscv/riscv-vector-builtins-bases.h: Ditto.
	* config/riscv/riscv-vector-builtins-functions.def
	(vfnmsac_frm): New function definition.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-single-negate-multiply-sub.c:
	New test.