RISC-V: PR33216, Allow c.slli, c.srai, c.srli with 0 immediate as a hint

RISC-V: PR33216, Allow c.slli, c.srai, c.srli with 0 immediate as a hint

The original patch,
e6f372ba661bb0d8eec1e22a6dc1ad9937336e4d

Since recently c.slli64, c.srai64, and c.srli64 have been removed from the
riscv-isa-manual, c.slli, c.srli, and c.srai with 0 immediate are now listed
as hints,
https://github.com/riscv/riscv-isa-manual/pull/1942 and https://github.com/riscv/riscv-isa-manual/pull/2093

So allow c.slli, c.srli, and c.srai with 0 immediate as a hint.  Also allow to
assemble slli, srli and srai with 0 immediate to hint c.slli, c.srli and c.srai
when rvc is enabled.  The c.slli64, c.srai64, and c.srli64 should be kept as
aliases, so dis-assembler should disassemble to c.slli, c.srli, and c.srai with
0 immediate.

Passed rv32/64-elf/linux binutils testcases.

gas/
	PR 33216
	* testsuite/gas/riscv/c-zero-imm.d: Updated since allow c.slli64,
	c.srai64, and c.srli64 with 0 immediate as a hint.
	* testsuite/gas/riscv/c-zero-imm.s: Likewise.
	* testsuite/gas/riscv/zca.d: Likewise.
opcodes/
	PR 33216
	* riscv-opc.c (riscv_opcodes): Updated since allow c.slli64, c.srai64,
	and c.srli64 with 0 immediate as a hint.