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sim: riscv: Add support for compressed integer instructions
authorJaydeep Patil <jaydeep.patil@imgtec.com>
Thu, 1 Feb 2024 04:42:27 +0000 (04:42 +0000)
committerAndrew Burgess <aburgess@redhat.com>
Tue, 13 Feb 2024 11:04:04 +0000 (11:04 +0000)
commit3224e32fb84f034d190ad91d7b9ac86f6800d47a
tree239a301674c7c5040bda776596521d61b83b33adtree
parent4dad3c1e1c9e789addc0d196cef8e8ea22ddbedacommit | diff
sim: riscv: Add support for compressed integer instructions

Added support for simulation of compressed integer instruction set ("c").
Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions.
The compressed instructions are available for models implementing C extension.
Such as RV32IC, RV64IC, RV32GC, RV64GC etc.

Approved-By: Andrew Burgess <aburgess@redhat.com>
sim/riscv/model_list.def diff | blob | blame | history
sim/riscv/sim-main.c diff | blob | blame | history
sim/testsuite/riscv/allinsn.exp diff | blob | blame | history
sim/testsuite/riscv/c-ext.s [new file with mode: 0644] blob
sim/testsuite/riscv/jalr.s diff | blob | blame | history
sim/testsuite/riscv/m-ext.s diff | blob | blame | history
sim/testsuite/riscv/pass.s diff | blob | blame | history
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