git.ipfire.org Git - thirdparty/linux.git/blob

1 // SPDX-License-Identifier: GPL-2.0-only

2 /*

4 */

6 #include <linux/bitfield.h>

7 #include <linux/clk.h>

8 #include <linux/component.h>

9 #include <linux/iopoll.h>

10 #include <linux/irq.h>

11 #include <linux/of.h>

12 #include <linux/of_platform.h>

13 #include <linux/phy/phy.h>

14 #include <linux/platform_device.h>

15 #include <linux/reset.h>

16 #include <linux/units.h>

18 #include <video/mipi_display.h>

19 #include <video/videomode.h>

21 #include <drm/drm_atomic_helper.h>

22 #include <drm/drm_bridge.h>

23 #include <drm/drm_bridge_connector.h>

24 #include <drm/drm_mipi_dsi.h>

25 #include <drm/drm_of.h>

26 #include <drm/drm_panel.h>

27 #include <drm/drm_print.h>

28 #include <drm/drm_probe_helper.h>

29 #include <drm/drm_simple_kms_helper.h>

31 #include "mtk_ddp_comp.h"

32 #include "mtk_disp_drv.h"

33 #include "mtk_drm_drv.h"

35 #define DSI_START 0x00

37 #define DSI_INTEN 0x08

39 #define DSI_INTSTA 0x0c

40 #define LPRX_RD_RDY_INT_FLAG BIT(0)

41 #define CMD_DONE_INT_FLAG BIT(1)

42 #define TE_RDY_INT_FLAG BIT(2)

43 #define VM_DONE_INT_FLAG BIT(3)

44 #define EXT_TE_RDY_INT_FLAG BIT(4)

45 #define DSI_BUSY BIT(31)

47 #define DSI_CON_CTRL 0x10

48 #define DSI_RESET BIT(0)

49 #define DSI_EN BIT(1)

50 #define DPHY_RESET BIT(2)

52 #define DSI_MODE_CTRL 0x14

53 #define MODE (3)

54 #define CMD_MODE 0

55 #define SYNC_PULSE_MODE 1

56 #define SYNC_EVENT_MODE 2

57 #define BURST_MODE 3

58 #define FRM_MODE BIT(16)

59 #define MIX_MODE BIT(17)

61 #define DSI_TXRX_CTRL 0x18

62 #define VC_NUM BIT(1)

63 #define LANE_NUM GENMASK(5, 2)

64 #define DIS_EOT BIT(6)

65 #define NULL_EN BIT(7)

66 #define TE_FREERUN BIT(8)

67 #define EXT_TE_EN BIT(9)

68 #define EXT_TE_EDGE BIT(10)

69 #define MAX_RTN_SIZE GENMASK(15, 12)

70 #define HSTX_CKLP_EN BIT(16)

72 #define DSI_PSCTRL 0x1c

73 #define DSI_PS_WC GENMASK(13, 0)

74 #define DSI_PS_SEL GENMASK(17, 16)

75 #define PACKED_PS_16BIT_RGB565 0

76 #define PACKED_PS_18BIT_RGB666 1

77 #define LOOSELY_PS_24BIT_RGB666 2

78 #define PACKED_PS_24BIT_RGB888 3

80 #define DSI_VSA_NL 0x20

81 #define DSI_VBP_NL 0x24

82 #define DSI_VFP_NL 0x28

83 #define DSI_VACT_NL 0x2C

84 #define VACT_NL GENMASK(14, 0)

85 #define DSI_SIZE_CON 0x38

86 #define DSI_HEIGHT GENMASK(30, 16)

87 #define DSI_WIDTH GENMASK(14, 0)

88 #define DSI_HSA_WC 0x50

89 #define DSI_HBP_WC 0x54

90 #define DSI_HFP_WC 0x58

91 #define HFP_HS_VB_PS_WC GENMASK(30, 16)

92 #define HFP_HS_EN BIT(31)

94 #define DSI_CMDQ_SIZE 0x60

95 #define CMDQ_SIZE 0x3f

96 #define CMDQ_SIZE_SEL BIT(15)

98 #define DSI_HSTX_CKL_WC 0x64

99 #define HSTX_CKL_WC GENMASK(15, 2)

100

101 #define DSI_RX_DATA0 0x74

102 #define DSI_RX_DATA1 0x78

103 #define DSI_RX_DATA2 0x7c

104 #define DSI_RX_DATA3 0x80

105

106 #define DSI_RACK 0x84

107 #define RACK BIT(0)

108

109 #define DSI_PHY_LCCON 0x104

110 #define LC_HS_TX_EN BIT(0)

111 #define LC_ULPM_EN BIT(1)

112 #define LC_WAKEUP_EN BIT(2)

113

114 #define DSI_PHY_LD0CON 0x108

115 #define LD0_HS_TX_EN BIT(0)

116 #define LD0_ULPM_EN BIT(1)

117 #define LD0_WAKEUP_EN BIT(2)

118

119 #define DSI_PHY_TIMECON0 0x110

120 #define LPX GENMASK(7, 0)

121 #define HS_PREP GENMASK(15, 8)

122 #define HS_ZERO GENMASK(23, 16)

123 #define HS_TRAIL GENMASK(31, 24)

124

125 #define DSI_PHY_TIMECON1 0x114

126 #define TA_GO GENMASK(7, 0)

127 #define TA_SURE GENMASK(15, 8)

128 #define TA_GET GENMASK(23, 16)

129 #define DA_HS_EXIT GENMASK(31, 24)

130

131 #define DSI_PHY_TIMECON2 0x118

132 #define CONT_DET GENMASK(7, 0)

133 #define DA_HS_SYNC GENMASK(15, 8)

134 #define CLK_ZERO GENMASK(23, 16)

135 #define CLK_TRAIL GENMASK(31, 24)

136

137 #define DSI_PHY_TIMECON3 0x11c

138 #define CLK_HS_PREP GENMASK(7, 0)

139 #define CLK_HS_POST GENMASK(15, 8)

140 #define CLK_HS_EXIT GENMASK(23, 16)

141

142 #define DSI_VM_CMD_CON 0x130

143 #define VM_CMD_EN BIT(0)

144 #define TS_VFP_EN BIT(5)

145

146 #define DSI_SHADOW_DEBUG 0x190U

147 #define FORCE_COMMIT BIT(0)

148 #define BYPASS_SHADOW BIT(1)

149

150 /* CMDQ related bits */

151 #define CONFIG GENMASK(7, 0)

152 #define SHORT_PACKET 0

153 #define LONG_PACKET 2

154 #define BTA BIT(2)

155 #define DATA_ID GENMASK(15, 8)

156 #define DATA_0 GENMASK(23, 16)

157 #define DATA_1 GENMASK(31, 24)

158

159 #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))

160

161 #define MTK_DSI_HOST_IS_READ(type) \

162 ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \

163 (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \

164 (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \

165 (type == MIPI_DSI_DCS_READ))

166

167 struct mtk_phy_timing {

168 u32 lpx;

169 u32 da_hs_prepare;

170 u32 da_hs_zero;

171 u32 da_hs_trail;

172

173 u32 ta_go;

174 u32 ta_sure;

175 u32 ta_get;

176 u32 da_hs_exit;

177

178 u32 clk_hs_zero;

179 u32 clk_hs_trail;

180

181 u32 clk_hs_prepare;

182 u32 clk_hs_post;

183 u32 clk_hs_exit;

184 };

185

186 struct phy;

187

188 struct mtk_dsi_driver_data {

189 const u32 reg_cmdq_off;

190 bool has_shadow_ctl;

191 bool has_size_ctl;

192 bool cmdq_long_packet_ctl;

193 bool support_per_frame_lp;

194 };

195

196 struct mtk_dsi {

197 struct device *dev;

198 struct mipi_dsi_host host;

199 struct drm_encoder encoder;

200 struct drm_bridge bridge;

201 struct drm_bridge *next_bridge;

202 struct drm_connector *connector;

203 struct phy *phy;

204

205 void __iomem *regs;

206

207 struct clk *engine_clk;

208 struct clk *digital_clk;

209 struct clk *hs_clk;

210

211 u32 data_rate;

212

213 unsigned long mode_flags;

214 enum mipi_dsi_pixel_format format;

215 unsigned int lanes;

216 struct videomode vm;

217 struct mtk_phy_timing phy_timing;

218 int refcount;

219 bool enabled;

220 bool lanes_ready;

221 u32 irq_data;

222 wait_queue_head_t irq_wait_queue;

223 const struct mtk_dsi_driver_data *driver_data;

224 };

225

226 static inline struct mtk_dsi *bridge_to_dsi(struct drm_bridge *b)

227 {

228 return container_of(b, struct mtk_dsi, bridge);

229 }

230

231 static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)

232 {

233 return container_of(h, struct mtk_dsi, host);

234 }

235

236 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)

237 {

238 u32 temp = readl(dsi->regs + offset);

239

240 writel((temp & ~mask) | (data & mask), dsi->regs + offset);

241 }

242

243 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)

244 {

245 u32 timcon0, timcon1, timcon2, timcon3;

246 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ);

247 struct mtk_phy_timing *timing = &dsi->phy_timing;

248

249 timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;

250 timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;

251 timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -

252 timing->da_hs_prepare;

253 timing->da_hs_trail = timing->da_hs_prepare + 1;

254

255 timing->ta_go = 4 * timing->lpx - 2;

256 timing->ta_sure = timing->lpx + 2;

257 timing->ta_get = 4 * timing->lpx;

258 timing->da_hs_exit = 2 * timing->lpx + 1;

259

260 timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);

261 timing->clk_hs_post = timing->clk_hs_prepare + 8;

262 timing->clk_hs_trail = timing->clk_hs_prepare;

263 timing->clk_hs_zero = timing->clk_hs_trail * 4;

264 timing->clk_hs_exit = 2 * timing->clk_hs_trail;

265

266 timcon0 = FIELD_PREP(LPX, timing->lpx) |

267 FIELD_PREP(HS_PREP, timing->da_hs_prepare) |

268 FIELD_PREP(HS_ZERO, timing->da_hs_zero) |

269 FIELD_PREP(HS_TRAIL, timing->da_hs_trail);

270

271 timcon1 = FIELD_PREP(TA_GO, timing->ta_go) |

272 FIELD_PREP(TA_SURE, timing->ta_sure) |

273 FIELD_PREP(TA_GET, timing->ta_get) |

274 FIELD_PREP(DA_HS_EXIT, timing->da_hs_exit);

275

276 timcon2 = FIELD_PREP(DA_HS_SYNC, 1) |

277 FIELD_PREP(CLK_ZERO, timing->clk_hs_zero) |

278 FIELD_PREP(CLK_TRAIL, timing->clk_hs_trail);

279

280 timcon3 = FIELD_PREP(CLK_HS_PREP, timing->clk_hs_prepare) |

281 FIELD_PREP(CLK_HS_POST, timing->clk_hs_post) |

282 FIELD_PREP(CLK_HS_EXIT, timing->clk_hs_exit);

283

284 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);

285 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);

286 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);

287 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);

288 }

289

290 static void mtk_dsi_enable(struct mtk_dsi *dsi)

291 {

292 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);

293 }

294

295 static void mtk_dsi_disable(struct mtk_dsi *dsi)

296 {

297 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);

298 }

299

300 static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)

301 {

302 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);

303 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);

304 }

305

306 static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)

307 {

308 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);

309 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);

310 }

311

312 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)

313 {

314 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);

315 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);

316 }

317

318 static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)

319 {

320 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);

321 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);

322 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);

323 }

324

325 static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)

326 {

327 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);

328 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);

329 }

330

331 static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)

332 {

333 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);

334 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);

335 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);

336 }

337

338 static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)

339 {

340 return readl(dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN;

341 }

342

343 static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)

344 {

345 if (enter && !mtk_dsi_clk_hs_state(dsi))

346 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);

347 else if (!enter && mtk_dsi_clk_hs_state(dsi))

348 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);

349 }

350

351 static void mtk_dsi_set_mode(struct mtk_dsi *dsi)

352 {

353 u32 vid_mode = CMD_MODE;

354

355 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {

356 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)

357 vid_mode = BURST_MODE;

358 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)

359 vid_mode = SYNC_PULSE_MODE;

360 else

361 vid_mode = SYNC_EVENT_MODE;

362 }

363

364 writel(vid_mode, dsi->regs + DSI_MODE_CTRL);

365 }

366

367 static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)

368 {

369 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);

370 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);

371 }

372

373 static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)

374 {

375 u32 regval, tmp_reg = 0;

376 u8 i;

377

378 /* Number of DSI lanes (max 4 lanes), each bit enables one DSI lane. */

379 for (i = 0; i < dsi->lanes; i++)

380 tmp_reg |= BIT(i);

381

382 regval = FIELD_PREP(LANE_NUM, tmp_reg);

383

384 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)

385 regval |= HSTX_CKLP_EN;

386

387 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)

388 regval |= DIS_EOT;

389

390 writel(regval, dsi->regs + DSI_TXRX_CTRL);

391 }

392

393 static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact)

394 {

395 u32 dsi_buf_bpp, ps_val, ps_wc, vact_nl;

396

397 if (dsi->format == MIPI_DSI_FMT_RGB565)

398 dsi_buf_bpp = 2;

399 else

400 dsi_buf_bpp = 3;

401

402 /* Word count */

403 ps_wc = FIELD_PREP(DSI_PS_WC, dsi->vm.hactive * dsi_buf_bpp);

404 ps_val = ps_wc;

405

406 /* Pixel Stream type */

407 switch (dsi->format) {

408 default:

409 fallthrough;

410 case MIPI_DSI_FMT_RGB888:

411 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_24BIT_RGB888);

412 break;

413 case MIPI_DSI_FMT_RGB666:

414 ps_val |= FIELD_PREP(DSI_PS_SEL, LOOSELY_PS_24BIT_RGB666);

415 break;

416 case MIPI_DSI_FMT_RGB666_PACKED:

417 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_18BIT_RGB666);

418 break;

419 case MIPI_DSI_FMT_RGB565:

420 ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_16BIT_RGB565);

421 break;

422 }

423

424 if (config_vact) {

425 vact_nl = FIELD_PREP(VACT_NL, dsi->vm.vactive);

426 writel(vact_nl, dsi->regs + DSI_VACT_NL);

427 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);

428 }

429 writel(ps_val, dsi->regs + DSI_PSCTRL);

430 }

431

432 static void mtk_dsi_config_vdo_timing_per_frame_lp(struct mtk_dsi *dsi)

433 {

434 u32 horizontal_sync_active_byte;

435 u32 horizontal_backporch_byte;

436 u32 horizontal_frontporch_byte;

437 u32 hfp_byte_adjust, v_active_adjust;

438 u32 cklp_wc_min_adjust, cklp_wc_max_adjust;

439 u32 dsi_tmp_buf_bpp;

440 unsigned int da_hs_trail;

441 unsigned int ps_wc, hs_vb_ps_wc;

442 u32 v_active_roundup, hstx_cklp_wc;

443 u32 hstx_cklp_wc_max, hstx_cklp_wc_min;

444 struct videomode *vm = &dsi->vm;

445

446 if (dsi->format == MIPI_DSI_FMT_RGB565)

447 dsi_tmp_buf_bpp = 2;

448 else

449 dsi_tmp_buf_bpp = 3;

450

451 da_hs_trail = dsi->phy_timing.da_hs_trail;

452 ps_wc = vm->hactive * dsi_tmp_buf_bpp;

453

454 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {

455 horizontal_sync_active_byte =

456 vm->hsync_len * dsi_tmp_buf_bpp - 10;

457 horizontal_backporch_byte =

458 vm->hback_porch * dsi_tmp_buf_bpp - 10;

459 hfp_byte_adjust = 12;

460 v_active_adjust = 32 + horizontal_sync_active_byte;

461 cklp_wc_min_adjust = 12 + 2 + 4 + horizontal_sync_active_byte;

462 cklp_wc_max_adjust = 20 + 6 + 4 + horizontal_sync_active_byte;

463 } else {

464 horizontal_sync_active_byte = vm->hsync_len * dsi_tmp_buf_bpp - 4;

465 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *

466 dsi_tmp_buf_bpp - 10;

467 cklp_wc_min_adjust = 4;

468 cklp_wc_max_adjust = 12 + 4 + 4;

469 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {

470 hfp_byte_adjust = 18;

471 v_active_adjust = 28;

472 } else {

473 hfp_byte_adjust = 12;

474 v_active_adjust = 22;

475 }

476 }

477 horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp - hfp_byte_adjust;

478 v_active_roundup = (v_active_adjust + horizontal_backporch_byte + ps_wc +

479 horizontal_frontporch_byte) % dsi->lanes;

480 if (v_active_roundup)

481 horizontal_backporch_byte += dsi->lanes - v_active_roundup;

482 hstx_cklp_wc_min = (DIV_ROUND_UP(cklp_wc_min_adjust, dsi->lanes) + da_hs_trail + 1)

483 * dsi->lanes / 6 - 1;

484 hstx_cklp_wc_max = (DIV_ROUND_UP((cklp_wc_max_adjust + horizontal_backporch_byte +

485 ps_wc), dsi->lanes) + da_hs_trail + 1) * dsi->lanes / 6 - 1;

486

487 hstx_cklp_wc = FIELD_PREP(HSTX_CKL_WC, (hstx_cklp_wc_min + hstx_cklp_wc_max) / 2);

488 writel(hstx_cklp_wc, dsi->regs + DSI_HSTX_CKL_WC);

489

490 hs_vb_ps_wc = ps_wc - (dsi->phy_timing.lpx + dsi->phy_timing.da_hs_exit +

491 dsi->phy_timing.da_hs_prepare + dsi->phy_timing.da_hs_zero + 2) * dsi->lanes;

492 horizontal_frontporch_byte |= FIELD_PREP(HFP_HS_EN, 1) |

493 FIELD_PREP(HFP_HS_VB_PS_WC, hs_vb_ps_wc);

494

495 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);

496 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);

497 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);

498 }

499

500 static void mtk_dsi_config_vdo_timing_per_line_lp(struct mtk_dsi *dsi)

501 {

502 u32 horizontal_sync_active_byte;

503 u32 horizontal_backporch_byte;

504 u32 horizontal_frontporch_byte;

505 u32 horizontal_front_back_byte;

506 u32 data_phy_cycles_byte;

507 u32 dsi_tmp_buf_bpp, data_phy_cycles;

508 u32 delta;

509 struct mtk_phy_timing *timing = &dsi->phy_timing;

510 struct videomode *vm = &dsi->vm;

511

512 if (dsi->format == MIPI_DSI_FMT_RGB565)

513 dsi_tmp_buf_bpp = 2;

514 else

515 dsi_tmp_buf_bpp = 3;

516

517 horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);

518

519 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)

520 horizontal_backporch_byte = vm->hback_porch * dsi_tmp_buf_bpp - 10;

521 else

522 horizontal_backporch_byte = (vm->hback_porch + vm->hsync_len) *

523 dsi_tmp_buf_bpp - 10;

524

525 data_phy_cycles = timing->lpx + timing->da_hs_prepare +

526 timing->da_hs_zero + timing->da_hs_exit + 3;

527

528 delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12;

529 delta += dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET ? 0 : 2;

530

531 horizontal_frontporch_byte = vm->hfront_porch * dsi_tmp_buf_bpp;

532 horizontal_front_back_byte = horizontal_frontporch_byte + horizontal_backporch_byte;

533 data_phy_cycles_byte = data_phy_cycles * dsi->lanes + delta;

534

535 if (horizontal_front_back_byte > data_phy_cycles_byte) {

536 horizontal_frontporch_byte -= data_phy_cycles_byte *

537 horizontal_frontporch_byte /

538 horizontal_front_back_byte;

539

540 horizontal_backporch_byte -= data_phy_cycles_byte *

541 horizontal_backporch_byte /

542 horizontal_front_back_byte;

543 } else {

544 DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");

545 }

546

547 if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) &&

548 (dsi->lanes == 4)) {

549 horizontal_sync_active_byte =

550 roundup(horizontal_sync_active_byte, dsi->lanes) - 2;

551 horizontal_frontporch_byte =

552 roundup(horizontal_frontporch_byte, dsi->lanes) - 2;

553 horizontal_backporch_byte =

554 roundup(horizontal_backporch_byte, dsi->lanes) - 2;

555 horizontal_backporch_byte -=

556 (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;

557 }

558

559 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);

560 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);

561 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);

562 }

563

564 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)

565 {

566 struct videomode *vm = &dsi->vm;

567

568 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);

569 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);

570 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);

571 writel(vm->vactive, dsi->regs + DSI_VACT_NL);

572

573 if (dsi->driver_data->has_size_ctl)

574 writel(FIELD_PREP(DSI_HEIGHT, vm->vactive) |

575 FIELD_PREP(DSI_WIDTH, vm->hactive),

576 dsi->regs + DSI_SIZE_CON);

577

578 if (dsi->driver_data->support_per_frame_lp)

579 mtk_dsi_config_vdo_timing_per_frame_lp(dsi);

580 else

581 mtk_dsi_config_vdo_timing_per_line_lp(dsi);

582

583 mtk_dsi_ps_control(dsi, false);

584 }

585

586 static void mtk_dsi_start(struct mtk_dsi *dsi)

587 {

588 writel(0, dsi->regs + DSI_START);

589 writel(1, dsi->regs + DSI_START);

590 }

591

592 static void mtk_dsi_stop(struct mtk_dsi *dsi)

593 {

594 writel(0, dsi->regs + DSI_START);

595 }

596

597 static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)

598 {

599 writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);

600 }

601

602 static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)

603 {

604 u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;

605

606 writel(inten, dsi->regs + DSI_INTEN);

607 }

608

609 static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)

610 {

611 dsi->irq_data |= irq_bit;

612 }

613

614 static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)

615 {

616 dsi->irq_data &= ~irq_bit;

617 }

618

619 static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,

620 unsigned int timeout)

621 {

622 s32 ret = 0;

623 unsigned long jiffies = msecs_to_jiffies(timeout);

624

625 ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,

626 dsi->irq_data & irq_flag,

627 jiffies);

628 if (ret == 0) {

629 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);

630

631 mtk_dsi_enable(dsi);

632 mtk_dsi_reset_engine(dsi);

633 }

634

635 return ret;

636 }

637

638 static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)

639 {

640 struct mtk_dsi *dsi = dev_id;

641 u32 status, tmp;

642 u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;

643

644 status = readl(dsi->regs + DSI_INTSTA) & flag;

645

646 if (status) {

647 do {

648 mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);

649 tmp = readl(dsi->regs + DSI_INTSTA);

650 } while (tmp & DSI_BUSY);

651

652 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);

653 mtk_dsi_irq_data_set(dsi, status);

654 wake_up_interruptible(&dsi->irq_wait_queue);

655 }

656

657 return IRQ_HANDLED;

658 }

659

660 static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)

661 {

662 mtk_dsi_irq_data_clear(dsi, irq_flag);

663 mtk_dsi_set_cmd_mode(dsi);

664

665 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {

666 DRM_ERROR("failed to switch cmd mode\n");

667 return -ETIME;

668 } else {

669 return 0;

670 }

671 }

672

673 static int mtk_dsi_poweron(struct mtk_dsi *dsi)

674 {

675 struct device *dev = dsi->host.dev;

676 int ret;

677 u32 bit_per_pixel;

678

679 if (++dsi->refcount != 1)

680 return 0;

681

682 ret = mipi_dsi_pixel_format_to_bpp(dsi->format);

683 if (ret < 0) {

684 dev_err(dev, "Unknown MIPI DSI format %d\n", dsi->format);

685 return ret;

686 }

687 bit_per_pixel = ret;

688

689 dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,

690 dsi->lanes);

691

692 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);

693 if (ret < 0) {

694 dev_err(dev, "Failed to set data rate: %d\n", ret);

695 goto err_refcount;

696 }

697

698 phy_power_on(dsi->phy);

699

700 ret = clk_prepare_enable(dsi->engine_clk);

701 if (ret < 0) {

702 dev_err(dev, "Failed to enable engine clock: %d\n", ret);

703 goto err_phy_power_off;

704 }

705

706 ret = clk_prepare_enable(dsi->digital_clk);

707 if (ret < 0) {

708 dev_err(dev, "Failed to enable digital clock: %d\n", ret);

709 goto err_disable_engine_clk;

710 }

711

712 mtk_dsi_enable(dsi);

713

714 if (dsi->driver_data->has_shadow_ctl)

715 writel(FORCE_COMMIT | BYPASS_SHADOW,

716 dsi->regs + DSI_SHADOW_DEBUG);

717

718 mtk_dsi_reset_engine(dsi);

719 mtk_dsi_phy_timconfig(dsi);

720

721 mtk_dsi_ps_control(dsi, true);

722 mtk_dsi_set_vm_cmd(dsi);

723 mtk_dsi_config_vdo_timing(dsi);

724 mtk_dsi_set_interrupt_enable(dsi);

725

726 return 0;

727 err_disable_engine_clk:

728 clk_disable_unprepare(dsi->engine_clk);

729 err_phy_power_off:

730 phy_power_off(dsi->phy);

731 err_refcount:

732 dsi->refcount--;

733 return ret;

734 }

735

736 static void mtk_dsi_poweroff(struct mtk_dsi *dsi)

737 {

738 if (WARN_ON(dsi->refcount == 0))

739 return;

740

741 if (--dsi->refcount != 0)

742 return;

743

744 /*

745 * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since

746 * mtk_dsi_stop() should be called after mtk_crtc_atomic_disable(),

747 * which needs irq for vblank, and mtk_dsi_stop() will disable irq.

748 * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),

749 * after dsi is fully set.

750 */

751 mtk_dsi_stop(dsi);

752

753 mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);

754 mtk_dsi_reset_engine(dsi);

755 mtk_dsi_lane0_ulp_mode_enter(dsi);

756 mtk_dsi_clk_ulp_mode_enter(dsi);

757 /* set the lane number as 0 to pull down mipi */

758 writel(0, dsi->regs + DSI_TXRX_CTRL);

759

760 mtk_dsi_disable(dsi);

761

762 clk_disable_unprepare(dsi->engine_clk);

763 clk_disable_unprepare(dsi->digital_clk);

764

765 phy_power_off(dsi->phy);

766

767 dsi->lanes_ready = false;

768 }

769

770 static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)

771 {

772 if (!dsi->lanes_ready) {

773 dsi->lanes_ready = true;

774 mtk_dsi_rxtx_control(dsi);

775 usleep_range(30, 100);

776 mtk_dsi_reset_dphy(dsi);

777 mtk_dsi_clk_ulp_mode_leave(dsi);

778 mtk_dsi_lane0_ulp_mode_leave(dsi);

779 mtk_dsi_clk_hs_mode(dsi, 0);

780 usleep_range(1000, 3000);

781 /* The reaction time after pulling up the mipi signal for dsi_rx */

782 }

783 }

784

785 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)

786 {

787 if (dsi->enabled)

788 return;

789

790 mtk_dsi_lane_ready(dsi);

791 mtk_dsi_set_mode(dsi);

792 mtk_dsi_clk_hs_mode(dsi, 1);

793

794 mtk_dsi_start(dsi);

795

796 dsi->enabled = true;

797 }

798

799 static void mtk_output_dsi_disable(struct mtk_dsi *dsi)

800 {

801 if (!dsi->enabled)

802 return;

803

804 dsi->enabled = false;

805 }

806

807 static int mtk_dsi_bridge_attach(struct drm_bridge *bridge,

808 enum drm_bridge_attach_flags flags)

809 {

810 struct mtk_dsi *dsi = bridge_to_dsi(bridge);

811

812 /* Attach the panel or bridge to the dsi bridge */

813 return drm_bridge_attach(bridge->encoder, dsi->next_bridge,

814 &dsi->bridge, flags);

815 }

816

817 static void mtk_dsi_bridge_mode_set(struct drm_bridge *bridge,

818 const struct drm_display_mode *mode,

819 const struct drm_display_mode *adjusted)

820 {

821 struct mtk_dsi *dsi = bridge_to_dsi(bridge);

822

823 drm_display_mode_to_videomode(adjusted, &dsi->vm);

824 }

825

826 static void mtk_dsi_bridge_atomic_disable(struct drm_bridge *bridge,

827 struct drm_bridge_state *old_bridge_state)

828 {

829 struct mtk_dsi *dsi = bridge_to_dsi(bridge);

830

831 mtk_output_dsi_disable(dsi);

832 }

833

834 static void mtk_dsi_bridge_atomic_enable(struct drm_bridge *bridge,

835 struct drm_bridge_state *old_bridge_state)

836 {

837 struct mtk_dsi *dsi = bridge_to_dsi(bridge);

838

839 if (dsi->refcount == 0)

840 return;

841

842 mtk_output_dsi_enable(dsi);

843 }

844

845 static void mtk_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,

846 struct drm_bridge_state *old_bridge_state)

847 {

848 struct mtk_dsi *dsi = bridge_to_dsi(bridge);

849 int ret;

850

851 ret = mtk_dsi_poweron(dsi);

852 if (ret < 0)

853 DRM_ERROR("failed to power on dsi\n");

854 }

855

856 static void mtk_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge,

857 struct drm_bridge_state *old_bridge_state)

858 {

859 struct mtk_dsi *dsi = bridge_to_dsi(bridge);

860

861 mtk_dsi_poweroff(dsi);

862 }

863

864 static enum drm_mode_status

865 mtk_dsi_bridge_mode_valid(struct drm_bridge *bridge,

866 const struct drm_display_info *info,

867 const struct drm_display_mode *mode)

868 {

869 struct mtk_dsi *dsi = bridge_to_dsi(bridge);

870 int bpp;

871

872 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);

873 if (bpp < 0)

874 return MODE_ERROR;

875

876 if (mode->clock * bpp / dsi->lanes > 1500000)

877 return MODE_CLOCK_HIGH;

878

879 return MODE_OK;

880 }

881

882 static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = {

883 .attach = mtk_dsi_bridge_attach,

884 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,

885 .atomic_disable = mtk_dsi_bridge_atomic_disable,

886 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,

887 .atomic_enable = mtk_dsi_bridge_atomic_enable,

888 .atomic_pre_enable = mtk_dsi_bridge_atomic_pre_enable,

889 .atomic_post_disable = mtk_dsi_bridge_atomic_post_disable,

890 .atomic_reset = drm_atomic_helper_bridge_reset,

891 .mode_valid = mtk_dsi_bridge_mode_valid,

892 .mode_set = mtk_dsi_bridge_mode_set,

893 };

894

895 void mtk_dsi_ddp_start(struct device *dev)

896 {

897 struct mtk_dsi *dsi = dev_get_drvdata(dev);

898

899 mtk_dsi_poweron(dsi);

900 }

901

902 void mtk_dsi_ddp_stop(struct device *dev)

903 {

904 struct mtk_dsi *dsi = dev_get_drvdata(dev);

905

906 mtk_dsi_poweroff(dsi);

907 }

908

909 static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi)

910 {

911 int ret;

912

913 ret = drm_simple_encoder_init(drm, &dsi->encoder,

914 DRM_MODE_ENCODER_DSI);

915 if (ret) {

916 DRM_ERROR("Failed to encoder init to drm\n");

917 return ret;

918 }

919

920 ret = mtk_find_possible_crtcs(drm, dsi->host.dev);

921 if (ret < 0)

922 goto err_cleanup_encoder;

923 dsi->encoder.possible_crtcs = ret;

924

925 ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL,

926 DRM_BRIDGE_ATTACH_NO_CONNECTOR);

927 if (ret)

928 goto err_cleanup_encoder;

929

930 dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder);

931 if (IS_ERR(dsi->connector)) {

932 DRM_ERROR("Unable to create bridge connector\n");

933 ret = PTR_ERR(dsi->connector);

934 goto err_cleanup_encoder;

935 }

936 drm_connector_attach_encoder(dsi->connector, &dsi->encoder);

937

938 return 0;

939

940 err_cleanup_encoder:

941 drm_encoder_cleanup(&dsi->encoder);

942 return ret;

943 }

944

945 unsigned int mtk_dsi_encoder_index(struct device *dev)

946 {

947 struct mtk_dsi *dsi = dev_get_drvdata(dev);

948 unsigned int encoder_index = drm_encoder_index(&dsi->encoder);

949

950 dev_dbg(dev, "encoder index:%d\n", encoder_index);

951 return encoder_index;

952 }

953

954 static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)

955 {

956 int ret;

957 struct drm_device *drm = data;

958 struct mtk_dsi *dsi = dev_get_drvdata(dev);

959

960 ret = mtk_dsi_encoder_init(drm, dsi);

961 if (ret)

962 return ret;

963

964 return device_reset_optional(dev);

965 }

966

967 static void mtk_dsi_unbind(struct device *dev, struct device *master,

968 void *data)

969 {

970 struct mtk_dsi *dsi = dev_get_drvdata(dev);

971

972 drm_encoder_cleanup(&dsi->encoder);

973 }

974

975 static const struct component_ops mtk_dsi_component_ops = {

976 .bind = mtk_dsi_bind,

977 .unbind = mtk_dsi_unbind,

978 };

979

980 static int mtk_dsi_host_attach(struct mipi_dsi_host *host,

981 struct mipi_dsi_device *device)

982 {

983 struct mtk_dsi *dsi = host_to_dsi(host);

984 struct device *dev = host->dev;

985 int ret;

986

987 dsi->lanes = device->lanes;

988 dsi->format = device->format;

989 dsi->mode_flags = device->mode_flags;

990 dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);

991 if (IS_ERR(dsi->next_bridge)) {

992 ret = PTR_ERR(dsi->next_bridge);

993 if (ret == -EPROBE_DEFER)

994 return ret;

995

996 /* Old devicetree has only one endpoint */

997 dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0);

998 if (IS_ERR(dsi->next_bridge))

999 return PTR_ERR(dsi->next_bridge);

1000 }

1001

1002 drm_bridge_add(&dsi->bridge);

1003

1004 ret = component_add(host->dev, &mtk_dsi_component_ops);

1005 if (ret) {

1006 DRM_ERROR("failed to add dsi_host component: %d\n", ret);

1007 drm_bridge_remove(&dsi->bridge);

1008 return ret;

1009 }

1010

1011 return 0;

1012 }

1013

1014 static int mtk_dsi_host_detach(struct mipi_dsi_host *host,

1015 struct mipi_dsi_device *device)

1016 {

1017 struct mtk_dsi *dsi = host_to_dsi(host);

1018

1019 component_del(host->dev, &mtk_dsi_component_ops);

1020 drm_bridge_remove(&dsi->bridge);

1021 return 0;

1022 }

1023

1024 static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)

1025 {

1026 int ret;

1027 u32 val;

1028

1029 ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),

1030 4, 2000000);

1031 if (ret) {

1032 DRM_WARN("polling dsi wait not busy timeout!\n");

1033

1034 mtk_dsi_enable(dsi);

1035 mtk_dsi_reset_engine(dsi);

1036 }

1037 }

1038

1039 static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)

1040 {

1041 switch (type) {

1042 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:

1043 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:

1044 return 1;

1045 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:

1046 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:

1047 return 2;

1048 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:

1049 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:

1050 return read_data[1] + read_data[2] * 16;

1051 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:

1052 DRM_INFO("type is 0x02, try again\n");

1053 break;

1054 default:

1055 DRM_INFO("type(0x%x) not recognized\n", type);

1056 break;

1057 }

1058

1059 return 0;

1060 }

1061

1062 static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)

1063 {

1064 const char *tx_buf = msg->tx_buf;

1065 u8 config, cmdq_size, cmdq_off, type = msg->type;

1066 u32 reg_val, cmdq_mask, i;

1067 u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;

1068

1069 if (MTK_DSI_HOST_IS_READ(type))

1070 config = BTA;

1071 else

1072 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;

1073

1074 if (msg->tx_len > 2) {

1075 cmdq_size = 1 + (msg->tx_len + 3) / 4;

1076 cmdq_off = 4;

1077 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;

1078 reg_val = (msg->tx_len << 16) | (type << 8) | config;

1079 } else {

1080 cmdq_size = 1;

1081 cmdq_off = 2;

1082 cmdq_mask = CONFIG | DATA_ID;

1083 reg_val = (type << 8) | config;

1084 }

1085

1086 for (i = 0; i < msg->tx_len; i++)

1087 mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),

1088 (0xffUL << (((i + cmdq_off) & 3U) * 8U)),

1089 tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));

1090

1091 mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);

1092 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);

1093 if (dsi->driver_data->cmdq_long_packet_ctl) {

1094 /* Disable setting cmdq_size automatically for long packets */

1095 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE_SEL, CMDQ_SIZE_SEL);

1096 }

1097 }

1098

1099 static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,

1100 const struct mipi_dsi_msg *msg, u8 flag)

1101 {

1102 mtk_dsi_wait_for_idle(dsi);

1103 mtk_dsi_irq_data_clear(dsi, flag);

1104 mtk_dsi_cmdq(dsi, msg);

1105 mtk_dsi_start(dsi);

1106

1107 if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))

1108 return -ETIME;

1109 else

1110 return 0;

1111 }

1112

1113 static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,

1114 const struct mipi_dsi_msg *msg)

1115 {

1116 struct mtk_dsi *dsi = host_to_dsi(host);

1117 u32 recv_cnt, i;

1118 u8 read_data[16];

1119 void *src_addr;

1120 u8 irq_flag = CMD_DONE_INT_FLAG;

1121 u32 dsi_mode;

1122 int ret;

1123

1124 dsi_mode = readl(dsi->regs + DSI_MODE_CTRL);

1125 if (dsi_mode & MODE) {

1126 mtk_dsi_stop(dsi);

1127 ret = mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);

1128 if (ret)

1129 goto restore_dsi_mode;

1130 }

1131

1132 if (MTK_DSI_HOST_IS_READ(msg->type))

1133 irq_flag |= LPRX_RD_RDY_INT_FLAG;

1134

1135 mtk_dsi_lane_ready(dsi);

1136

1137 ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag);

1138 if (ret)

1139 goto restore_dsi_mode;

1140

1141 if (!MTK_DSI_HOST_IS_READ(msg->type)) {

1142 recv_cnt = 0;

1143 goto restore_dsi_mode;

1144 }

1145

1146 if (!msg->rx_buf) {

1147 DRM_ERROR("dsi receive buffer size may be NULL\n");

1148 ret = -EINVAL;

1149 goto restore_dsi_mode;

1150 }

1151

1152 for (i = 0; i < 16; i++)

1153 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);

1154

1155 recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);

1156

1157 if (recv_cnt > 2)

1158 src_addr = &read_data[4];

1159 else

1160 src_addr = &read_data[1];

1161

1162 if (recv_cnt > 10)

1163 recv_cnt = 10;

1164

1165 if (recv_cnt > msg->rx_len)

1166 recv_cnt = msg->rx_len;

1167

1168 if (recv_cnt)

1169 memcpy(msg->rx_buf, src_addr, recv_cnt);

1170

1171 DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",

1172 recv_cnt, *((u8 *)(msg->tx_buf)));

1173

1174 restore_dsi_mode:

1175 if (dsi_mode & MODE) {

1176 mtk_dsi_set_mode(dsi);

1177 mtk_dsi_start(dsi);

1178 }

1179

1180 return ret < 0 ? ret : recv_cnt;

1181 }

1182

1183 static const struct mipi_dsi_host_ops mtk_dsi_ops = {

1184 .attach = mtk_dsi_host_attach,

1185 .detach = mtk_dsi_host_detach,

1186 .transfer = mtk_dsi_host_transfer,

1187 };

1188

1189 static int mtk_dsi_probe(struct platform_device *pdev)

1190 {

1191 struct mtk_dsi *dsi;

1192 struct device *dev = &pdev->dev;

1193 struct resource *regs;

1194 int irq_num;

1195 int ret;

1196

1197 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);

1198 if (!dsi)

1199 return -ENOMEM;

1200

1201 dsi->driver_data = of_device_get_match_data(dev);

1202

1203 dsi->engine_clk = devm_clk_get(dev, "engine");

1204 if (IS_ERR(dsi->engine_clk))

1205 return dev_err_probe(dev, PTR_ERR(dsi->engine_clk),

1206 "Failed to get engine clock\n");

1207

1208

1209 dsi->digital_clk = devm_clk_get(dev, "digital");

1210 if (IS_ERR(dsi->digital_clk))

1211 return dev_err_probe(dev, PTR_ERR(dsi->digital_clk),

1212 "Failed to get digital clock\n");

1213

1214 dsi->hs_clk = devm_clk_get(dev, "hs");

1215 if (IS_ERR(dsi->hs_clk))

1216 return dev_err_probe(dev, PTR_ERR(dsi->hs_clk), "Failed to get hs clock\n");

1217

1218 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);

1219 dsi->regs = devm_ioremap_resource(dev, regs);

1220 if (IS_ERR(dsi->regs))

1221 return dev_err_probe(dev, PTR_ERR(dsi->regs), "Failed to ioremap memory\n");

1222

1223 dsi->phy = devm_phy_get(dev, "dphy");

1224 if (IS_ERR(dsi->phy))

1225 return dev_err_probe(dev, PTR_ERR(dsi->phy), "Failed to get MIPI-DPHY\n");

1226

1227 irq_num = platform_get_irq(pdev, 0);

1228 if (irq_num < 0)

1229 return irq_num;

1230

1231 dsi->host.ops = &mtk_dsi_ops;

1232 dsi->host.dev = dev;

1233 ret = mipi_dsi_host_register(&dsi->host);

1234 if (ret < 0)

1235 return dev_err_probe(dev, ret, "Failed to register DSI host\n");

1236

1237 ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,

1238 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), dsi);

1239 if (ret) {

1240 mipi_dsi_host_unregister(&dsi->host);

1241 return dev_err_probe(&pdev->dev, ret, "Failed to request DSI irq\n");

1242 }

1243

1244 init_waitqueue_head(&dsi->irq_wait_queue);

1245

1246 platform_set_drvdata(pdev, dsi);

1247

1248 dsi->bridge.funcs = &mtk_dsi_bridge_funcs;

1249 dsi->bridge.of_node = dev->of_node;

1250 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;

1251

1252 return 0;

1253 }

1254

1255 static void mtk_dsi_remove(struct platform_device *pdev)

1256 {

1257 struct mtk_dsi *dsi = platform_get_drvdata(pdev);

1258

1259 mtk_output_dsi_disable(dsi);

1260 mipi_dsi_host_unregister(&dsi->host);

1261 }

1262

1263 static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {

1264 .reg_cmdq_off = 0x200,

1265 };

1266

1267 static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {

1268 .reg_cmdq_off = 0x180,

1269 };

1270

1271 static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {

1272 .reg_cmdq_off = 0x200,

1273 .has_shadow_ctl = true,

1274 .has_size_ctl = true,

1275 };

1276

1277 static const struct mtk_dsi_driver_data mt8186_dsi_driver_data = {

1278 .reg_cmdq_off = 0xd00,

1279 .has_shadow_ctl = true,

1280 .has_size_ctl = true,

1281 };

1282

1283 static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {

1284 .reg_cmdq_off = 0xd00,

1285 .has_shadow_ctl = true,

1286 .has_size_ctl = true,

1287 .cmdq_long_packet_ctl = true,

1288 .support_per_frame_lp = true,

1289 };

1290

1291 static const struct of_device_id mtk_dsi_of_match[] = {

1292 { .compatible = "mediatek,mt2701-dsi", .data = &mt2701_dsi_driver_data },

1293 { .compatible = "mediatek,mt8173-dsi", .data = &mt8173_dsi_driver_data },

1294 { .compatible = "mediatek,mt8183-dsi", .data = &mt8183_dsi_driver_data },

1295 { .compatible = "mediatek,mt8186-dsi", .data = &mt8186_dsi_driver_data },

1296 { .compatible = "mediatek,mt8188-dsi", .data = &mt8188_dsi_driver_data },

1297 { /* sentinel */ }

1298 };

1299 MODULE_DEVICE_TABLE(of, mtk_dsi_of_match);

1300

1301 struct platform_driver mtk_dsi_driver = {

1302 .probe = mtk_dsi_probe,

1303 .remove_new = mtk_dsi_remove,

1304 .driver = {

1305 .name = "mtk-dsi",

1306 .of_match_table = mtk_dsi_of_match,

1307 },

1308 };