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(parent: 1da8f3a) | patch
target/avr: Improve decode of LDS, STS
authorRichard Henderson <richard.henderson@linaro.org>
Sun, 23 Mar 2025 17:16:23 +0000 (10:16 -0700)
committerRichard Henderson <richard.henderson@linaro.org>
Tue, 22 Apr 2025 21:07:12 +0000 (14:07 -0700)
commit6b661b7ed7cd02c54a78426d5eb7dd8543b030ed
tree8f7b1ccbefa13965cbc3b8c41fa3f78b454769d2tree
parent1da8f3a3c53b604edfe0d55e475102640490549ecommit | diff
target/avr: Improve decode of LDS, STS

The comment about not being able to define a field with
zero bits is out of date since 94597b6146f3
("decodetree: Allow !function with no input bits").

This fixes the missing load of imm in the disassembler.

Cc: qemu-stable@nongnu.org
Fixes: 9d8caa67a24 ("target/avr: Add support for disassembling via option '-d in_asm'")
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
target/avr/insn.decode diff | blob | blame | history
target/avr/translate.c diff | blob | blame | history
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