dwc3: versal: Correct the logic for GFLADJ adjustment

dwc3: versal: Correct the logic for GFLADJ adjustment

This patch corrects the logic used for adjusting GFLADJ register.

Currently during phy initialization, USB core reset is happening.
Because of reset USB GFLADJ register is getting restored to default
values. This patch updates the GFADJ[21:8] & GFLADJ[5:0] bits if
they are not equal to the requested value from dts.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
State: pending