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target/riscv: Fix the rvv reserved encoding of unmasked instructions
authorMax Chou <max.chou@sifive.com>
Tue, 8 Apr 2025 10:39:38 +0000 (18:39 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 19 May 2025 03:39:20 +0000 (13:39 +1000)
commit8539a1244bf240d28917effb88a140eb58e45e88
tree3dd57f5c70d055332e4bac0bff90ed6f41b686d5tree
parentdb21c3eb05504c4cedaad4f7b19e588361b02385commit | diff
target/riscv: Fix the rvv reserved encoding of unmasked instructions

According to the v spec, the encodings of vcomoress.vm and vector
mask-register logical instructions with vm=0 are reserved.

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20250408103938.3623486-11-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable@nongnu.org
target/riscv/insn32.decode diff | blob | blame | history
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