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hw/intc: Don't clear pending bits on IRQ lowering
authorSergey Makarov <s.makarov@syntacore.com>
Wed, 18 Sep 2024 14:02:29 +0000 (17:02 +0300)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 30 Oct 2024 01:22:08 +0000 (11:22 +1000)
commita84be2baa9eca8bc500f866ad943b8f63dc99adf
treee6a973eab31b9f8099e0d6b7f890c524e5cc8e44tree
parent41fc1f02947dd7a33b2c1d0e8474744b12f2514ecommit | diff
hw/intc: Don't clear pending bits on IRQ lowering

According to PLIC specification (chapter 5), there
is only one case, when interrupt is claimed. Fix
PLIC controller to match this behavior.

Signed-off-by: Sergey Makarov <s.makarov@syntacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240918140229.124329-3-s.makarov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
hw/intc/sifive_plic.c diff | blob | blame | history
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