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(parent: 3e8d1e4) | patch
target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS
authorAnton Blanchard <antonb@tenstorrent.com>
Tue, 8 Apr 2025 10:39:30 +0000 (18:39 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 19 May 2025 03:38:33 +0000 (13:38 +1000)
commitb0450a101d6c88789d0e8df2bcbef61bc7cd159a
treee8e82fc5f0a1877f4f3f0eee3e6856b34497ea17tree
parent3e8d1e4a628bb234c0b5d1ccd510900047181dbdcommit | diff
target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS

Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20250408103938.3623486-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable@nongnu.org
target/riscv/insn_trans/trans_rvv.c.inc diff | blob | blame | history
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