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target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI...
authorMax Chou <max.chou@sifive.com>
Tue, 8 Apr 2025 10:39:34 +0000 (18:39 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 19 May 2025 03:39:01 +0000 (13:39 +1000)
commitb5480a693e3e657108746721ffe434b3bb6e7a72
tree9bcf6c488fc3221af3666fba807fb5120ca91422tree
parentfda68acb7761af40df78db18e44ca1ff20195fe0commit | diff
target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX)

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20250408103938.3623486-7-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable@nongnu.org
target/riscv/insn_trans/trans_rvv.c.inc diff | blob | blame | history
Mirror of https://git.qemu.org/git/qemu.git