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(parent: 8aedfb6) | patch
target/mips: enable GINVx support for I6400 and I6500
authorMarcin Nowakowski <marcin.nowakowski@fungible.com>
Fri, 30 Jun 2023 07:28:06 +0000 (09:28 +0200)
committerPhilippe Mathieu-Daudé <philmd@linaro.org>
Mon, 10 Jul 2023 21:33:38 +0000 (23:33 +0200)
commitbaf21eebc3e1026d21d94fdf8ca470050e49968f
tree8fc98f48948de62a2cbc46e55f485466b0759677tree
parent8aedfb64cdcfa60a077c66e802f6c65a419631decommit | diff
target/mips: enable GINVx support for I6400 and I6500

GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores,
so indicate that properly in CP0.Config5 register bits [16:15].

Cc: qemu-stable@nongnu.org
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230630072806.3093704-1-marcin.nowakowski@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
target/mips/cpu-defs.c.inc diff | blob | blame | history
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