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target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions
authorMax Chou <max.chou@sifive.com>
Tue, 8 Apr 2025 10:39:37 +0000 (18:39 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 19 May 2025 03:39:15 +0000 (13:39 +1000)
commitdb21c3eb05504c4cedaad4f7b19e588361b02385
tree44b2617adf9f941d6a3cdabd393d399831247788tree
parent1f090a229f85e662394267680408bd31fd0a99c9commit | diff
target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20250408103938.3623486-10-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable@nongnu.org
target/riscv/insn_trans/trans_rvv.c.inc diff | blob | blame | history
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