]> git.ipfire.org Git - thirdparty/gcc.git/commit
simplify-rtx: Combine bitwise operations in more cases
authorPengfei Li <Pengfei.Li2@arm.com>
Tue, 29 Apr 2025 18:14:42 +0000 (19:14 +0100)
committerRichard Sandiford <richard.sandiford@arm.com>
Tue, 29 Apr 2025 18:14:42 +0000 (19:14 +0100)
commitd84fbc516ea57de7e88fce76ff6f342ee808c02e
tree583180a5b5238762dda3856b99a148ea6840d25d
parent69669180d29cc420b1b1ac86530a4f9573748d81
simplify-rtx: Combine bitwise operations in more cases

This patch transforms RTL expressions of the form (subreg (not X)) into
(not (subreg X)) if the subreg is an operand of another binary logical
operation. This transformation can expose opportunities to combine more
logical operations.

For example, it improves the codegen of the following AArch64 NEON
intrinsics:
vandq_s64(vreinterpretq_s64_s32(vmvnq_s32(a)),
  vreinterpretq_s64_s32(b));
from:
not     v0.16b, v0.16b
and     v0.16b, v0.16b, v1.16b
to:
bic     v0.16b, v1.16b, v0.16b

Regression tested on x86_64-linux-gnu, arm-linux-gnueabihf and
aarch64-linux-gnu.

gcc/ChangeLog:

* simplify-rtx.cc (non_paradoxical_subreg_not_p): New function
for pattern match of (subreg (not X)).
(simplify_with_subreg_not): New function for simplification.
gcc/simplify-rtx.cc
gcc/testsuite/gcc.target/aarch64/simd/bic_orn_1.c [new file with mode: 0644]