From 7b49c9e1c0a48eb0b191bf2f650d133a0c7093a9 Mon Sep 17 00:00:00 2001 From: James Greenhalgh Date: Fri, 6 Sep 2013 13:37:56 +0000 Subject: [PATCH] [ARM,AARCH64] Insn type reclassification. Split f_cvt type. gcc/ * config/arm/types.md (type): Split f_cvt as f_cvt, f_cvtf2i, f_cvti2f. * config/aarch64/aarch64.md (l2): Update with new attributes. (fix_trunc2): Likewise. (fixuns_trunc2): Likewise. (float2): Likewise. * config/arm/vfp.md (*truncsisf2_vfp): Update with new attributes. (*truncsidf2_vfp): Likewise. (fixuns_truncsfsi2): Likewise. (fixuns_truncdfsi2): Likewise. (*floatsisf2_vfp): Likewise. (*floatsidf2_vfp): Likewise. (floatunssisf2): Likewise. (floatunssidf2): Likewise. (*combine_vcvt_f32_): Likewise. (*combine_vcvt_f64_): Likewise. * config/arm/arm1020e.md: Update with new attributes. * config/arm/cortex-a15-neon.md: Update with new attributes. * config/arm/cortex-a5.md: Update with new attributes. * config/arm/cortex-a53.md: Update with new attributes. * config/arm/cortex-a7.md: Update with new attributes. * config/arm/cortex-a8-neon.md: Update with new attributes. * config/arm/cortex-a9.md: Update with new attributes. * config/arm/cortex-m4-fpu.md: Update with new attributes. * config/arm/cortex-r4f.md: Update with new attributes. * config/arm/marvell-pj4.md: Update with new attributes. * config/arm/vfp11.md: Update with new attributes. From-SVN: r202328 --- gcc/ChangeLog | 33 +++++++++++++++++++++++++++++++ gcc/config/aarch64/aarch64.md | 8 ++++---- gcc/config/arm/arm1020e.md | 2 +- gcc/config/arm/cortex-a15-neon.md | 2 +- gcc/config/arm/cortex-a5.md | 3 ++- gcc/config/arm/cortex-a53.md | 3 ++- gcc/config/arm/cortex-a7.md | 2 +- gcc/config/arm/cortex-a8-neon.md | 2 +- gcc/config/arm/cortex-a9.md | 2 +- gcc/config/arm/cortex-m4-fpu.md | 2 +- gcc/config/arm/cortex-r4f.md | 2 +- gcc/config/arm/marvell-pj4.md | 3 ++- gcc/config/arm/types.md | 6 +++++- gcc/config/arm/vfp.md | 20 +++++++++---------- gcc/config/arm/vfp11.md | 3 ++- 15 files changed, 67 insertions(+), 26 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4c33190ec03d..d70d0e4e5b89 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,36 @@ +2013-09-06 James Greenhalgh + + * config/arm/types.md + (type): Split f_cvt as f_cvt, f_cvtf2i, f_cvti2f. + * config/aarch64/aarch64.md + (l2): Update with + new attributes. + (fix_trunc2): Likewise. + (fixuns_trunc2): Likewise. + (float2): Likewise. + * config/arm/vfp.md + (*truncsisf2_vfp): Update with new attributes. + (*truncsidf2_vfp): Likewise. + (fixuns_truncsfsi2): Likewise. + (fixuns_truncdfsi2): Likewise. + (*floatsisf2_vfp): Likewise. + (*floatsidf2_vfp): Likewise. + (floatunssisf2): Likewise. + (floatunssidf2): Likewise. + (*combine_vcvt_f32_): Likewise. + (*combine_vcvt_f64_): Likewise. + * config/arm/arm1020e.md: Update with new attributes. + * config/arm/cortex-a15-neon.md: Update with new attributes. + * config/arm/cortex-a5.md: Update with new attributes. + * config/arm/cortex-a53.md: Update with new attributes. + * config/arm/cortex-a7.md: Update with new attributes. + * config/arm/cortex-a8-neon.md: Update with new attributes. + * config/arm/cortex-a9.md: Update with new attributes. + * config/arm/cortex-m4-fpu.md: Update with new attributes. + * config/arm/cortex-r4f.md: Update with new attributes. + * config/arm/marvell-pj4.md: Update with new attributes. + * config/arm/vfp11.md: Update with new attributes. + 2013-09-06 James Greenhalgh * config/aarch64/arm_neon.h diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 4dfd2ab83d00..6a4a975bb89c 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3685,7 +3685,7 @@ "TARGET_FLOAT" "fcvt\\t%0, %1" [(set_attr "v8type" "fcvtf2i") - (set_attr "type" "f_cvt") + (set_attr "type" "f_cvtf2i") (set_attr "mode" "") (set_attr "mode2" "")] ) @@ -3785,7 +3785,7 @@ "TARGET_FLOAT" "fcvtzs\\t%0, %1" [(set_attr "v8type" "fcvtf2i") - (set_attr "type" "f_cvt") + (set_attr "type" "f_cvtf2i") (set_attr "mode" "") (set_attr "mode2" "")] ) @@ -3796,7 +3796,7 @@ "TARGET_FLOAT" "fcvtzu\\t%0, %1" [(set_attr "v8type" "fcvtf2i") - (set_attr "type" "f_cvt") + (set_attr "type" "f_cvtf2i") (set_attr "mode" "") (set_attr "mode2" "")] ) @@ -3807,7 +3807,7 @@ "TARGET_FLOAT" "scvtf\\t%0, %1" [(set_attr "v8type" "fcvti2f") - (set_attr "type" "f_cvt") + (set_attr "type" "f_cvti2f") (set_attr "mode" "") (set_attr "mode2" "")] ) diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md index 615c6a5b16de..e16e862c1f49 100644 --- a/gcc/config/arm/arm1020e.md +++ b/gcc/config/arm/arm1020e.md @@ -289,7 +289,7 @@ (define_insn_reservation "v10_cvt" 5 (and (eq_attr "vfp10" "yes") - (eq_attr "type" "f_cvt")) + (eq_attr "type" "f_cvt,f_cvti2f,f_cvtf2i")) "1020a_e+v10_fmac") (define_insn_reservation "v10_fmul" 6 diff --git a/gcc/config/arm/cortex-a15-neon.md b/gcc/config/arm/cortex-a15-neon.md index f1cac9e1af88..b5d14e7f7f9c 100644 --- a/gcc/config/arm/cortex-a15-neon.md +++ b/gcc/config/arm/cortex-a15-neon.md @@ -471,7 +471,7 @@ (define_insn_reservation "cortex_a15_vfp_cvt" 6 (and (eq_attr "tune" "cortexa15") - (eq_attr "type" "f_cvt")) + (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f")) "ca15_issue1,ca15_cx_vfp") (define_insn_reservation "cortex_a15_vfp_cmpd" 8 diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md index 8930baf8daff..54c8c420324a 100644 --- a/gcc/config/arm/cortex-a5.md +++ b/gcc/config/arm/cortex-a5.md @@ -168,7 +168,8 @@ (define_insn_reservation "cortex_a5_fpalu" 4 (and (eq_attr "tune" "cortexa5") - (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\ + (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls,\ + f_cvt,f_cvtf2i,f_cvti2f,\ fcmps, fcmpd")) "cortex_a5_ex1+cortex_a5_fpadd_pipe") diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index 66d4cb436f5f..e84b9ea1a71e 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -209,7 +209,8 @@ (define_insn_reservation "cortex_a53_fpalu" 4 (and (eq_attr "tune" "cortexa53") - (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\ + (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls,\ + f_cvt,f_cvtf2i,f_cvti2f,\ fcmps, fcmpd, fcsel")) "cortex_a53_slot0+cortex_a53_fpadd_pipe") diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md index bd7aecda021e..6d7b43685a3a 100644 --- a/gcc/config/arm/cortex-a7.md +++ b/gcc/config/arm/cortex-a7.md @@ -205,7 +205,7 @@ (define_insn_reservation "cortex_a7_fpalu" 4 (and (eq_attr "tune" "cortexa7") (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys,\ - f_cvt, fcmps, fcmpd")) + f_cvt, f_cvtf2i, f_cvti2f, fcmps, fcmpd")) "cortex_a7_ex1+cortex_a7_fpadd_pipe") ;; For fconsts and fconstd, 8-bit immediate data is passed directly from diff --git a/gcc/config/arm/cortex-a8-neon.md b/gcc/config/arm/cortex-a8-neon.md index 57a81142a18f..6953a9590a5c 100644 --- a/gcc/config/arm/cortex-a8-neon.md +++ b/gcc/config/arm/cortex-a8-neon.md @@ -177,7 +177,7 @@ (define_insn_reservation "cortex_a8_vfp_cvt" 7 (and (eq_attr "tune" "cortexa8") - (eq_attr "type" "f_cvt")) + (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f")) "cortex_a8_vfp,cortex_a8_vfplite*6") ;; NEON -> core transfers. diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md index 4703bf36b2f8..a66481807cf4 100644 --- a/gcc/config/arm/cortex-a9.md +++ b/gcc/config/arm/cortex-a9.md @@ -233,7 +233,7 @@ cortex_a9_store3_4, cortex_a9_store1_2, cortex_a9_load3_4") (define_insn_reservation "cortex_a9_fadd" 4 (and (eq_attr "tune" "cortexa9") - (eq_attr "type" "fadds, faddd, f_cvt")) + (eq_attr "type" "fadds, faddd, f_cvt, f_cvtf2i, f_cvti2f")) "ca9fp_add") (define_insn_reservation "cortex_a9_fcmp" 1 diff --git a/gcc/config/arm/cortex-m4-fpu.md b/gcc/config/arm/cortex-m4-fpu.md index f148e9dba798..81c12b74f65c 100644 --- a/gcc/config/arm/cortex-m4-fpu.md +++ b/gcc/config/arm/cortex-m4-fpu.md @@ -77,7 +77,7 @@ (define_insn_reservation "cortex_m4_f_cvt" 2 (and (eq_attr "tune" "cortexm4") - (eq_attr "type" "f_cvt")) + (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f")) "cortex_m4_ex_v") (define_insn_reservation "cortex_m4_f_load" 2 diff --git a/gcc/config/arm/cortex-r4f.md b/gcc/config/arm/cortex-r4f.md index 8262ccd5b659..06e061e2b145 100644 --- a/gcc/config/arm/cortex-r4f.md +++ b/gcc/config/arm/cortex-r4f.md @@ -146,7 +146,7 @@ (define_insn_reservation "cortex_r4_f_cvt" 8 (and (eq_attr "tune_cortexr4" "yes") - (eq_attr "type" "f_cvt")) + (eq_attr "type" "f_cvt,f_cvtf2i,f_cvti2f")) "cortex_r4_single_issue*3") (define_insn_reservation "cortex_r4_f_memd" 8 diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md index f6e4e011c338..d9cf8d4b6b57 100644 --- a/gcc/config/arm/marvell-pj4.md +++ b/gcc/config/arm/marvell-pj4.md @@ -209,7 +209,8 @@ (define_insn_reservation "pj4_vfp_cpy" 4 (and (eq_attr "tune" "marvell_pj4") (eq_attr "type" "fcpys,ffariths,ffarithd,fconsts,fconstd,\ - fcmps,fcmpd,f_cvt")) "pj4_is,nothing*2,vissue,vfast,nothing*2") + fcmps,fcmpd,f_cvt,f_cvtf2i,f_cvti2f")) +"pj4_is,nothing*2,vissue,vfast,nothing*2") ;; Enlarge latency, and wish that more nondependent insns are ;; scheduled immediately after VFP load. diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index ed2522b0cfef..de817634ec98 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -55,7 +55,9 @@ ; clz count leading zeros (CLZ). ; csel From ARMv8-A: conditional select. ; extend extend instruction (SXTB, SXTH, UXTB, UXTH). -; f_cvt conversion between float and integral. +; f_cvt conversion between float representations. +; f_cvtf2i conversion between float and integral types. +; f_cvti2f conversion between integral and float types. ; f_flag transfer of co-processor flags to the CPSR. ; f_load[d,s] double/single load from memory. Used for VFP unit. ; f_mcr transfer arm to vfp reg. @@ -311,6 +313,8 @@ csel,\ extend,\ f_cvt,\ + f_cvtf2i,\ + f_cvti2f,\ f_flag,\ f_loadd,\ f_loads,\ diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 419a78984b82..0e61c6eff004 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -991,7 +991,7 @@ "ftosizs%?\\t%0, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "f_cvt")] + (set_attr "type" "f_cvtf2i")] ) (define_insn "*truncsidf2_vfp" @@ -1001,7 +1001,7 @@ "ftosizd%?\\t%0, %P1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "f_cvt")] + (set_attr "type" "f_cvtf2i")] ) @@ -1012,7 +1012,7 @@ "ftouizs%?\\t%0, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "f_cvt")] + (set_attr "type" "f_cvtf2i")] ) (define_insn "fixuns_truncdfsi2" @@ -1022,7 +1022,7 @@ "ftouizd%?\\t%0, %P1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "f_cvt")] + (set_attr "type" "f_cvtf2i")] ) @@ -1033,7 +1033,7 @@ "fsitos%?\\t%0, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "f_cvt")] + (set_attr "type" "f_cvti2f")] ) (define_insn "*floatsidf2_vfp" @@ -1043,7 +1043,7 @@ "fsitod%?\\t%P0, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "f_cvt")] + (set_attr "type" "f_cvti2f")] ) @@ -1054,7 +1054,7 @@ "fuitos%?\\t%0, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "f_cvt")] + (set_attr "type" "f_cvti2f")] ) (define_insn "floatunssidf2" @@ -1064,7 +1064,7 @@ "fuitod%?\\t%P0, %1" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "f_cvt")] + (set_attr "type" "f_cvti2f")] ) @@ -1229,7 +1229,7 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math" "vcvt.f32.\\t%0, %1, %v2" [(set_attr "predicable" "no") - (set_attr "type" "f_cvt")] + (set_attr "type" "f_cvti2f")] ) ;; Not the ideal way of implementing this. Ideally we would be able to split @@ -1246,7 +1246,7 @@ vmov.f32\\t%0, %1\;vcvt.f64.\\t%P0, %P0, %v2 vmov.f64\\t%P0, %1, %1\;vcvt.f64.\\t%P0, %P0, %v2" [(set_attr "predicable" "no") - (set_attr "type" "f_cvt") + (set_attr "type" "f_cvti2f") (set_attr "length" "8")] ) diff --git a/gcc/config/arm/vfp11.md b/gcc/config/arm/vfp11.md index 9e6ba849a718..3cc343e0186d 100644 --- a/gcc/config/arm/vfp11.md +++ b/gcc/config/arm/vfp11.md @@ -56,7 +56,8 @@ (define_insn_reservation "vfp_farith" 8 (and (eq_attr "generic_vfp" "yes") - (eq_attr "type" "fadds,faddd,fconsts,fconstd,f_cvt,fmuls,fmacs,ffmas")) + (eq_attr "type" "fadds,faddd,fconsts,fconstd,f_cvt,f_cvtf2i,f_cvti2f,\ + fmuls,fmacs,ffmas")) "fmac") (define_insn_reservation "vfp_fmul" 9 -- 2.39.5