From 081aaba705feea37986e02873e17348627e79770 Mon Sep 17 00:00:00 2001 From: Julian Ganz Date: Mon, 27 Oct 2025 11:03:29 +0000 Subject: [PATCH] target/riscv: call plugin trap callbacks MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for RISC-V targets. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Julian Ganz Message-ID: <20251027110344.2289945-23-alex.bennee@linaro.org> Signed-off-by: Alex Bennée --- target/riscv/cpu_helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 360db133e2..c4fb68b5de 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -36,6 +36,7 @@ #include "cpu_bits.h" #include "debug.h" #include "pmp.h" +#include "qemu/plugin.h" int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) { @@ -2175,6 +2176,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) uint64_t hdeleg = async ? env->hideleg : env->hedeleg; const bool prev_virt = env->virt_enabled; const target_ulong prev_priv = env->priv; + uint64_t last_pc = env->pc; target_ulong tval = 0; target_ulong tinst = 0; target_ulong htval = 0; @@ -2197,6 +2199,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_SEMIHOST: do_common_semihosting(cs); env->pc += 4; + qemu_plugin_vcpu_hostcall_cb(cs, last_pc); return; #endif case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: @@ -2466,6 +2469,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) prev_priv, prev_virt); } + if (async) { + qemu_plugin_vcpu_interrupt_cb(cs, last_pc); + } else { + qemu_plugin_vcpu_exception_cb(cs, last_pc); + } + /* * Interrupt/exception/trap delivery is asynchronous event and as per * zicfilp spec CPU should clear up the ELP state. No harm in clearing -- 2.47.3