From 08c0c8aef0028c7ab3b3e7768e47c5eeba393a64 Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Wed, 5 Feb 2020 23:53:40 -0500 Subject: [PATCH] fixes for 4.9 Signed-off-by: Sasha Levin --- ...a-iguanair-fix-endpoint-sanity-check.patch | 44 +++++++++++ queue-4.9/series | 3 + ...ix-struct-ipc64_perm-type-definition.patch | 74 +++++++++++++++++++ ...ached-hle-state-on-write-to-tsx_ctrl.patch | 67 +++++++++++++++++ 4 files changed, 188 insertions(+) create mode 100644 queue-4.9/media-iguanair-fix-endpoint-sanity-check.patch create mode 100644 queue-4.9/series create mode 100644 queue-4.9/sparc32-fix-struct-ipc64_perm-type-definition.patch create mode 100644 queue-4.9/x86-cpu-update-cached-hle-state-on-write-to-tsx_ctrl.patch diff --git a/queue-4.9/media-iguanair-fix-endpoint-sanity-check.patch b/queue-4.9/media-iguanair-fix-endpoint-sanity-check.patch new file mode 100644 index 00000000000..0e5242eaacc --- /dev/null +++ b/queue-4.9/media-iguanair-fix-endpoint-sanity-check.patch @@ -0,0 +1,44 @@ +From 20a73f6317df37ad62fe7883e1ff853923cf1f2f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 3 Jan 2020 17:35:13 +0100 +Subject: media: iguanair: fix endpoint sanity check + +From: Johan Hovold + +[ Upstream commit 1b257870a78b0a9ce98fdfb052c58542022ffb5b ] + +Make sure to use the current alternate setting, which need not be the +first one by index, when verifying the endpoint descriptors and +initialising the URBs. + +Failing to do so could cause the driver to misbehave or trigger a WARN() +in usb_submit_urb() that kernels with panic_on_warn set would choke on. + +Fixes: 26ff63137c45 ("[media] Add support for the IguanaWorks USB IR Transceiver") +Fixes: ab1cbdf159be ("media: iguanair: add sanity checks") +Cc: stable # 3.6 +Cc: Oliver Neukum +Signed-off-by: Johan Hovold +Signed-off-by: Sean Young +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +--- + drivers/media/rc/iguanair.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/media/rc/iguanair.c b/drivers/media/rc/iguanair.c +index 25470395c43f1..246795c315533 100644 +--- a/drivers/media/rc/iguanair.c ++++ b/drivers/media/rc/iguanair.c +@@ -430,7 +430,7 @@ static int iguanair_probe(struct usb_interface *intf, + int ret, pipein, pipeout; + struct usb_host_interface *idesc; + +- idesc = intf->altsetting; ++ idesc = intf->cur_altsetting; + if (idesc->desc.bNumEndpoints < 2) + return -ENODEV; + +-- +2.20.1 + diff --git a/queue-4.9/series b/queue-4.9/series new file mode 100644 index 00000000000..e72c0b43793 --- /dev/null +++ b/queue-4.9/series @@ -0,0 +1,3 @@ +media-iguanair-fix-endpoint-sanity-check.patch +x86-cpu-update-cached-hle-state-on-write-to-tsx_ctrl.patch +sparc32-fix-struct-ipc64_perm-type-definition.patch diff --git a/queue-4.9/sparc32-fix-struct-ipc64_perm-type-definition.patch b/queue-4.9/sparc32-fix-struct-ipc64_perm-type-definition.patch new file mode 100644 index 00000000000..5f8b489777a --- /dev/null +++ b/queue-4.9/sparc32-fix-struct-ipc64_perm-type-definition.patch @@ -0,0 +1,74 @@ +From 3d0ac6cee44b3d31036a55a6fffa6a3f1789ac49 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 14 Jan 2020 14:26:14 +0100 +Subject: sparc32: fix struct ipc64_perm type definition + +From: Arnd Bergmann + +[ Upstream commit 34ca70ef7d3a9fa7e89151597db5e37ae1d429b4 ] + +As discussed in the strace issue tracker, it appears that the sparc32 +sysvipc support has been broken for the past 11 years. It was however +working in compat mode, which is how it must have escaped most of the +regular testing. + +The problem is that a cleanup patch inadvertently changed the uid/gid +fields in struct ipc64_perm from 32-bit types to 16-bit types in uapi +headers. + +Both glibc and uclibc-ng still use the original types, so they should +work fine with compat mode, but not natively. Change the definitions +to use __kernel_uid32_t and __kernel_gid32_t again. + +Fixes: 83c86984bff2 ("sparc: unify ipcbuf.h") +Link: https://github.com/strace/strace/issues/116 +Cc: # v2.6.29 +Cc: Sam Ravnborg +Cc: "Dmitry V . Levin" +Cc: Rich Felker +Cc: libc-alpha@sourceware.org +Signed-off-by: Arnd Bergmann +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + arch/sparc/include/uapi/asm/ipcbuf.h | 22 +++++++++++----------- + 1 file changed, 11 insertions(+), 11 deletions(-) + +diff --git a/arch/sparc/include/uapi/asm/ipcbuf.h b/arch/sparc/include/uapi/asm/ipcbuf.h +index 66013b4fe10d5..58da9c4addb2d 100644 +--- a/arch/sparc/include/uapi/asm/ipcbuf.h ++++ b/arch/sparc/include/uapi/asm/ipcbuf.h +@@ -14,19 +14,19 @@ + + struct ipc64_perm + { +- __kernel_key_t key; +- __kernel_uid_t uid; +- __kernel_gid_t gid; +- __kernel_uid_t cuid; +- __kernel_gid_t cgid; ++ __kernel_key_t key; ++ __kernel_uid32_t uid; ++ __kernel_gid32_t gid; ++ __kernel_uid32_t cuid; ++ __kernel_gid32_t cgid; + #ifndef __arch64__ +- unsigned short __pad0; ++ unsigned short __pad0; + #endif +- __kernel_mode_t mode; +- unsigned short __pad1; +- unsigned short seq; +- unsigned long long __unused1; +- unsigned long long __unused2; ++ __kernel_mode_t mode; ++ unsigned short __pad1; ++ unsigned short seq; ++ unsigned long long __unused1; ++ unsigned long long __unused2; + }; + + #endif /* __SPARC_IPCBUF_H */ +-- +2.20.1 + diff --git a/queue-4.9/x86-cpu-update-cached-hle-state-on-write-to-tsx_ctrl.patch b/queue-4.9/x86-cpu-update-cached-hle-state-on-write-to-tsx_ctrl.patch new file mode 100644 index 00000000000..8629cb77f3b --- /dev/null +++ b/queue-4.9/x86-cpu-update-cached-hle-state-on-write-to-tsx_ctrl.patch @@ -0,0 +1,67 @@ +From 9703b2a49b466ae6b4073cc33e56681d50736ee0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 10 Jan 2020 14:50:54 -0800 +Subject: x86/cpu: Update cached HLE state on write to TSX_CTRL_CPUID_CLEAR + +From: Pawan Gupta + +[ Upstream commit 5efc6fa9044c3356d6046c6e1da6d02572dbed6b ] + +/proc/cpuinfo currently reports Hardware Lock Elision (HLE) feature to +be present on boot cpu even if it was disabled during the bootup. This +is because cpuinfo_x86->x86_capability HLE bit is not updated after TSX +state is changed via the new MSR IA32_TSX_CTRL. + +Update the cached HLE bit also since it is expected to change after an +update to CPUID_CLEAR bit in MSR IA32_TSX_CTRL. + +Fixes: 95c5824f75f3 ("x86/cpu: Add a "tsx=" cmdline option with TSX disabled by default") +Signed-off-by: Pawan Gupta +Signed-off-by: Thomas Gleixner +Tested-by: Neelima Krishnan +Reviewed-by: Dave Hansen +Reviewed-by: Josh Poimboeuf +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/2529b99546294c893dfa1c89e2b3e46da3369a59.1578685425.git.pawan.kumar.gupta@linux.intel.com +Signed-off-by: Sasha Levin +--- + arch/x86/kernel/cpu/tsx.c | 13 +++++++------ + 1 file changed, 7 insertions(+), 6 deletions(-) + +diff --git a/arch/x86/kernel/cpu/tsx.c b/arch/x86/kernel/cpu/tsx.c +index 3e20d322bc98b..032509adf9de9 100644 +--- a/arch/x86/kernel/cpu/tsx.c ++++ b/arch/x86/kernel/cpu/tsx.c +@@ -115,11 +115,12 @@ void __init tsx_init(void) + tsx_disable(); + + /* +- * tsx_disable() will change the state of the +- * RTM CPUID bit. Clear it here since it is now +- * expected to be not set. ++ * tsx_disable() will change the state of the RTM and HLE CPUID ++ * bits. Clear them here since they are now expected to be not ++ * set. + */ + setup_clear_cpu_cap(X86_FEATURE_RTM); ++ setup_clear_cpu_cap(X86_FEATURE_HLE); + } else if (tsx_ctrl_state == TSX_CTRL_ENABLE) { + + /* +@@ -131,10 +132,10 @@ void __init tsx_init(void) + tsx_enable(); + + /* +- * tsx_enable() will change the state of the +- * RTM CPUID bit. Force it here since it is now +- * expected to be set. ++ * tsx_enable() will change the state of the RTM and HLE CPUID ++ * bits. Force them here since they are now expected to be set. + */ + setup_force_cpu_cap(X86_FEATURE_RTM); ++ setup_force_cpu_cap(X86_FEATURE_HLE); + } + } +-- +2.20.1 + -- 2.47.3