From 08d64e0db02e826b063d2b0d8b84f1cb1f7306c9 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 18 Jul 2017 01:55:38 -0300 Subject: [PATCH] target/sparc: optimize gen_op_mulscc() using deposit op MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20170718045540.16322-9-f4bug@amsat.org> Signed-off-by: Richard Henderson --- target/sparc/translate.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 67a83b77cca..d13173275f0 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -632,11 +632,8 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) // b2 = T0 & 1; // env->y = (b2 << 31) | (env->y >> 1); - tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1); - tcg_gen_shli_tl(r_temp, r_temp, 31); tcg_gen_extract_tl(t0, cpu_y, 1, 31); - tcg_gen_or_tl(t0, t0, r_temp); - tcg_gen_andi_tl(cpu_y, t0, 0xffffffff); + tcg_gen_deposit_tl(cpu_y, t0, cpu_cc_src, 31, 1); // b1 = N ^ V; gen_mov_reg_N(t0, cpu_psr); -- 2.39.5