From 0caafbde07ec36bc34b4746017a6c0ce4d22ab0b Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 23 Feb 2017 18:30:44 +0100 Subject: [PATCH] arm64: tegra: Add ethernet support for Tegra186 The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC ethernet QOS IP block, which supports 10, 100 and 1000 Mbps data transfer rates. Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 31 ++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index d6955bb46ae0e..3ea5e6369bc36 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -27,6 +27,37 @@ gpio-controller; }; + ethernet@2490000 { + compatible = "nvidia,tegra186-eqos", + "snps,dwc-qos-ethernet-4.10"; + reg = <0x0 0x02490000 0x0 0x10000>; + interrupts = , /* common */ + , /* power */ + , /* rx0 */ + , /* tx0 */ + , /* rx1 */ + , /* tx1 */ + , /* rx2 */ + , /* tx2 */ + , /* rx3 */ + ; /* tx3 */ + clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, + <&bpmp TEGRA186_CLK_EQOS_AXI>, + <&bpmp TEGRA186_CLK_EQOS_RX>, + <&bpmp TEGRA186_CLK_EQOS_TX>, + <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; + clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; + resets = <&bpmp TEGRA186_RESET_EQOS>; + reset-names = "eqos"; + status = "disabled"; + + snps,write-requests = <1>; + snps,read-requests = <3>; + snps,burst-map = <0x7>; + snps,txpbl = <32>; + snps,rxpbl = <8>; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; reg = <0x0 0x03100000 0x0 0x40>; -- 2.39.5