From 0cba6abbba5c0bd5c80e652c35d0bd74e644a49e Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Thu, 29 Sep 2016 11:44:41 -0700 Subject: [PATCH] ARM64: zynqmp: Adjust to new SMC interface to get silicon version The new FW interface returns the IDCODE and version register, leaving extracting bitfields to the caller. Cc: Michal Simek Cc: Siva Durga Prasad Paladugu Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 11 +++++++++++ include/zynqmppl.h | 6 ++++++ 2 files changed, 17 insertions(+) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index ba4dfbb476..b0acaa5b77 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -86,6 +86,17 @@ static int chip_id(void) smc_call(®s); + /* + * SMC returns: + * regs[0][31:0] = status of the operation + * regs[0][63:32] = CSU.IDCODE register + * regs[1][31:0] = CSU.version register + */ + regs.regs[0] = upper_32_bits(regs.regs[0]); + regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | + ZYNQMP_CSU_IDCODE_SVD_MASK; + regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT; + return regs.regs[0]; } diff --git a/include/zynqmppl.h b/include/zynqmppl.h index 542ace9a03..fb5200ec84 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -16,6 +16,12 @@ #define ZYNQMP_FPGA_OP_LOAD (1 << 1) #define ZYNQMP_FPGA_OP_DONE (1 << 2) +#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15 +#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \ + ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) +#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 +#define ZYNQMP_CSU_IDCODE_SVD_MASK (0xe << ZYNQMP_CSU_IDCODE_SVD_SHIFT) + extern struct xilinx_fpga_op zynqmp_op; #define XILINX_ZYNQMP_DESC \ -- 2.39.5