From 0e2715176df3787d1470d7b9bde26b1b5e16e1e2 Mon Sep 17 00:00:00 2001 From: Ju-Zhe Zhong Date: Tue, 14 Mar 2023 10:23:31 +0800 Subject: [PATCH] RISC-V: Fix wrong RTL pattern for ternary instructions. We've wrong RTL pattern cause unexpected optimizaion result. Give a example is vnmsub.vx pattern, the operation of vnmsub.vx list below: vnmsub.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vd[i]) + vs2[i] But our RTL pattern write as (x[rs1] * vd[i]) - vs2[i], and the GCC try to simplify when x[rs1] is constant 1, and then become a vd[i] - vs[i] instruction. We also revise all ternary instructions to make sure the RTL has right semantic: And it's the mapping list between instruction and RTL pattern: interger: vnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] (minus op3 (mult op1 op2)) vnmsac.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vs2[i]) + vd[i] (minus op3 (mult op1 op2)) floating-point: vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] (plus (mult (op1 op2)) op3) vfmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] (plus (mult (op1 op2)) op3) vfnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i] (minus (neg (mult (op1 op2))) op3)) vfnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i] (minus (neg (mult (op1 op2)) op3)) vfmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i] (minus (mult (op1 op2)) op3) vfmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i] (minus (mult (op1 op2)) op3) vfnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] (plus (neg:(mult (op1 op2))) op3) vfnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i] (plus (neg:(mult (op1 op2))) op3) gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: Fix ternary bug. * config/riscv/vector-iterators.md (nmsac): Ditto. (nmsub): Ditto. (msac): Ditto. (msub): Ditto. (nmadd): Ditto. (nmacc): Ditto. * config/riscv/vector.md (@pred_mul_): Ditto. (@pred_mul_plus): Ditto. (*pred_madd): Ditto. (*pred_macc): Ditto. (*pred_mul_plus): Ditto. (@pred_mul_plus_scalar): Ditto. (*pred_madd_scalar): Ditto. (*pred_macc_scalar): Ditto. (*pred_mul_plus_scalar): Ditto. (*pred_madd_extended_scalar): Ditto. (*pred_macc_extended_scalar): Ditto. (*pred_mul_plus_extended_scalar): Ditto. (@pred_minus_mul): Ditto. (*pred_): Ditto. (*pred_nmsub): Ditto. (*pred_): Ditto. (*pred_nmsac): Ditto. (*pred_mul_): Ditto. (*pred_minus_mul): Ditto. (@pred_mul__scalar): Ditto. (@pred_minus_mul_scalar): Ditto. (*pred__scalar): Ditto. (*pred_nmsub_scalar): Ditto. (*pred__scalar): Ditto. (*pred_nmsac_scalar): Ditto. (*pred_mul__scalar): Ditto. (*pred_minus_mul_scalar): Ditto. (*pred__extended_scalar): Ditto. (*pred_nmsub_extended_scalar): Ditto. (*pred__extended_scalar): Ditto. (*pred_nmsac_extended_scalar): Ditto. (*pred_mul__extended_scalar): Ditto. (*pred_minus_mul_extended_scalar): Ditto. (*pred_): Ditto. (*pred_): Ditto. (*pred__scalar): Ditto. (*pred__scalar): Ditto. (@pred_neg_mul_): Ditto. (@pred_mul_neg_): Ditto. (*pred_): Ditto. (*pred_): Ditto. (*pred_): Ditto. (*pred_): Ditto. (*pred_neg_mul_): Ditto. (*pred_mul_neg_): Ditto. (@pred_neg_mul__scalar): Ditto. (@pred_mul_neg__scalar): Ditto. (*pred__scalar): Ditto. (*pred__scalar): Ditto. (*pred__scalar): Ditto. (*pred__scalar): Ditto. (*pred_neg_mul__scalar): Ditto. (*pred_mul_neg__scalar): Ditto. (@pred_widen_neg_mul_): Ditto. (@pred_widen_mul_neg_): Ditto. (@pred_widen_neg_mul__scalar): Ditto. (@pred_widen_mul_neg__scalar): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/bug-3.c: New test. * gcc.target/riscv/rvv/base/bug-4.c: New test. * gcc.target/riscv/rvv/base/bug-5.c: New test. Signed-off-by: Ju-Zhe Zhong Co-authored-by: kito-cheng --- .../riscv/riscv-vector-builtins-bases.cc | 80 +- gcc/config/riscv/vector-iterators.md | 8 +- gcc/config/riscv/vector.md | 713 ++++++++++++++---- .../gcc.target/riscv/rvv/base/bug-3.c | 22 + .../gcc.target/riscv/rvv/base/bug-4.c | 22 + .../gcc.target/riscv/rvv/base/bug-5.c | 22 + 6 files changed, 671 insertions(+), 196 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 3f0f809c7143..839eb66efb2c 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -627,12 +627,11 @@ public: rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_vx) - return e.use_ternop_insn (true, - code_for_pred_mul_scalar (PLUS, - e.vector_mode ())); + return e.use_ternop_insn (true, code_for_pred_mul_plus_scalar ( + e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (true, - code_for_pred_mul (PLUS, e.vector_mode ())); + code_for_pred_mul_plus (e.vector_mode ())); gcc_unreachable (); } }; @@ -645,12 +644,11 @@ public: rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_vx) - return e.use_ternop_insn (true, - code_for_pred_mul_scalar (MINUS, - e.vector_mode ())); + return e.use_ternop_insn (true, code_for_pred_minus_mul_scalar ( + e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (true, - code_for_pred_mul (MINUS, e.vector_mode ())); + code_for_pred_minus_mul (e.vector_mode ())); gcc_unreachable (); } }; @@ -663,12 +661,11 @@ public: rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_vx) - return e.use_ternop_insn (false, - code_for_pred_mul_scalar (PLUS, - e.vector_mode ())); + return e.use_ternop_insn (false, code_for_pred_mul_plus_scalar ( + e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (false, - code_for_pred_mul (PLUS, e.vector_mode ())); + code_for_pred_mul_plus (e.vector_mode ())); gcc_unreachable (); } }; @@ -681,17 +678,15 @@ public: rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_vx) - return e.use_ternop_insn (false, - code_for_pred_mul_scalar (MINUS, - e.vector_mode ())); + return e.use_ternop_insn (false, code_for_pred_minus_mul_scalar ( + e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (false, - code_for_pred_mul (MINUS, e.vector_mode ())); + code_for_pred_minus_mul (e.vector_mode ())); gcc_unreachable (); } }; - /* Implements vwmacc. */ class vwmacc : public function_base { @@ -973,12 +968,11 @@ public: rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_vf) - return e.use_ternop_insn (true, - code_for_pred_mul_scalar (MINUS, - e.vector_mode ())); + return e.use_ternop_insn ( + true, code_for_pred_mul_neg_scalar (PLUS, e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (true, - code_for_pred_mul (MINUS, e.vector_mode ())); + code_for_pred_mul_neg (PLUS, e.vector_mode ())); gcc_unreachable (); } }; @@ -1009,12 +1003,11 @@ public: rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_vf) - return e.use_ternop_insn (false, - code_for_pred_mul_scalar (MINUS, - e.vector_mode ())); + return e.use_ternop_insn ( + false, code_for_pred_mul_neg_scalar (PLUS, e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (false, - code_for_pred_mul (MINUS, e.vector_mode ())); + code_for_pred_mul_neg (PLUS, e.vector_mode ())); gcc_unreachable (); } }; @@ -1028,10 +1021,10 @@ public: { if (e.op_info->op == OP_TYPE_vf) return e.use_ternop_insn ( - true, code_for_pred_neg_mul_scalar (PLUS, e.vector_mode ())); + true, code_for_pred_mul_neg_scalar (MINUS, e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (true, - code_for_pred_neg_mul (PLUS, e.vector_mode ())); + code_for_pred_mul_neg (MINUS, e.vector_mode ())); gcc_unreachable (); } }; @@ -1044,11 +1037,12 @@ public: rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_vf) - return e.use_ternop_insn ( - true, code_for_pred_neg_mul_scalar (MINUS, e.vector_mode ())); + return e.use_ternop_insn (true, + code_for_pred_mul_scalar (MINUS, + e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) - return e.use_ternop_insn (true, code_for_pred_neg_mul (MINUS, - e.vector_mode ())); + return e.use_ternop_insn (true, + code_for_pred_mul (MINUS, e.vector_mode ())); gcc_unreachable (); } }; @@ -1062,10 +1056,10 @@ public: { if (e.op_info->op == OP_TYPE_vf) return e.use_ternop_insn ( - false, code_for_pred_neg_mul_scalar (PLUS, e.vector_mode ())); + false, code_for_pred_mul_neg_scalar (MINUS, e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (false, - code_for_pred_neg_mul (PLUS, e.vector_mode ())); + code_for_pred_mul_neg (MINUS, e.vector_mode ())); gcc_unreachable (); } }; @@ -1078,12 +1072,12 @@ public: rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_vf) - return e.use_ternop_insn ( - false, code_for_pred_neg_mul_scalar (MINUS, e.vector_mode ())); + return e.use_ternop_insn (false, + code_for_pred_mul_scalar (MINUS, + e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (false, - code_for_pred_neg_mul (MINUS, - e.vector_mode ())); + code_for_pred_mul (MINUS, e.vector_mode ())); gcc_unreachable (); } }; @@ -1114,10 +1108,10 @@ public: { if (e.op_info->op == OP_TYPE_vf) return e.use_widen_ternop_insn ( - code_for_pred_widen_neg_mul_scalar (PLUS, e.vector_mode ())); + code_for_pred_widen_mul_neg_scalar (MINUS, e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_widen_ternop_insn ( - code_for_pred_widen_neg_mul (PLUS, e.vector_mode ())); + code_for_pred_widen_mul_neg (MINUS, e.vector_mode ())); gcc_unreachable (); } }; @@ -1131,10 +1125,10 @@ public: { if (e.op_info->op == OP_TYPE_vf) return e.use_widen_ternop_insn ( - code_for_pred_widen_neg_mul_scalar (MINUS, e.vector_mode ())); + code_for_pred_widen_mul_scalar (MINUS, e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_widen_ternop_insn ( - code_for_pred_widen_neg_mul (MINUS, e.vector_mode ())); + code_for_pred_widen_mul (MINUS, e.vector_mode ())); gcc_unreachable (); } }; @@ -1148,10 +1142,10 @@ public: { if (e.op_info->op == OP_TYPE_vf) return e.use_widen_ternop_insn ( - code_for_pred_widen_mul_scalar (MINUS, e.vector_mode ())); + code_for_pred_widen_mul_neg_scalar (PLUS, e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_widen_ternop_insn ( - code_for_pred_widen_mul (MINUS, e.vector_mode ())); + code_for_pred_widen_mul_neg (PLUS, e.vector_mode ())); gcc_unreachable (); } }; diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 266563a3aa05..34e486e48ca3 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -839,10 +839,10 @@ (define_code_iterator any_widen_binop [plus minus mult]) (define_code_iterator plus_minus [plus minus]) -(define_code_attr macc_nmsac [(plus "macc") (minus "nmsac")]) -(define_code_attr madd_nmsub [(plus "madd") (minus "nmsub")]) -(define_code_attr nmacc_msac [(plus "nmacc") (minus "msac")]) -(define_code_attr nmadd_msub [(plus "nmadd") (minus "msub")]) +(define_code_attr madd_msub [(plus "madd") (minus "msub")]) +(define_code_attr macc_msac [(plus "macc") (minus "msac")]) +(define_code_attr nmsub_nmadd [(plus "nmsub") (minus "nmadd")]) +(define_code_attr nmsac_nmacc [(plus "nmsac") (minus "nmacc")]) (define_code_iterator and_ior [and ior]) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 37a539b48526..a6ea86844eaa 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -4148,7 +4148,7 @@ ;; - 11.13 Vector Single-Width Integer Multiply-Add Instructions ;; ------------------------------------------------------------------------------- -(define_expand "@pred_mul_" +(define_expand "@pred_mul_plus" [(set (match_operand:VI 0 "register_operand") (if_then_else:VI (unspec: @@ -4159,7 +4159,7 @@ (match_operand 9 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI + (plus:VI (mult:VI (match_operand:VI 2 "register_operand") (match_operand:VI 3 "register_operand")) @@ -4173,7 +4173,7 @@ std::swap (operands[2], operands[3]); }) -(define_insn "*pred_" +(define_insn "*pred_madd" [(set (match_operand:VI 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VI (unspec: @@ -4184,7 +4184,7 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI + (plus:VI (mult:VI (match_operand:VI 2 "register_operand" " 0, 0, vr") (match_operand:VI 3 "register_operand" " vr, vr, vr")) @@ -4192,9 +4192,9 @@ (match_dup 2)))] "TARGET_VECTOR" "@ - v.vv\t%0,%3,%4%p1 - v.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%2\;v.vv\t%0,%3,%4%p1" + vmadd.vv\t%0,%3,%4%p1 + vmadd.vv\t%0,%3,%4%p1 + vmv.v.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -4203,7 +4203,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn "*pred_" +(define_insn "*pred_macc" [(set (match_operand:VI 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VI (unspec: @@ -4214,7 +4214,7 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI + (plus:VI (mult:VI (match_operand:VI 2 "register_operand" " vr, vr, vr") (match_operand:VI 3 "register_operand" " vr, vr, vr")) @@ -4222,9 +4222,9 @@ (match_dup 4)))] "TARGET_VECTOR" "@ - v.vv\t%0,%2,%3%p1 - v.vv\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;v.vv\t%0,%2,%3%p1" + vmacc.vv\t%0,%2,%3%p1 + vmacc.vv\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -4233,7 +4233,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn_and_rewrite "*pred_mul_" +(define_insn_and_rewrite "*pred_mul_plus" [(set (match_operand:VI 0 "register_operand" "=&vr,?&vr, ?&vr, ?&vr, ?&vr") (if_then_else:VI (unspec: @@ -4244,7 +4244,7 @@ (match_operand 9 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI + (plus:VI (mult:VI (match_operand:VI 2 "register_operand" " vr, vr, vi, vr, vr") (match_operand:VI 3 "register_operand" " vr, vr, vr, vi, vr")) @@ -4255,7 +4255,7 @@ && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" "@ - vmv.v.v\t%0,%4\;v.vv\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1 # # # @@ -4284,7 +4284,7 @@ [(set_attr "type" "vimuladd") (set_attr "mode" "")]) -(define_expand "@pred_mul__scalar" +(define_expand "@pred_mul_plus_scalar" [(set (match_operand:VI_QHS 0 "register_operand") (if_then_else:VI_QHS (unspec: @@ -4295,7 +4295,7 @@ (match_operand 9 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI_QHS + (plus:VI_QHS (mult:VI_QHS (vec_duplicate:VI_QHS (match_operand: 2 "reg_or_int_operand")) @@ -4307,7 +4307,7 @@ operands[2] = force_reg (mode, operands[2]); }) -(define_insn "*pred__scalar" +(define_insn "*pred_madd_scalar" [(set (match_operand:VI 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VI (unspec: @@ -4318,7 +4318,7 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI + (plus:VI (mult:VI (vec_duplicate:VI (match_operand: 2 "register_operand" " r, r, vr")) @@ -4327,9 +4327,9 @@ (match_dup 3)))] "TARGET_VECTOR" "@ - v.vx\t%0,%2,%4%p1 - v.vx\t%0,%2,%4%p1 - vmv.v.v\t%0,%2\;v.vx\t%0,%2,%4%p1" + vmadd.vx\t%0,%2,%4%p1 + vmadd.vx\t%0,%2,%4%p1 + vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -4338,7 +4338,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn "*pred__scalar" +(define_insn "*pred_macc_scalar" [(set (match_operand:VI 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VI (unspec: @@ -4349,7 +4349,7 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI + (plus:VI (mult:VI (vec_duplicate:VI (match_operand: 2 "register_operand" " r, r, vr")) @@ -4358,9 +4358,9 @@ (match_dup 4)))] "TARGET_VECTOR" "@ - v.vx\t%0,%2,%3%p1 - v.vx\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;v.vx\t%0,%2,%3%p1" + vmacc.vx\t%0,%2,%3%p1 + vmacc.vx\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -4369,7 +4369,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn_and_rewrite "*pred_mul__scalar" +(define_insn_and_rewrite "*pred_mul_plus_scalar" [(set (match_operand:VI 0 "register_operand" "=&vr, ?&vr, ?&vr, ?&vr") (if_then_else:VI (unspec: @@ -4380,7 +4380,7 @@ (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI + (plus:VI (mult:VI (vec_duplicate:VI (match_operand: 2 "register_operand" " r, r, r, r")) @@ -4391,7 +4391,7 @@ && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" "@ - vmv.v.v\t%0,%4\;v.vx\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1 # # #" @@ -4416,7 +4416,7 @@ [(set_attr "type" "vimuladd") (set_attr "mode" "")]) -(define_expand "@pred_mul__scalar" +(define_expand "@pred_mul_plus_scalar" [(set (match_operand:VI_D 0 "register_operand") (if_then_else:VI_D (unspec: @@ -4427,7 +4427,7 @@ (match_operand 9 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI_D + (plus:VI_D (mult:VI_D (vec_duplicate:VI_D (match_operand: 2 "reg_or_int_operand")) @@ -4444,14 +4444,14 @@ mode, false, [] (rtx *operands, rtx boardcast_scalar) { - emit_insn (gen_pred_mul_ (operands[0], operands[1], + emit_insn (gen_pred_mul_plus (operands[0], operands[1], boardcast_scalar, operands[3], operands[4], operands[5], operands[6], operands[7], operands[8], operands[9])); })) DONE; }) -(define_insn "*pred__extended_scalar" +(define_insn "*pred_madd_extended_scalar" [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VI_D (unspec: @@ -4462,7 +4462,7 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI_D + (plus:VI_D (mult:VI_D (vec_duplicate:VI_D (sign_extend: @@ -4472,9 +4472,9 @@ (match_dup 3)))] "TARGET_VECTOR" "@ - v.vx\t%0,%2,%4%p1 - v.vx\t%0,%2,%4%p1 - vmv.v.v\t%0,%2\;v.vx\t%0,%2,%4%p1" + vmadd.vx\t%0,%2,%4%p1 + vmadd.vx\t%0,%2,%4%p1 + vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -4483,7 +4483,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn "*pred__extended_scalar" +(define_insn "*pred_macc_extended_scalar" [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VI_D (unspec: @@ -4494,7 +4494,7 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI_D + (plus:VI_D (mult:VI_D (vec_duplicate:VI_D (sign_extend: @@ -4504,9 +4504,9 @@ (match_dup 4)))] "TARGET_VECTOR" "@ - v.vx\t%0,%2,%3%p1 - v.vx\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;v.vx\t%0,%2,%3%p1" + vmacc.vx\t%0,%2,%3%p1 + vmacc.vx\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -4515,7 +4515,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn_and_rewrite "*pred_mul__extended_scalar" +(define_insn_and_rewrite "*pred_mul_plus_extended_scalar" [(set (match_operand:VI_D 0 "register_operand" "=&vr, ?&vr, ?&vr, ?&vr") (if_then_else:VI_D (unspec: @@ -4526,7 +4526,7 @@ (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI_D + (plus:VI_D (mult:VI_D (vec_duplicate:VI_D (sign_extend: @@ -4538,7 +4538,422 @@ && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" "@ - vmv.v.v\t%0,%4\;v.vx\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1 + # + # + #" + "&& reload_completed + && !rtx_equal_p (operands[0], operands[5])" + { + if (satisfies_constraint_vi (operands[3])) + { + emit_insn (gen_pred_merge (operands[0], RVV_VUNDEF (mode), + operands[5], operands[3], operands[1], operands[6], + operands[7], operands[9])); + operands[5] = operands[3] = operands[0]; + } + else + { + emit_insn (gen_pred_merge (operands[0], RVV_VUNDEF (mode), + operands[5], operands[4], operands[1], operands[6], + operands[7], operands[9])); + operands[5] = operands[4] = operands[0]; + } + } + [(set_attr "type" "vimuladd") + (set_attr "mode" "")]) + +(define_expand "@pred_minus_mul" + [(set (match_operand:VI 0 "register_operand") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand") + (match_operand 6 "vector_length_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (match_operand 9 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:VI + (match_operand:VI 4 "register_operand") + (mult:VI + (match_operand:VI 2 "register_operand") + (match_operand:VI 3 "register_operand"))) + (match_operand:VI 5 "register_operand")))] + "TARGET_VECTOR" +{ + /* Swap the multiplication operands if the fallback value is the + second of the two. */ + if (rtx_equal_p (operands[3], operands[5])) + std::swap (operands[2], operands[3]); +}) + +(define_insn "*pred_nmsub" + [(set (match_operand:VI 0 "register_operand" "=vd, vr, ?&vr") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i") + (match_operand 7 "const_int_operand" " i, i, i") + (match_operand 8 "const_int_operand" " i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:VI + (match_operand:VI 4 "register_operand" " vr, vr, vr") + (mult:VI + (match_operand:VI 2 "register_operand" " 0, 0, vr") + (match_operand:VI 3 "register_operand" " vr, vr, vr"))) + (match_dup 2)))] + "TARGET_VECTOR" + "@ + vnmsub.vv\t%0,%3,%4%p1 + vnmsub.vv\t%0,%3,%4%p1 + vmv.v.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "4") + (set_attr "vl_op_idx" "5") + (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) + (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + +(define_insn "*pred_nmsac" + [(set (match_operand:VI 0 "register_operand" "=vd, vr, ?&vr") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i") + (match_operand 7 "const_int_operand" " i, i, i") + (match_operand 8 "const_int_operand" " i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:VI + (match_operand:VI 4 "register_operand" " 0, 0, vr") + (mult:VI + (match_operand:VI 2 "register_operand" " vr, vr, vr") + (match_operand:VI 3 "register_operand" " vr, vr, vr"))) + (match_dup 4)))] + "TARGET_VECTOR" + "@ + vnmsac.vv\t%0,%2,%3%p1 + vnmsac.vv\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "2") + (set_attr "vl_op_idx" "5") + (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) + (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + +(define_insn_and_rewrite "*pred_minus_mul" + [(set (match_operand:VI 0 "register_operand" "=&vr,?&vr, ?&vr, ?&vr, ?&vr") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:VI + (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr, vr") + (mult:VI + (match_operand:VI 2 "register_operand" " vr, vr, vi, vr, vr") + (match_operand:VI 3 "register_operand" " vr, vr, vr, vi, vr"))) + (match_operand:VI 5 "register_operand" " 0, vr, vr, vr, vr")))] + "TARGET_VECTOR + && !rtx_equal_p (operands[2], operands[5]) + && !rtx_equal_p (operands[3], operands[5]) + && !rtx_equal_p (operands[4], operands[5])" + "@ + vmv.v.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1 + # + # + # + #" + "&& reload_completed + && !rtx_equal_p (operands[0], operands[5])" + { + if (satisfies_constraint_vi (operands[3])) + std::swap (operands[2], operands[3]); + + if (satisfies_constraint_vi (operands[2])) + { + emit_insn (gen_pred_merge (operands[0], RVV_VUNDEF (mode), + operands[5], operands[2], operands[1], operands[6], + operands[7], operands[9])); + operands[5] = operands[2] = operands[0]; + } + else + { + emit_insn (gen_pred_merge (operands[0], RVV_VUNDEF (mode), + operands[5], operands[4], operands[1], operands[6], + operands[7], operands[9])); + operands[5] = operands[4] = operands[0]; + } + } + [(set_attr "type" "vimuladd") + (set_attr "mode" "")]) + +(define_expand "@pred_minus_mul_scalar" + [(set (match_operand:VI_QHS 0 "register_operand") + (if_then_else:VI_QHS + (unspec: + [(match_operand: 1 "vector_mask_operand") + (match_operand 6 "vector_length_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (match_operand 9 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:VI_QHS + (match_operand:VI_QHS 4 "register_operand") + (mult:VI_QHS + (vec_duplicate:VI_QHS + (match_operand: 2 "reg_or_int_operand")) + (match_operand:VI_QHS 3 "register_operand"))) + (match_operand:VI_QHS 5 "register_operand")))] + "TARGET_VECTOR" +{ + operands[2] = force_reg (mode, operands[2]); +}) + +(define_insn "*pred_nmsub_scalar" + [(set (match_operand:VI 0 "register_operand" "=vd, vr, ?&vr") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i") + (match_operand 7 "const_int_operand" " i, i, i") + (match_operand 8 "const_int_operand" " i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:VI + (match_operand:VI 4 "register_operand" " vr, vr, vr") + (mult:VI + (vec_duplicate:VI + (match_operand: 2 "register_operand" " r, r, vr")) + (match_operand:VI 3 "register_operand" " 0, 0, vr"))) + (match_dup 3)))] + "TARGET_VECTOR" + "@ + vnmsub.vx\t%0,%2,%4%p1 + vnmsub.vx\t%0,%2,%4%p1 + vmv.v.v\t%0,%2\;vnmsub.vx\t%0,%2,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "4") + (set_attr "vl_op_idx" "5") + (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) + (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + +(define_insn "*pred_nmsac_scalar" + [(set (match_operand:VI 0 "register_operand" "=vd, vr, ?&vr") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i") + (match_operand 7 "const_int_operand" " i, i, i") + (match_operand 8 "const_int_operand" " i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:VI + (match_operand:VI 4 "register_operand" " 0, 0, vr") + (mult:VI + (vec_duplicate:VI + (match_operand: 2 "register_operand" " r, r, vr")) + (match_operand:VI 3 "register_operand" " vr, vr, vr"))) + (match_dup 4)))] + "TARGET_VECTOR" + "@ + vnmsac.vx\t%0,%2,%3%p1 + vnmsac.vx\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "2") + (set_attr "vl_op_idx" "5") + (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) + (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + +(define_insn_and_rewrite "*pred_minus_mul_scalar" + [(set (match_operand:VI 0 "register_operand" "=&vr, ?&vr, ?&vr, ?&vr") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:VI + (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr") + (mult:VI + (vec_duplicate:VI + (match_operand: 2 "register_operand" " r, r, r, r")) + (match_operand:VI 3 "register_operand" " vr, vr, vi, vr"))) + (match_operand:VI 5 "register_operand" " 0, vr, vr, vr")))] + "TARGET_VECTOR + && !rtx_equal_p (operands[3], operands[5]) + && !rtx_equal_p (operands[4], operands[5])" + "@ + vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1 + # + # + #" + "&& reload_completed + && !rtx_equal_p (operands[0], operands[5])" + { + if (satisfies_constraint_vi (operands[3])) + { + emit_insn (gen_pred_merge (operands[0], RVV_VUNDEF (mode), + operands[5], operands[3], operands[1], operands[6], + operands[7], operands[9])); + operands[5] = operands[3] = operands[0]; + } + else + { + emit_insn (gen_pred_merge (operands[0], RVV_VUNDEF (mode), + operands[5], operands[4], operands[1], operands[6], + operands[7], operands[9])); + operands[5] = operands[4] = operands[0]; + } + } + [(set_attr "type" "vimuladd") + (set_attr "mode" "")]) + +(define_expand "@pred_minus_mul_scalar" + [(set (match_operand:VI_D 0 "register_operand") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand") + (match_operand 6 "vector_length_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (match_operand 9 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:VI_D + (match_operand:VI_D 4 "register_operand") + (mult:VI_D + (vec_duplicate:VI_D + (match_operand: 2 "reg_or_int_operand")) + (match_operand:VI_D 3 "register_operand"))) + (match_operand:VI_D 5 "register_operand")))] + "TARGET_VECTOR" +{ + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[2], + /* vl */operands[6], + mode, + mode, + false, + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_minus_mul (operands[0], operands[1], + boardcast_scalar, operands[3], operands[4], operands[5], + operands[6], operands[7], operands[8], operands[9])); + })) + DONE; +}) + +(define_insn "*pred_nmsub_extended_scalar" + [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, ?&vr") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i") + (match_operand 7 "const_int_operand" " i, i, i") + (match_operand 8 "const_int_operand" " i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:VI_D + (match_operand:VI_D 4 "register_operand" " vr, vr, vr") + (mult:VI_D + (vec_duplicate:VI_D + (sign_extend: + (match_operand: 2 "register_operand" " r, r, vr"))) + (match_operand:VI_D 3 "register_operand" " 0, 0, vr"))) + (match_dup 3)))] + "TARGET_VECTOR" + "@ + vnmsub.vx\t%0,%2,%4%p1 + vnmsub.vx\t%0,%2,%4%p1 + vmv.v.v\t%0,%2\;vnmsub.vx\t%0,%2,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "4") + (set_attr "vl_op_idx" "5") + (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) + (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + +(define_insn "*pred_nmsac_extended_scalar" + [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, ?&vr") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i") + (match_operand 7 "const_int_operand" " i, i, i") + (match_operand 8 "const_int_operand" " i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:VI_D + (match_operand:VI_D 4 "register_operand" " 0, 0, vr") + (mult:VI_D + (vec_duplicate:VI_D + (sign_extend: + (match_operand: 2 "register_operand" " r, r, vr"))) + (match_operand:VI_D 3 "register_operand" " vr, vr, vr"))) + (match_dup 4)))] + "TARGET_VECTOR" + "@ + vnmsac.vx\t%0,%2,%3%p1 + vnmsac.vx\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "2") + (set_attr "vl_op_idx" "5") + (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) + (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + +(define_insn_and_rewrite "*pred_minus_mul_extended_scalar" + [(set (match_operand:VI_D 0 "register_operand" "=&vr, ?&vr, ?&vr, ?&vr") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (minus:VI_D + (match_operand:VI_D 4 "vector_arith_operand" " vr, vr, vr, vr") + (mult:VI_D + (vec_duplicate:VI_D + (sign_extend: + (match_operand: 2 "register_operand" " r, r, r, r"))) + (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))) + (match_operand:VI_D 5 "register_operand" " 0, vr, vr, vr")))] + "TARGET_VECTOR + && !rtx_equal_p (operands[3], operands[5]) + && !rtx_equal_p (operands[4], operands[5])" + "@ + vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1 # # #" @@ -5046,7 +5461,7 @@ std::swap (operands[2], operands[3]); }) -(define_insn "*pred_" +(define_insn "*pred_" [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VF (unspec: @@ -5065,9 +5480,9 @@ (match_dup 2)))] "TARGET_VECTOR" "@ - vf.vv\t%0,%3,%4%p1 - vf.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1" + vf.vv\t%0,%3,%4%p1 + vf.vv\t%0,%3,%4%p1 + vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5076,7 +5491,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn "*pred_" +(define_insn "*pred_" [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VF (unspec: @@ -5095,9 +5510,9 @@ (match_dup 4)))] "TARGET_VECTOR" "@ - vf.vv\t%0,%2,%3%p1 - vf.vv\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1" + vf.vv\t%0,%2,%3%p1 + vf.vv\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -5128,7 +5543,7 @@ && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" "@ - vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1 #" "&& reload_completed && !rtx_equal_p (operands[0], operands[5])" @@ -5162,7 +5577,7 @@ "TARGET_VECTOR" {}) -(define_insn "*pred__scalar" +(define_insn "*pred__scalar" [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VF (unspec: @@ -5182,9 +5597,9 @@ (match_dup 3)))] "TARGET_VECTOR" "@ - vf.vf\t%0,%2,%4%p1 - vf.vf\t%0,%2,%4%p1 - vmv.v.v\t%0,%2\;vf.vf\t%0,%2,%4%p1" + vf.vf\t%0,%2,%4%p1 + vf.vf\t%0,%2,%4%p1 + vmv.v.v\t%0,%2\;vf.vf\t%0,%2,%4%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5193,7 +5608,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn "*pred__scalar" +(define_insn "*pred__scalar" [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VF (unspec: @@ -5213,9 +5628,9 @@ (match_dup 4)))] "TARGET_VECTOR" "@ - vf.vf\t%0,%2,%3%p1 - vf.vf\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1" + vf.vf\t%0,%2,%3%p1 + vf.vf\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -5246,7 +5661,7 @@ && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" "@ - vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1 #" "&& reload_completed && !rtx_equal_p (operands[0], operands[5])" @@ -5259,7 +5674,7 @@ [(set_attr "type" "vfmuladd") (set_attr "mode" "")]) -(define_expand "@pred_neg_mul_" +(define_expand "@pred_mul_neg_" [(set (match_operand:VF 0 "register_operand") (if_then_else:VF (unspec: @@ -5270,12 +5685,12 @@ (match_operand 9 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VF - (plus_minus:VF - (match_operand:VF 4 "register_operand") + (plus_minus:VF + (neg:VF (mult:VF (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand")))) + (match_operand:VF 3 "register_operand"))) + (match_operand:VF 4 "register_operand")) (match_operand:VF 5 "register_operand")))] "TARGET_VECTOR" { @@ -5285,7 +5700,7 @@ std::swap (operands[2], operands[3]); }) -(define_insn "*pred_" +(define_insn "*pred_" [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VF (unspec: @@ -5296,18 +5711,18 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VF - (plus_minus:VF - (match_operand:VF 4 "register_operand" " vr, vr, vr") + (plus_minus:VF + (neg:VF (mult:VF (match_operand:VF 2 "register_operand" " 0, 0, vr") - (match_operand:VF 3 "register_operand" " vr, vr, vr")))) + (match_operand:VF 3 "register_operand" " vr, vr, vr"))) + (match_operand:VF 4 "register_operand" " vr, vr, vr")) (match_dup 2)))] "TARGET_VECTOR" "@ - vf.vv\t%0,%3,%4%p1 - vf.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1" + vf.vv\t%0,%3,%4%p1 + vf.vv\t%0,%3,%4%p1 + vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5316,7 +5731,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn "*pred_" +(define_insn "*pred_" [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VF (unspec: @@ -5327,18 +5742,18 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VF - (plus_minus:VF - (match_operand:VF 4 "register_operand" " 0, 0, vr") + (plus_minus:VF + (neg:VF (mult:VF (match_operand:VF 2 "register_operand" " vr, vr, vr") - (match_operand:VF 3 "register_operand" " vr, vr, vr")))) + (match_operand:VF 3 "register_operand" " vr, vr, vr"))) + (match_operand:VF 4 "register_operand" " 0, 0, vr")) (match_dup 4)))] "TARGET_VECTOR" "@ - vf.vv\t%0,%2,%3%p1 - vf.vv\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1" + vf.vv\t%0,%2,%3%p1 + vf.vv\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -5347,7 +5762,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn_and_rewrite "*pred_neg_mul_" +(define_insn_and_rewrite "*pred_mul_neg_" [(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr") (if_then_else:VF (unspec: @@ -5358,19 +5773,19 @@ (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VF - (plus_minus:VF - (match_operand:VF 4 "vector_arith_operand" " vr, vr") + (plus_minus:VF + (neg:VF (mult:VF - (match_operand:VF 2 "register_operand" " vr, vr") - (match_operand:VF 3 "register_operand" " vr, vr")))) + (match_operand:VF 2 "register_operand" " vr, vr") + (match_operand:VF 3 "register_operand" " vr, vr"))) + (match_operand:VF 4 "vector_arith_operand" " vr, vr")) (match_operand:VF 5 "register_operand" " 0, vr")))] "TARGET_VECTOR && !rtx_equal_p (operands[2], operands[5]) && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" "@ - vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1 #" "&& reload_completed && !rtx_equal_p (operands[0], operands[5])" @@ -5383,7 +5798,7 @@ [(set_attr "type" "vfmuladd") (set_attr "mode" "")]) -(define_expand "@pred_neg_mul__scalar" +(define_expand "@pred_mul_neg__scalar" [(set (match_operand:VF 0 "register_operand") (if_then_else:VF (unspec: @@ -5394,41 +5809,41 @@ (match_operand 9 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VF - (plus_minus:VF - (match_operand:VF 4 "register_operand") + (plus_minus:VF + (neg:VF (mult:VF (vec_duplicate:VF (match_operand: 2 "register_operand")) - (match_operand:VF 3 "register_operand")))) + (match_operand:VF 3 "register_operand"))) + (match_operand:VF 4 "register_operand")) (match_operand:VF 5 "register_operand")))] "TARGET_VECTOR" {}) -(define_insn "*pred__scalar" - [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") +(define_insn "*pred__scalar" + [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VF (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i") - (match_operand 7 "const_int_operand" " i, i, i") - (match_operand 8 "const_int_operand" " i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i") + (match_operand 7 "const_int_operand" " i, i, i") + (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VF - (plus_minus:VF - (match_operand:VF 4 "register_operand" " vr, vr, vr") + (plus_minus:VF + (neg:VF (mult:VF (vec_duplicate:VF (match_operand: 2 "register_operand" " f, f, vr")) - (match_operand:VF 3 "register_operand" " 0, 0, vr")))) + (match_operand:VF 3 "register_operand" " 0, 0, vr"))) + (match_operand:VF 4 "register_operand" " vr, vr, vr")) (match_dup 3)))] "TARGET_VECTOR" "@ - vf.vf\t%0,%2,%4%p1 - vf.vf\t%0,%2,%4%p1 - vmv.v.v\t%0,%2\;vf.vf\t%0,%2,%4%p1" + vf.vf\t%0,%2,%4%p1 + vf.vf\t%0,%2,%4%p1 + vmv.v.v\t%0,%2\;vf.vf\t%0,%2,%4%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5437,7 +5852,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn "*pred__scalar" +(define_insn "*pred__scalar" [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VF (unspec: @@ -5448,19 +5863,19 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VF - (plus_minus:VF - (match_operand:VF 4 "register_operand" " 0, 0, vr") + (plus_minus:VF + (neg:VF (mult:VF (vec_duplicate:VF (match_operand: 2 "register_operand" " f, f, vr")) - (match_operand:VF 3 "register_operand" " vr, vr, vr")))) + (match_operand:VF 3 "register_operand" " vr, vr, vr"))) + (match_operand:VF 4 "register_operand" " 0, 0, vr")) (match_dup 4)))] "TARGET_VECTOR" "@ - vf.vf\t%0,%2,%3%p1 - vf.vf\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1" + vf.vf\t%0,%2,%3%p1 + vf.vf\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -5469,30 +5884,30 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn_and_rewrite "*pred_neg_mul__scalar" - [(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr") +(define_insn_and_rewrite "*pred_mul_neg__scalar" + [(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr") (if_then_else:VF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (match_operand 9 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VF - (plus_minus:VF - (match_operand:VF 4 "vector_arith_operand" " vr, vr") + (plus_minus:VF + (neg:VF (mult:VF (vec_duplicate:VF (match_operand: 2 "register_operand" " f, f")) - (match_operand:VF 3 "register_operand" " vr, vr")))) + (match_operand:VF 3 "register_operand" " vr, vr"))) + (match_operand:VF 4 "vector_arith_operand" " vr, vr")) (match_operand:VF 5 "register_operand" " 0, vr")))] "TARGET_VECTOR && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" "@ - vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1 #" "&& reload_completed && !rtx_equal_p (operands[0], operands[5])" @@ -5693,15 +6108,15 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF - (match_operand:VWEXTF 2 "register_operand" " 0") (mult:VWEXTF (float_extend:VWEXTF (match_operand: 3 "register_operand" " vr")) (float_extend:VWEXTF - (match_operand: 4 "register_operand" " vr")))) + (match_operand: 4 "register_operand" " vr"))) + (match_operand:VWEXTF 2 "register_operand" " 0")) (match_dup 2)))] "TARGET_VECTOR" - "vfw.vv\t%0,%3,%4%p1" + "vfw.vv\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "")]) @@ -5717,20 +6132,20 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF - (match_operand:VWEXTF 2 "register_operand" " 0") (mult:VWEXTF (float_extend:VWEXTF (vec_duplicate: (match_operand: 3 "register_operand" " f"))) (float_extend:VWEXTF - (match_operand: 4 "register_operand" " vr")))) + (match_operand: 4 "register_operand" " vr"))) + (match_operand:VWEXTF 2 "register_operand" " 0")) (match_dup 2)))] "TARGET_VECTOR" - "vfw.vf\t%0,%3,%4%p1" + "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "")]) -(define_insn "@pred_widen_neg_mul_" +(define_insn "@pred_widen_mul_neg_" [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") (if_then_else:VWEXTF (unspec: @@ -5741,21 +6156,21 @@ (match_operand 8 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VWEXTF - (plus_minus:VWEXTF - (match_operand:VWEXTF 2 "register_operand" " 0") + (plus_minus:VWEXTF + (neg:VWEXTF (mult:VWEXTF (float_extend:VWEXTF (match_operand: 3 "register_operand" " vr")) (float_extend:VWEXTF - (match_operand: 4 "register_operand" " vr"))))) + (match_operand: 4 "register_operand" " vr")))) + (match_operand:VWEXTF 2 "register_operand" " 0")) (match_dup 2)))] "TARGET_VECTOR" - "vfw.vv\t%0,%3,%4%p1" + "vfw.vv\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "")]) -(define_insn "@pred_widen_neg_mul__scalar" +(define_insn "@pred_widen_mul_neg__scalar" [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") (if_then_else:VWEXTF (unspec: @@ -5766,18 +6181,18 @@ (match_operand 8 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VWEXTF - (plus_minus:VWEXTF - (match_operand:VWEXTF 2 "register_operand" " 0") + (plus_minus:VWEXTF + (neg:VWEXTF (mult:VWEXTF (float_extend:VWEXTF (vec_duplicate: (match_operand: 3 "register_operand" " f"))) (float_extend:VWEXTF - (match_operand: 4 "register_operand" " vr"))))) + (match_operand: 4 "register_operand" " vr")))) + (match_operand:VWEXTF 2 "register_operand" " 0")) (match_dup 2)))] "TARGET_VECTOR" - "vfw.vf\t%0,%3,%4%p1" + "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c new file mode 100644 index 000000000000..2832c9c8e4c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c @@ -0,0 +1,22 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "-O2" } */ + +#include "riscv_vector.h" +#include + +int main() +{ + int32_t a = 1; + int32_t b[1] = {3}; + int32_t c[1] = {10}; + int32_t d[1] = {0}; + vint32m1_t vb = __riscv_vle32_v_i32m1 (b, 1); + vint32m1_t vc = __riscv_vle32_v_i32m1 (c, 1); + vint32m1_t vd = __riscv_vnmsub_vx_i32m1 (vb, a, vc, 1); + __riscv_vse32_v_i32m1 (d, vd, 1); + if (d[0] != 7){ + printf("d[0] should be 7, but got %d\n", d[0]); + __builtin_abort (); + } + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c new file mode 100644 index 000000000000..ab003fdef243 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c @@ -0,0 +1,22 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "-O2" } */ + +#include "riscv_vector.h" +#include + +int main() +{ + float a = 1.0; + float b[1] = {3.0}; + float c[1] = {10.0}; + float d[1] = {0.0}; + vfloat32m1_t vb = __riscv_vle32_v_f32m1 (b, 1); + vfloat32m1_t vc = __riscv_vle32_v_f32m1 (c, 1); + vfloat32m1_t vd = __riscv_vfnmsub_vf_f32m1 (vb, a, vc, 1); + __riscv_vse32_v_f32m1 (d, vd, 1); + if (d[0] != 7.0){ + printf("d[0] should be 7.0, but got %f\n", d[0]); + __builtin_abort (); + } + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c new file mode 100644 index 000000000000..8230695d6620 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c @@ -0,0 +1,22 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-options "-O2" } */ + +#include "riscv_vector.h" +#include + +int main() +{ + float a = 1.0; + float b[1] = {3.0}; + float c[1] = {10.0}; + float d[1] = {0.0}; + vfloat32m1_t vb = __riscv_vle32_v_f32m1 (b, 1); + vfloat32m1_t vc = __riscv_vle32_v_f32m1 (c, 1); + vfloat32m1_t vd = __riscv_vfmsub_vf_f32m1 (vb, a, vc, 1); + __riscv_vse32_v_f32m1 (d, vd, 1); + if (d[0] != -7.0){ + printf("d[0] should be -7.0, but got %f\n", d[0]); + __builtin_abort (); + } + return 0; +} -- 2.47.3