From 107d5d682576e54963ddd36f3f21bc6b9506d278 Mon Sep 17 00:00:00 2001 From: Xi Ruoyao Date: Mon, 13 Jan 2025 11:28:05 -0700 Subject: [PATCH] RISC-V: Improve bitwise and ashift reassociation for single-bit immediate without zbs [PR 115921] When zbs is not available, there's nothing special with single-bit immediates and we should perform reassociation as normal immediates. gcc/ChangeLog: PR target/115921 * config/riscv/riscv.md (_shift_reverse): Only check popcount_hwi if !TARGET_ZBS. --- gcc/config/riscv/riscv.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 0922cab4402c..0a76ed63f0d1 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2969,9 +2969,9 @@ ;; for IOR/XOR. It probably doesn't matter for AND. ;; ;; We also don't want to do this if the immediate already fits in a simm12 -;; field, or is a single bit operand, or when we might be able to generate -;; a shift-add sequence via the splitter in bitmanip.md -;; in bitmanip.md for masks that are a run of consecutive ones. +;; field, or it is a single bit operand and zbs is available, or when we +;; might be able to generate a shift-add sequence via the splitter in +;; bitmanip.md for masks that are a run of consecutive ones. (define_insn_and_split "_shift_reverse" [(set (match_operand:X 0 "register_operand" "=r") (any_bitwise:X (ashift:X (match_operand:X 1 "register_operand" "r") @@ -2979,7 +2979,7 @@ (match_operand 3 "immediate_operand" "n")))] "(!SMALL_OPERAND (INTVAL (operands[3])) && SMALL_OPERAND (INTVAL (operands[3]) >> INTVAL (operands[2])) - && popcount_hwi (INTVAL (operands[3])) > 1 + && (!TARGET_ZBS || popcount_hwi (INTVAL (operands[3])) > 1) && (!(TARGET_64BIT && TARGET_ZBA) || !consecutive_bits_operand (operands[3], VOIDmode) || !imm123_operand (operands[2], VOIDmode)) -- 2.47.2