From 15944b9f951b6cbec8554e960cc62846a31e52a1 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 23 Aug 2025 10:07:48 +0200 Subject: [PATCH] 6.16-stable patches added patches: accel-habanalabs-gaudi2-use-kvfree-for-memory-allocated-with-kvcalloc.patch drm-amd-display-avoid-a-null-pointer-dereference.patch drm-amd-display-don-t-overclock-dce-6-by-15.patch drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch drm-amd-display-fix-fractional-fb-divider-in-set_pixel_clock_v3.patch drm-amd-display-fix-xorg-desktop-unresponsive-on-replay-panel.patch drm-amdgpu-swm14-update-power-limit-logic.patch drm-i915-gt-relocate-compression-repacking-wa-for-jsl-ehl.patch drm-i915-icl-tc-cache-the-max-lane-count-value.patch drm-i915-icl-tc-convert-aux-powered-warn-to-a-debug-message.patch drm-i915-lnl-tc-fix-handling-of-an-enabled-disconnected-dp-alt-sink.patch drm-i915-lnl-tc-fix-max-lane-count-hw-readout.patch drm-i915-lnl-tc-use-the-cached-max-lane-count-value.patch drm-i915-silence-rpm-wakeref-asserts-on-gen11_gu_misc_iir-access.patch drm-nouveau-gsp-fix-mismatched-alloc-free-for-kvmalloc.patch --- ...e-for-memory-allocated-with-kvcalloc.patch | 39 ++++ ...lay-avoid-a-null-pointer-dereference.patch | 42 ++++ ...-display-don-t-overclock-dce-6-by-15.patch | 53 +++++ ...-time-in-dce110_fill_display_configs.patch | 78 +++++++ ...-time-in-dce110_fill_display_configs.patch | 84 ++++++++ ...-dp-audio-dto1-clock-source-on-dce-6.patch | 91 +++++++++ ...nal-fb-divider-in-set_pixel_clock_v3.patch | 53 +++++ ...desktop-unresponsive-on-replay-panel.patch | 62 ++++++ ...mdgpu-swm14-update-power-limit-logic.patch | 72 +++++++ ...compression-repacking-wa-for-jsl-ehl.patch | 76 +++++++ ...cl-tc-cache-the-max-lane-count-value.patch | 190 ++++++++++++++++++ ...-aux-powered-warn-to-a-debug-message.patch | 45 +++++ ...-an-enabled-disconnected-dp-alt-sink.patch | 100 +++++++++ ...lnl-tc-fix-max-lane-count-hw-readout.patch | 71 +++++++ ...-use-the-cached-max-lane-count-value.patch | 51 +++++ ...-asserts-on-gen11_gu_misc_iir-access.patch | 49 +++++ ...x-mismatched-alloc-free-for-kvmalloc.patch | 50 +++++ queue-6.16/series | 17 ++ 18 files changed, 1223 insertions(+) create mode 100644 queue-6.16/accel-habanalabs-gaudi2-use-kvfree-for-memory-allocated-with-kvcalloc.patch create mode 100644 queue-6.16/drm-amd-display-avoid-a-null-pointer-dereference.patch create mode 100644 queue-6.16/drm-amd-display-don-t-overclock-dce-6-by-15.patch create mode 100644 queue-6.16/drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch create mode 100644 queue-6.16/drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch create mode 100644 queue-6.16/drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch create mode 100644 queue-6.16/drm-amd-display-fix-fractional-fb-divider-in-set_pixel_clock_v3.patch create mode 100644 queue-6.16/drm-amd-display-fix-xorg-desktop-unresponsive-on-replay-panel.patch create mode 100644 queue-6.16/drm-amdgpu-swm14-update-power-limit-logic.patch create mode 100644 queue-6.16/drm-i915-gt-relocate-compression-repacking-wa-for-jsl-ehl.patch create mode 100644 queue-6.16/drm-i915-icl-tc-cache-the-max-lane-count-value.patch create mode 100644 queue-6.16/drm-i915-icl-tc-convert-aux-powered-warn-to-a-debug-message.patch create mode 100644 queue-6.16/drm-i915-lnl-tc-fix-handling-of-an-enabled-disconnected-dp-alt-sink.patch create mode 100644 queue-6.16/drm-i915-lnl-tc-fix-max-lane-count-hw-readout.patch create mode 100644 queue-6.16/drm-i915-lnl-tc-use-the-cached-max-lane-count-value.patch create mode 100644 queue-6.16/drm-i915-silence-rpm-wakeref-asserts-on-gen11_gu_misc_iir-access.patch create mode 100644 queue-6.16/drm-nouveau-gsp-fix-mismatched-alloc-free-for-kvmalloc.patch diff --git a/queue-6.16/accel-habanalabs-gaudi2-use-kvfree-for-memory-allocated-with-kvcalloc.patch b/queue-6.16/accel-habanalabs-gaudi2-use-kvfree-for-memory-allocated-with-kvcalloc.patch new file mode 100644 index 0000000000..e111fd0aad --- /dev/null +++ b/queue-6.16/accel-habanalabs-gaudi2-use-kvfree-for-memory-allocated-with-kvcalloc.patch @@ -0,0 +1,39 @@ +From a44458dfd5bc0c79c6739c3f4c658361d3a5126b Mon Sep 17 00:00:00 2001 +From: Thorsten Blum +Date: Wed, 21 Aug 2024 01:10:28 +0200 +Subject: accel/habanalabs/gaudi2: Use kvfree() for memory allocated with kvcalloc() + +From: Thorsten Blum + +commit a44458dfd5bc0c79c6739c3f4c658361d3a5126b upstream. + +Use kvfree() to fix the following Coccinelle/coccicheck warning reported +by kfree_mismatch.cocci: + + WARNING kvmalloc is used to allocate this memory at line 10398 + +Fixes: f728c17fc97a ("accel/habanalabs/gaudi2: move HMMU page tables to device memory") +Reported-by: Qianfeng Rong +Closes: https://patch.msgid.link/20250808085530.233737-1-rongqianfeng@vivo.com +Signed-off-by: Thorsten Blum +[lukas: acknowledge Qianfeng, adjust Thorsten's domain, add Fixes tag] +Signed-off-by: Lukas Wunner +Reviewed-by: Tomer Tayar +Cc: stable@vger.kernel.org # v6.9+ +Link: https://patch.msgid.link/20240820231028.136126-1-thorsten.blum@toblux.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/accel/habanalabs/gaudi2/gaudi2.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/accel/habanalabs/gaudi2/gaudi2.c ++++ b/drivers/accel/habanalabs/gaudi2/gaudi2.c +@@ -10437,7 +10437,7 @@ end: + (u64 *)(lin_dma_pkts_arr), DEBUGFS_WRITE64); + WREG32(sob_addr, 0); + +- kfree(lin_dma_pkts_arr); ++ kvfree(lin_dma_pkts_arr); + + return rc; + } diff --git a/queue-6.16/drm-amd-display-avoid-a-null-pointer-dereference.patch b/queue-6.16/drm-amd-display-avoid-a-null-pointer-dereference.patch new file mode 100644 index 0000000000..d6ecde69a2 --- /dev/null +++ b/queue-6.16/drm-amd-display-avoid-a-null-pointer-dereference.patch @@ -0,0 +1,42 @@ +From 07b93a5704b0b72002f0c4bd1076214af67dc661 Mon Sep 17 00:00:00 2001 +From: Mario Limonciello +Date: Thu, 24 Jul 2025 15:00:43 -0500 +Subject: drm/amd/display: Avoid a NULL pointer dereference + +From: Mario Limonciello + +commit 07b93a5704b0b72002f0c4bd1076214af67dc661 upstream. + +[WHY] +Although unlikely drm_atomic_get_new_connector_state() or +drm_atomic_get_old_connector_state() can return NULL. + +[HOW] +Check returns before dereference. + +Cc: Mario Limonciello +Cc: Alex Deucher +Reviewed-by: Harry Wentland +Signed-off-by: Mario Limonciello +Signed-off-by: Alex Hung +Tested-by: Dan Wheeler +Signed-off-by: Alex Deucher +(cherry picked from commit 1e5e8d672fec9f2ab352be121be971877bff2af9) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -7761,6 +7761,9 @@ amdgpu_dm_connector_atomic_check(struct + struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); + int ret; + ++ if (WARN_ON(unlikely(!old_con_state || !new_con_state))) ++ return -EINVAL; ++ + trace_amdgpu_dm_connector_atomic_check(new_con_state); + + if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { diff --git a/queue-6.16/drm-amd-display-don-t-overclock-dce-6-by-15.patch b/queue-6.16/drm-amd-display-don-t-overclock-dce-6-by-15.patch new file mode 100644 index 0000000000..e7dd612d12 --- /dev/null +++ b/queue-6.16/drm-amd-display-don-t-overclock-dce-6-by-15.patch @@ -0,0 +1,53 @@ +From cb7b7ae53b557d168b4af5cd8549f3eff920bfb5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Timur=20Krist=C3=B3f?= +Date: Thu, 31 Jul 2025 11:43:46 +0200 +Subject: drm/amd/display: Don't overclock DCE 6 by 15% +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Timur Kristóf + +commit cb7b7ae53b557d168b4af5cd8549f3eff920bfb5 upstream. + +The extra 15% clock was added as a workaround for a Polaris issue +which uses DCE 11, and should not have been used on DCE 6 which +is already hardcoded to the highest possible display clock. +Unfortunately, the extra 15% was mistakenly copied and kept +even on code paths which don't affect Polaris. + +This commit fixes that and also adds a check to make sure +not to exceed the maximum DCE 6 display clock. + +Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris") +Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific") +Fixes: 3ecb3b794e2c ("drm/amd/display: dc/clk_mgr: add support for SI parts (v2)") +Signed-off-by: Timur Kristóf +Acked-by: Alex Deucher +Reviewed-by: Rodrigo Siqueira +Reviewed-by: Alex Hung +Signed-off-by: Alex Deucher +(cherry picked from commit 427980c1cbd22bb256b9385f5ce73c0937562408) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c +@@ -123,11 +123,9 @@ static void dce60_update_clocks(struct c + { + struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct dm_pp_power_level_change_request level_change_req; +- int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; +- +- /*TODO: W/A for dal3 linux, investigate why this works */ +- if (!clk_mgr_dce->dfs_bypass_active) +- patched_disp_clk = patched_disp_clk * 115 / 100; ++ const int max_disp_clk = ++ clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz; ++ int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz); + + level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); + /* get max clock state from PPLIB */ diff --git a/queue-6.16/drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch b/queue-6.16/drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch new file mode 100644 index 0000000000..0804603e1b --- /dev/null +++ b/queue-6.16/drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch @@ -0,0 +1,78 @@ +From 7d07140d37f792f01cfdb8ca9a6a792ab1d29126 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Timur=20Krist=C3=B3f?= +Date: Thu, 31 Jul 2025 11:43:49 +0200 +Subject: drm/amd/display: Fill display clock and vblank time in dce110_fill_display_configs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Timur Kristóf + +commit 7d07140d37f792f01cfdb8ca9a6a792ab1d29126 upstream. + +Also needed by DCE 6. +This way the code that gathers this info can be shared between +different DCE versions and doesn't have to be repeated. + +Signed-off-by: Timur Kristóf +Acked-by: Alex Deucher +Reviewed-by: Rodrigo Siqueira +Reviewed-by: Alex Hung +Signed-off-by: Alex Deucher +(cherry picked from commit 8107432dff37db26fcb641b6cebeae8981cd73a0) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 2 -- + drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 10 +++------- + drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 2 -- + 3 files changed, 3 insertions(+), 11 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +@@ -391,8 +391,6 @@ static void dce_pplib_apply_display_requ + { + struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; + +- pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); +- + dce110_fill_display_configs(context, pp_display_cfg); + + if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c +@@ -124,6 +124,9 @@ void dce110_fill_display_configs( + int j; + int num_cfgs = 0; + ++ pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); ++ pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; ++ pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; + pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator; + + for (j = 0; j < context->stream_count; j++) { +@@ -243,13 +246,6 @@ void dce11_pplib_apply_display_requireme + pp_display_cfg->min_engine_clock_deep_sleep_khz + = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; + +- pp_display_cfg->avail_mclk_switch_time_us = +- dce110_get_min_vblank_time_us(context); +- /* TODO: dce11.2*/ +- pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; +- +- pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; +- + dce110_fill_display_configs(context, pp_display_cfg); + + if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c +@@ -100,8 +100,6 @@ static void dce60_pplib_apply_display_re + { + struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; + +- pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); +- + dce110_fill_display_configs(context, pp_display_cfg); + + if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) diff --git a/queue-6.16/drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch b/queue-6.16/drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch new file mode 100644 index 0000000000..770957d000 --- /dev/null +++ b/queue-6.16/drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch @@ -0,0 +1,84 @@ +From 669f73a26f6112eedbadac53a2f2707ac6d0b9c8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Timur=20Krist=C3=B3f?= +Date: Thu, 31 Jul 2025 11:43:48 +0200 +Subject: drm/amd/display: Find first CRTC and its line time in dce110_fill_display_configs +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Timur Kristóf + +commit 669f73a26f6112eedbadac53a2f2707ac6d0b9c8 upstream. + +dce110_fill_display_configs is shared between DCE 6-11, and +finding the first CRTC and its line time is relevant to DCE 6 too. +Move the code to find it from DCE 11 specific code. + +Signed-off-by: Timur Kristóf +Acked-by: Alex Deucher +Reviewed-by: Rodrigo Siqueira +Reviewed-by: Alex Hung +Signed-off-by: Alex Deucher +(cherry picked from commit 4ab09785f8d5d03df052827af073d5c508ff5f63) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 30 ++++++---- + 1 file changed, 20 insertions(+), 10 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c +@@ -120,9 +120,12 @@ void dce110_fill_display_configs( + const struct dc_state *context, + struct dm_pp_display_configuration *pp_display_cfg) + { ++ struct dc *dc = context->clk_mgr->ctx->dc; + int j; + int num_cfgs = 0; + ++ pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator; ++ + for (j = 0; j < context->stream_count; j++) { + int k; + +@@ -164,6 +167,23 @@ void dce110_fill_display_configs( + cfg->v_refresh /= stream->timing.h_total; + cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) + / stream->timing.v_total; ++ ++ /* Find first CRTC index and calculate its line time. ++ * This is necessary for DPM on SI GPUs. ++ */ ++ if (cfg->pipe_idx < pp_display_cfg->crtc_index) { ++ const struct dc_crtc_timing *timing = ++ &context->streams[0]->timing; ++ ++ pp_display_cfg->crtc_index = cfg->pipe_idx; ++ pp_display_cfg->line_time_in_us = ++ timing->h_total * 10000 / timing->pix_clk_100hz; ++ } ++ } ++ ++ if (!num_cfgs) { ++ pp_display_cfg->crtc_index = 0; ++ pp_display_cfg->line_time_in_us = 0; + } + + pp_display_cfg->display_count = num_cfgs; +@@ -232,16 +252,6 @@ void dce11_pplib_apply_display_requireme + + dce110_fill_display_configs(context, pp_display_cfg); + +- /* TODO: is this still applicable?*/ +- if (pp_display_cfg->display_count == 1) { +- const struct dc_crtc_timing *timing = +- &context->streams[0]->timing; +- +- pp_display_cfg->crtc_index = +- pp_display_cfg->disp_configs[0].pipe_idx; +- pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz; +- } +- + if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) + dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); + } diff --git a/queue-6.16/drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch b/queue-6.16/drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch new file mode 100644 index 0000000000..b74556a61f --- /dev/null +++ b/queue-6.16/drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch @@ -0,0 +1,91 @@ +From 297a4833a68aac3316eb808b4123eb016ef242d7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Timur=20Krist=C3=B3f?= +Date: Sat, 2 Aug 2025 17:51:53 +0200 +Subject: drm/amd/display: Fix DP audio DTO1 clock source on DCE 6. +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Timur Kristóf + +commit 297a4833a68aac3316eb808b4123eb016ef242d7 upstream. + +On DCE 6, DP audio was not working. However, it worked when an +HDMI monitor was also plugged in. + +Looking at dce_aud_wall_dto_setup it seems that the main +difference is that we use DTO1 when only DP is plugged in. + +When programming DTO1, it uses audio_dto_source_clock_in_khz +which is set from get_dp_ref_freq_khz + +The dce60_get_dp_ref_freq_khz implementation looks incorrect, +because DENTIST_DISPCLK_CNTL seems to be always zero on DCE 6, +so it isn't usable. +I compared dce60_get_dp_ref_freq_khz to the legacy display code, +specifically dce_v6_0_audio_set_dto, and it turns out that in +case of DCE 6, it needs to use the display clock. With that, +DP audio started working on Pitcairn, Oland and Cape Verde. + +However, it still didn't work on Tahiti. Despite having the +same DCE version, Tahiti seems to have a different audio device. +After some trial and error I realized that it works with the +default display clock as reported by the VBIOS, not the current +display clock. + +The patch was tested on all four SI GPUs: + +* Pitcairn (DCE 6.0) +* Oland (DCE 6.4) +* Cape Verde (DCE 6.0) +* Tahiti (DCE 6.0 but different) + +The testing was done on Samsung Odyssey G7 LS28BG700EPXEN on +each of the above GPUs, at the following settings: + +* 4K 60 Hz +* 1080p 60 Hz +* 1080p 144 Hz + +Acked-by: Alex Deucher +Reviewed-by: Rodrigo Siqueira +Signed-off-by: Timur Kristóf +Signed-off-by: Alex Deucher +(cherry picked from commit 645cc7863da5de700547d236697dffd6760cf051) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 21 +++-------- + 1 file changed, 6 insertions(+), 15 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c +@@ -83,22 +83,13 @@ static const struct state_dependent_cloc + static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) + { + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); +- int dprefclk_wdivider; +- int dp_ref_clk_khz; +- int target_div; ++ struct dc_context *ctx = clk_mgr_base->ctx; ++ int dp_ref_clk_khz = 0; + +- /* DCE6 has no DPREFCLK_CNTL to read DP Reference Clock source */ +- +- /* Read the mmDENTIST_DISPCLK_CNTL to get the currently +- * programmed DID DENTIST_DPREFCLK_WDIVIDER*/ +- REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider); +- +- /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/ +- target_div = dentist_get_divider_from_did(dprefclk_wdivider); +- +- /* Calculate the current DFS clock, in kHz.*/ +- dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR +- * clk_mgr->base.dentist_vco_freq_khz) / target_div; ++ if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev)) ++ dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency; ++ else ++ dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz; + + return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz); + } diff --git a/queue-6.16/drm-amd-display-fix-fractional-fb-divider-in-set_pixel_clock_v3.patch b/queue-6.16/drm-amd-display-fix-fractional-fb-divider-in-set_pixel_clock_v3.patch new file mode 100644 index 0000000000..a5e5b3705d --- /dev/null +++ b/queue-6.16/drm-amd-display-fix-fractional-fb-divider-in-set_pixel_clock_v3.patch @@ -0,0 +1,53 @@ +From 10507478468f165ea681605d133991ed05cdff62 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Timur=20Krist=C3=B3f?= +Date: Thu, 31 Jul 2025 11:43:52 +0200 +Subject: drm/amd/display: Fix fractional fb divider in set_pixel_clock_v3 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Timur Kristóf + +commit 10507478468f165ea681605d133991ed05cdff62 upstream. + +For later VBIOS versions, the fractional feedback divider is +calculated as the remainder of dividing the feedback divider by +a factor, which is set to 1000000. For reference, see: +- calculate_fb_and_fractional_fb_divider +- calc_pll_max_vco_construct + +However, in case of old VBIOS versions that have +set_pixel_clock_v3, they only have 1 byte available for the +fractional feedback divider, and it's expected to be set to the +remainder from dividing the feedback divider by 10. +For reference see the legacy display code: +- amdgpu_pll_compute +- amdgpu_atombios_crtc_program_pll + +This commit fixes set_pixel_clock_v3 by dividing the fractional +feedback divider passed to the function by 100000. + +Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") +Signed-off-by: Timur Kristóf +Acked-by: Alex Deucher +Reviewed-by: Rodrigo Siqueira +Reviewed-by: Alex Hung +Signed-off-by: Alex Deucher +(cherry picked from commit 027e7acc7e17802ebf28e1edb88a404836ad50d6) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/bios/command_table.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c ++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c +@@ -993,7 +993,7 @@ static enum bp_result set_pixel_clock_v3 + allocation.sPCLKInput.usFbDiv = + cpu_to_le16((uint16_t)bp_params->feedback_divider); + allocation.sPCLKInput.ucFracFbDiv = +- (uint8_t)bp_params->fractional_feedback_divider; ++ (uint8_t)(bp_params->fractional_feedback_divider / 100000); + allocation.sPCLKInput.ucPostDiv = + (uint8_t)bp_params->pixel_clock_post_divider; + diff --git a/queue-6.16/drm-amd-display-fix-xorg-desktop-unresponsive-on-replay-panel.patch b/queue-6.16/drm-amd-display-fix-xorg-desktop-unresponsive-on-replay-panel.patch new file mode 100644 index 0000000000..0ebc126430 --- /dev/null +++ b/queue-6.16/drm-amd-display-fix-xorg-desktop-unresponsive-on-replay-panel.patch @@ -0,0 +1,62 @@ +From 66af73a1c319336694a8610fe4c2943f7b33066c Mon Sep 17 00:00:00 2001 +From: Tom Chung +Date: Fri, 18 Jul 2025 18:25:08 +0800 +Subject: drm/amd/display: Fix Xorg desktop unresponsive on Replay panel + +From: Tom Chung + +commit 66af73a1c319336694a8610fe4c2943f7b33066c upstream. + +[WHY & HOW] +IPS & self-fresh feature can cause vblank counter resets between +vblank disable and enable. +It may cause system stuck due to wait the vblank counter. + +Call the drm_crtc_vblank_restore() during vblank enable to estimate +missed vblanks by using timestamps and update the vblank counter in +DRM. + +It can make the vblank counter increase smoothly and resolve this issue. + +Cc: Mario Limonciello +Cc: Alex Deucher +Reviewed-by: Sun peng (Leo) Li +Signed-off-by: Tom Chung +Signed-off-by: Alex Hung +Tested-by: Dan Wheeler +Signed-off-by: Alex Deucher +(cherry picked from commit 34d66bc7ff10e146a4cec76cf286979740a10954) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 19 +++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +@@ -299,6 +299,25 @@ static inline int amdgpu_dm_crtc_set_vbl + irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); + + if (enable) { ++ struct dc *dc = adev->dm.dc; ++ struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); ++ struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; ++ struct replay_settings *pr = &acrtc_state->stream->link->replay_settings; ++ bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) || ++ pr->config.replay_supported; ++ ++ /* ++ * IPS & self-refresh feature can cause vblank counter resets between ++ * vblank disable and enable. ++ * It may cause system stuck due to waiting for the vblank counter. ++ * Call this function to estimate missed vblanks by using timestamps and ++ * update the vblank counter in DRM. ++ */ ++ if (dc->caps.ips_support && ++ dc->config.disable_ips != DMUB_IPS_DISABLE_ALL && ++ sr_supported && vblank->config.disable_immediate) ++ drm_crtc_vblank_restore(crtc); ++ + /* vblank irq on -> Only need vupdate irq in vrr mode */ + if (amdgpu_dm_crtc_vrr_active(acrtc_state)) + rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true); diff --git a/queue-6.16/drm-amdgpu-swm14-update-power-limit-logic.patch b/queue-6.16/drm-amdgpu-swm14-update-power-limit-logic.patch new file mode 100644 index 0000000000..c7499c1921 --- /dev/null +++ b/queue-6.16/drm-amdgpu-swm14-update-power-limit-logic.patch @@ -0,0 +1,72 @@ +From 79e25cd06e85105c75701ef1773c6c64bb304091 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Fri, 8 Aug 2025 13:12:07 -0400 +Subject: drm/amdgpu/swm14: Update power limit logic + +From: Alex Deucher + +commit 79e25cd06e85105c75701ef1773c6c64bb304091 upstream. + +Take into account the limits from the vbios. Ported +from the SMU13 code. + +Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4352 +Reviewed-by: Jesse Zhang +Reviewed-by: Kenneth Feng +Signed-off-by: Alex Deucher +(cherry picked from commit 203cc7f1dd86f2c8de5c3c6182f19adac7c9c206) +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 30 +++++++++++++++---- + 1 file changed, 25 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +@@ -1689,9 +1689,11 @@ static int smu_v14_0_2_get_power_limit(s + uint32_t *min_power_limit) + { + struct smu_table_context *table_context = &smu->smu_table; ++ struct smu_14_0_2_powerplay_table *powerplay_table = ++ table_context->power_play_table; + PPTable_t *pptable = table_context->driver_pptable; + CustomSkuTable_t *skutable = &pptable->CustomSkuTable; +- uint32_t power_limit; ++ uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0; + uint32_t msg_limit = pptable->SkuTable.MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC]; + + if (smu_v14_0_get_current_power_limit(smu, &power_limit)) +@@ -1704,11 +1706,29 @@ static int smu_v14_0_2_get_power_limit(s + if (default_power_limit) + *default_power_limit = power_limit; + +- if (max_power_limit) +- *max_power_limit = msg_limit; ++ if (powerplay_table) { ++ if (smu->od_enabled && ++ smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) { ++ od_percent_upper = pptable->SkuTable.OverDriveLimitsBasicMax.Ppt; ++ od_percent_lower = pptable->SkuTable.OverDriveLimitsBasicMin.Ppt; ++ } else if (smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) { ++ od_percent_upper = 0; ++ od_percent_lower = pptable->SkuTable.OverDriveLimitsBasicMin.Ppt; ++ } ++ } + +- if (min_power_limit) +- *min_power_limit = 0; ++ dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n", ++ od_percent_upper, od_percent_lower, power_limit); ++ ++ if (max_power_limit) { ++ *max_power_limit = msg_limit * (100 + od_percent_upper); ++ *max_power_limit /= 100; ++ } ++ ++ if (min_power_limit) { ++ *min_power_limit = power_limit * (100 + od_percent_lower); ++ *min_power_limit /= 100; ++ } + + return 0; + } diff --git a/queue-6.16/drm-i915-gt-relocate-compression-repacking-wa-for-jsl-ehl.patch b/queue-6.16/drm-i915-gt-relocate-compression-repacking-wa-for-jsl-ehl.patch new file mode 100644 index 0000000000..bc13c90f5e --- /dev/null +++ b/queue-6.16/drm-i915-gt-relocate-compression-repacking-wa-for-jsl-ehl.patch @@ -0,0 +1,76 @@ +From 8236820fd767f400d1baefb71bc7e36e37730a1e Mon Sep 17 00:00:00 2001 +From: Sebastian Brzezinka +Date: Mon, 11 Aug 2025 09:12:31 +0000 +Subject: drm/i915/gt: Relocate compression repacking WA for JSL/EHL + +From: Sebastian Brzezinka + +commit 8236820fd767f400d1baefb71bc7e36e37730a1e upstream. + +CACHE_MODE_0 registers should be saved and restored as part of +the context, not during engine reset. Move the related workaround +(Disable Repacking for Compression) from rcs_engine_wa_init() +to icl_ctx_workarounds_init() for Jasper Lake and Elkhart +Lake platforms. This ensures the WA is applied during context +initialisation. + +BSPEC: 11322 + +Fixes: 0ddae025ab6c ("drm/i915: Disable compression tricks on JSL") +Closes: Fixes: 0ddae025ab6c ("drm/i915: Disable compression tricks on JSL") +Signed-off-by: Sebastian Brzezinka +Cc: stable@vger.kernel.org # v6.13+ +Reviewed-by: Andi Shyti +Reviewed-by: Krzysztof Karas +Signed-off-by: Andi Shyti +Link: https://lore.kernel.org/r/4feaa24094e019e000ceb6011d8cd419b0361b3f.1754902406.git.sebastian.brzezinka@intel.com +(cherry picked from commit c9932f0d604e4c8f2c6018e598a322acb43c68a2) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 +++++++++++--------- + 1 file changed, 11 insertions(+), 9 deletions(-) + +--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c ++++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c +@@ -634,6 +634,8 @@ static void cfl_ctx_workarounds_init(str + static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, + struct i915_wa_list *wal) + { ++ struct drm_i915_private *i915 = engine->i915; ++ + /* Wa_1406697149 (WaDisableBankHangMode:icl) */ + wa_write(wal, GEN8_L3CNTLREG, GEN8_ERRDETBCTRL); + +@@ -669,6 +671,15 @@ static void icl_ctx_workarounds_init(str + + /* Wa_1406306137:icl,ehl */ + wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); ++ ++ if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) { ++ /* ++ * Disable Repacking for Compression (masked R/W access) ++ * before rendering compressed surfaces for display. ++ */ ++ wa_masked_en(wal, CACHE_MODE_0_GEN7, ++ DISABLE_REPACKING_FOR_COMPRESSION); ++ } + } + + /* +@@ -2306,15 +2317,6 @@ rcs_engine_wa_init(struct intel_engine_c + GEN8_RC_SEMA_IDLE_MSG_DISABLE); + } + +- if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) { +- /* +- * "Disable Repacking for Compression (masked R/W access) +- * before rendering compressed surfaces for display." +- */ +- wa_masked_en(wal, CACHE_MODE_0_GEN7, +- DISABLE_REPACKING_FOR_COMPRESSION); +- } +- + if (GRAPHICS_VER(i915) == 11) { + /* This is not an Wa. Enable for better image quality */ + wa_masked_en(wal, diff --git a/queue-6.16/drm-i915-icl-tc-cache-the-max-lane-count-value.patch b/queue-6.16/drm-i915-icl-tc-cache-the-max-lane-count-value.patch new file mode 100644 index 0000000000..ad82ab2813 --- /dev/null +++ b/queue-6.16/drm-i915-icl-tc-cache-the-max-lane-count-value.patch @@ -0,0 +1,190 @@ +From 5fd35236546abe780eaadb7561e09953719d4fc3 Mon Sep 17 00:00:00 2001 +From: Imre Deak +Date: Mon, 11 Aug 2025 11:01:49 +0300 +Subject: drm/i915/icl+/tc: Cache the max lane count value + +From: Imre Deak + +commit 5fd35236546abe780eaadb7561e09953719d4fc3 upstream. + +The PHY's pin assignment value in the TCSS_DDI_STATUS register - as set +by the HW/FW based on the connected DP-alt sink's TypeC/PD pin +assignment negotiation - gets cleared by the HW/FW on LNL+ as soon as +the sink gets disconnected, even if the PHY ownership got acquired +already by the driver (and hence the PHY itself is still connected and +used by the display). This is similar to how the PHY Ready flag gets +cleared on LNL+ in the same register. + +To be able to query the max lane count value on LNL+ - which is based on +the above pin assignment - at all times even after the sink gets +disconnected, the max lane count must be determined and cached during +the PHY's HW readout and connect sequences. Do that here, leaving the +actual use of the cached value to a follow-up change. + +v2: Don't read out the pin configuration if the PHY is disconnected. + +Cc: stable@vger.kernel.org # v6.8+ +Reported-by: Charlton Lin +Tested-by: Khaled Almahallawy +Reviewed-by: Mika Kahola +Signed-off-by: Imre Deak +Link: https://lore.kernel.org/r/20250811080152.906216-3-imre.deak@intel.com +(cherry picked from commit 3e32438fc406761f81b1928d210b3d2a5e7501a0) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_tc.c | 57 ++++++++++++++++++++++++++------ + 1 file changed, 48 insertions(+), 9 deletions(-) + +--- a/drivers/gpu/drm/i915/display/intel_tc.c ++++ b/drivers/gpu/drm/i915/display/intel_tc.c +@@ -65,6 +65,7 @@ struct intel_tc_port { + enum tc_port_mode init_mode; + enum phy_fia phy_fia; + u8 phy_fia_idx; ++ u8 max_lane_count; + }; + + static enum intel_display_power_domain +@@ -364,12 +365,12 @@ static int intel_tc_port_get_max_lane_co + } + } + +-int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port) ++static int get_max_lane_count(struct intel_tc_port *tc) + { +- struct intel_display *display = to_intel_display(dig_port); +- struct intel_tc_port *tc = to_tc_port(dig_port); ++ struct intel_display *display = to_intel_display(tc->dig_port); ++ struct intel_digital_port *dig_port = tc->dig_port; + +- if (!intel_encoder_is_tc(&dig_port->base) || tc->mode != TC_PORT_DP_ALT) ++ if (tc->mode != TC_PORT_DP_ALT) + return 4; + + assert_tc_cold_blocked(tc); +@@ -383,6 +384,21 @@ int intel_tc_port_max_lane_count(struct + return intel_tc_port_get_max_lane_count(dig_port); + } + ++static void read_pin_configuration(struct intel_tc_port *tc) ++{ ++ tc->max_lane_count = get_max_lane_count(tc); ++} ++ ++int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port) ++{ ++ struct intel_tc_port *tc = to_tc_port(dig_port); ++ ++ if (!intel_encoder_is_tc(&dig_port->base)) ++ return 4; ++ ++ return get_max_lane_count(tc); ++} ++ + void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port, + int required_lanes) + { +@@ -595,9 +611,12 @@ static void icl_tc_phy_get_hw_state(stru + tc_cold_wref = __tc_cold_block(tc, &domain); + + tc->mode = tc_phy_get_current_mode(tc); +- if (tc->mode != TC_PORT_DISCONNECTED) ++ if (tc->mode != TC_PORT_DISCONNECTED) { + tc->lock_wakeref = tc_cold_block(tc); + ++ read_pin_configuration(tc); ++ } ++ + __tc_cold_unblock(tc, domain, tc_cold_wref); + } + +@@ -655,8 +674,11 @@ static bool icl_tc_phy_connect(struct in + + tc->lock_wakeref = tc_cold_block(tc); + +- if (tc->mode == TC_PORT_TBT_ALT) ++ if (tc->mode == TC_PORT_TBT_ALT) { ++ read_pin_configuration(tc); ++ + return true; ++ } + + if ((!tc_phy_is_ready(tc) || + !icl_tc_phy_take_ownership(tc, true)) && +@@ -667,6 +689,7 @@ static bool icl_tc_phy_connect(struct in + goto out_unblock_tc_cold; + } + ++ read_pin_configuration(tc); + + if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes)) + goto out_release_phy; +@@ -857,9 +880,12 @@ static void adlp_tc_phy_get_hw_state(str + port_wakeref = intel_display_power_get(display, port_power_domain); + + tc->mode = tc_phy_get_current_mode(tc); +- if (tc->mode != TC_PORT_DISCONNECTED) ++ if (tc->mode != TC_PORT_DISCONNECTED) { + tc->lock_wakeref = tc_cold_block(tc); + ++ read_pin_configuration(tc); ++ } ++ + intel_display_power_put(display, port_power_domain, port_wakeref); + } + +@@ -872,6 +898,9 @@ static bool adlp_tc_phy_connect(struct i + + if (tc->mode == TC_PORT_TBT_ALT) { + tc->lock_wakeref = tc_cold_block(tc); ++ ++ read_pin_configuration(tc); ++ + return true; + } + +@@ -893,6 +922,8 @@ static bool adlp_tc_phy_connect(struct i + + tc->lock_wakeref = tc_cold_block(tc); + ++ read_pin_configuration(tc); ++ + if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes)) + goto out_unblock_tc_cold; + +@@ -1123,9 +1154,12 @@ static void xelpdp_tc_phy_get_hw_state(s + tc_cold_wref = __tc_cold_block(tc, &domain); + + tc->mode = tc_phy_get_current_mode(tc); +- if (tc->mode != TC_PORT_DISCONNECTED) ++ if (tc->mode != TC_PORT_DISCONNECTED) { + tc->lock_wakeref = tc_cold_block(tc); + ++ read_pin_configuration(tc); ++ } ++ + drm_WARN_ON(display->drm, + (tc->mode == TC_PORT_DP_ALT || tc->mode == TC_PORT_LEGACY) && + !xelpdp_tc_phy_tcss_power_is_enabled(tc)); +@@ -1137,14 +1171,19 @@ static bool xelpdp_tc_phy_connect(struct + { + tc->lock_wakeref = tc_cold_block(tc); + +- if (tc->mode == TC_PORT_TBT_ALT) ++ if (tc->mode == TC_PORT_TBT_ALT) { ++ read_pin_configuration(tc); ++ + return true; ++ } + + if (!xelpdp_tc_phy_enable_tcss_power(tc, true)) + goto out_unblock_tccold; + + xelpdp_tc_phy_take_ownership(tc, true); + ++ read_pin_configuration(tc); ++ + if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes)) + goto out_release_phy; + diff --git a/queue-6.16/drm-i915-icl-tc-convert-aux-powered-warn-to-a-debug-message.patch b/queue-6.16/drm-i915-icl-tc-convert-aux-powered-warn-to-a-debug-message.patch new file mode 100644 index 0000000000..77f1cdde54 --- /dev/null +++ b/queue-6.16/drm-i915-icl-tc-convert-aux-powered-warn-to-a-debug-message.patch @@ -0,0 +1,45 @@ +From d7fa5754e83cd36c4327eb2d806064e598a72ff6 Mon Sep 17 00:00:00 2001 +From: Imre Deak +Date: Mon, 11 Aug 2025 11:01:52 +0300 +Subject: drm/i915/icl+/tc: Convert AUX powered WARN to a debug message + +From: Imre Deak + +commit d7fa5754e83cd36c4327eb2d806064e598a72ff6 upstream. + +The BIOS can leave the AUX power well enabled on an output, even if this +isn't required (on platforms where the AUX power is only needed for an +AUX access). This was observed at least on PTL. To avoid the WARN which +would be triggered by this during the HW readout, convert the WARN to a +debug message. + +Cc: stable@vger.kernel.org # v6.8+ +Reported-by: Charlton Lin +Tested-by: Khaled Almahallawy +Reviewed-by: Mika Kahola +Signed-off-by: Imre Deak +Link: https://lore.kernel.org/r/20250811080152.906216-6-imre.deak@intel.com +(cherry picked from commit 6cb52cba474b2bec1a3018d3dbf75292059a29a1) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_tc.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/i915/display/intel_tc.c ++++ b/drivers/gpu/drm/i915/display/intel_tc.c +@@ -1497,11 +1497,11 @@ static void intel_tc_port_reset_mode(str + intel_display_power_flush_work(display); + if (!intel_tc_cold_requires_aux_pw(dig_port)) { + enum intel_display_power_domain aux_domain; +- bool aux_powered; + + aux_domain = intel_aux_power_domain(dig_port); +- aux_powered = intel_display_power_is_enabled(display, aux_domain); +- drm_WARN_ON(display->drm, aux_powered); ++ if (intel_display_power_is_enabled(display, aux_domain)) ++ drm_dbg_kms(display->drm, "Port %s: AUX unexpectedly powered\n", ++ tc->port_name); + } + + tc_phy_disconnect(tc); diff --git a/queue-6.16/drm-i915-lnl-tc-fix-handling-of-an-enabled-disconnected-dp-alt-sink.patch b/queue-6.16/drm-i915-lnl-tc-fix-handling-of-an-enabled-disconnected-dp-alt-sink.patch new file mode 100644 index 0000000000..0f0eb496f9 --- /dev/null +++ b/queue-6.16/drm-i915-lnl-tc-fix-handling-of-an-enabled-disconnected-dp-alt-sink.patch @@ -0,0 +1,100 @@ +From f52d6aa98379842fc255d93282655566f2114e0c Mon Sep 17 00:00:00 2001 +From: Imre Deak +Date: Mon, 11 Aug 2025 11:01:48 +0300 +Subject: drm/i915/lnl+/tc: Fix handling of an enabled/disconnected dp-alt sink + +From: Imre Deak + +commit f52d6aa98379842fc255d93282655566f2114e0c upstream. + +The TypeC PHY HW readout during driver loading and system resume +determines which TypeC mode the PHY is in (legacy/DP-alt/TBT-alt) and +whether the PHY is connected, based on the PHY's Owned and Ready flags. +For the PHY to be in DP-alt or legacy mode and for the PHY to be in the +connected state in these modes, both the Owned (set by the BIOS/driver) +and the Ready (set by the HW) flags should be set. + +On ICL-MTL the HW kept the PHY's Ready flag set after the driver +connected the PHY by acquiring the PHY ownership (by setting the Owned +flag), until the driver disconnected the PHY by releasing the PHY +ownership (by clearing the Owned flag). On LNL+ this has changed, in +that the HW clears the Ready flag as soon as the sink gets disconnected, +even if the PHY ownership was acquired already and hence the PHY is +being used by the display. + +When inheriting the HW state from BIOS for a PHY connected in DP-alt +mode on which the sink got disconnected - i.e. in a case where the sink +was connected while BIOS/GOP was running and so the sink got enabled +connecting the PHY, but the user disconnected the sink by the time the +driver loaded - the PHY Owned but not Ready state must be accounted for +on LNL+ according to the above. Do that by assuming on LNL+ that the PHY +is connected in DP-alt mode whenever the PHY Owned flag is set, +regardless of the PHY Ready flag. + +This fixes a problem on LNL+, where the PHY TypeC mode / connected state +was detected incorrectly for a DP-alt sink, which got connected and then +disconnected by the user in the above way. + +v2: Rename tc_phy_in_legacy_or_dp_alt_mode() to tc_phy_owned_by_display(). + (Luca, Jani) + +Cc: Jani Nikula +Cc: stable@vger.kernel.org # v6.8+ +Reported-by: Charlton Lin +Tested-by: Khaled Almahallawy +Reviewed-by: Mika Kahola +Reviewed-by: Luca Coelho +[Imre: Add one-liner function documentation for tc_phy_owned_by_display()] +Signed-off-by: Imre Deak +Link: https://lore.kernel.org/r/20250811080152.906216-2-imre.deak@intel.com +(cherry picked from commit 89f4b196ee4b056e0e8c179b247b29d4a71a4e7e) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_tc.c | 17 +++++++++++------ + 1 file changed, 11 insertions(+), 6 deletions(-) + +--- a/drivers/gpu/drm/i915/display/intel_tc.c ++++ b/drivers/gpu/drm/i915/display/intel_tc.c +@@ -1225,14 +1225,19 @@ static void tc_phy_get_hw_state(struct i + tc->phy_ops->get_hw_state(tc); + } + +-static bool tc_phy_is_ready_and_owned(struct intel_tc_port *tc, +- bool phy_is_ready, bool phy_is_owned) ++/* Is the PHY owned by display i.e. is it in legacy or DP-alt mode? */ ++static bool tc_phy_owned_by_display(struct intel_tc_port *tc, ++ bool phy_is_ready, bool phy_is_owned) + { + struct intel_display *display = to_intel_display(tc->dig_port); + +- drm_WARN_ON(display->drm, phy_is_owned && !phy_is_ready); ++ if (DISPLAY_VER(display) < 20) { ++ drm_WARN_ON(display->drm, phy_is_owned && !phy_is_ready); + +- return phy_is_ready && phy_is_owned; ++ return phy_is_ready && phy_is_owned; ++ } else { ++ return phy_is_owned; ++ } + } + + static bool tc_phy_is_connected(struct intel_tc_port *tc, +@@ -1243,7 +1248,7 @@ static bool tc_phy_is_connected(struct i + bool phy_is_owned = tc_phy_is_owned(tc); + bool is_connected; + +- if (tc_phy_is_ready_and_owned(tc, phy_is_ready, phy_is_owned)) ++ if (tc_phy_owned_by_display(tc, phy_is_ready, phy_is_owned)) + is_connected = port_pll_type == ICL_PORT_DPLL_MG_PHY; + else + is_connected = port_pll_type == ICL_PORT_DPLL_DEFAULT; +@@ -1351,7 +1356,7 @@ tc_phy_get_current_mode(struct intel_tc_ + phy_is_ready = tc_phy_is_ready(tc); + phy_is_owned = tc_phy_is_owned(tc); + +- if (!tc_phy_is_ready_and_owned(tc, phy_is_ready, phy_is_owned)) { ++ if (!tc_phy_owned_by_display(tc, phy_is_ready, phy_is_owned)) { + mode = get_tc_mode_in_phy_not_owned_state(tc, live_mode); + } else { + drm_WARN_ON(display->drm, live_mode == TC_PORT_TBT_ALT); diff --git a/queue-6.16/drm-i915-lnl-tc-fix-max-lane-count-hw-readout.patch b/queue-6.16/drm-i915-lnl-tc-fix-max-lane-count-hw-readout.patch new file mode 100644 index 0000000000..9b5a86ec06 --- /dev/null +++ b/queue-6.16/drm-i915-lnl-tc-fix-max-lane-count-hw-readout.patch @@ -0,0 +1,71 @@ +From c87514a0bb0a64507412a2d98264060dc0c1562a Mon Sep 17 00:00:00 2001 +From: Imre Deak +Date: Mon, 11 Aug 2025 11:01:50 +0300 +Subject: drm/i915/lnl+/tc: Fix max lane count HW readout + +From: Imre Deak + +commit c87514a0bb0a64507412a2d98264060dc0c1562a upstream. + +On LNL+ for a disconnected sink the pin assignment value gets cleared by +the HW/FW as soon as the sink gets disconnected, even if the PHY +ownership got acquired already by the BIOS/driver (and hence the PHY +itself is still connected and used by the display). During HW readout +this can result in detecting the PHY's max lane count as 0 - matching +the above cleared aka NONE pin assignment HW state. For a connected PHY +the driver in general (outside of intel_tc.c) expects the max lane count +value to be valid for the video mode enabled on the corresponding output +(1, 2 or 4). Ensure this by setting the max lane count to 4 in this +case. Note, that it doesn't matter if this lane count happened to be +more than the max lane count with which the PHY got connected and +enabled, since the only thing the driver can do with such an output - +where the DP-alt sink is disconnected - is to disable the output. + +v2: Rebased on change reading out the pin configuration only if the PHY + is connected. + +Cc: stable@vger.kernel.org # v6.8+ +Reported-by: Charlton Lin +Tested-by: Khaled Almahallawy +Reviewed-by: Mika Kahola +Signed-off-by: Imre Deak +Link: https://lore.kernel.org/r/20250811080152.906216-4-imre.deak@intel.com +(cherry picked from commit 33cf70bc0fe760224f892bc1854a33665f27d482) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_tc.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/gpu/drm/i915/display/intel_tc.c ++++ b/drivers/gpu/drm/i915/display/intel_tc.c +@@ -22,6 +22,7 @@ + #include "intel_modeset_lock.h" + #include "intel_tc.h" + ++#define DP_PIN_ASSIGNMENT_NONE 0x0 + #define DP_PIN_ASSIGNMENT_C 0x3 + #define DP_PIN_ASSIGNMENT_D 0x4 + #define DP_PIN_ASSIGNMENT_E 0x5 +@@ -307,6 +308,8 @@ static int lnl_tc_port_get_max_lane_coun + REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val); + + switch (pin_assignment) { ++ case DP_PIN_ASSIGNMENT_NONE: ++ return 0; + default: + MISSING_CASE(pin_assignment); + fallthrough; +@@ -1158,6 +1161,12 @@ static void xelpdp_tc_phy_get_hw_state(s + tc->lock_wakeref = tc_cold_block(tc); + + read_pin_configuration(tc); ++ /* ++ * Set a valid lane count value for a DP-alt sink which got ++ * disconnected. The driver can only disable the output on this PHY. ++ */ ++ if (tc->max_lane_count == 0) ++ tc->max_lane_count = 4; + } + + drm_WARN_ON(display->drm, diff --git a/queue-6.16/drm-i915-lnl-tc-use-the-cached-max-lane-count-value.patch b/queue-6.16/drm-i915-lnl-tc-use-the-cached-max-lane-count-value.patch new file mode 100644 index 0000000000..e52819a416 --- /dev/null +++ b/queue-6.16/drm-i915-lnl-tc-use-the-cached-max-lane-count-value.patch @@ -0,0 +1,51 @@ +From c5c2b4b3841666be3a45346d0ffa96b4b143504e Mon Sep 17 00:00:00 2001 +From: Imre Deak +Date: Mon, 11 Aug 2025 11:01:51 +0300 +Subject: drm/i915/lnl+/tc: Use the cached max lane count value + +From: Imre Deak + +commit c5c2b4b3841666be3a45346d0ffa96b4b143504e upstream. + +Use the cached max lane count value on LNL+, to account for scenarios +where this value is queried after the HW cleared the corresponding pin +assignment value in the TCSS_DDI_STATUS register after the sink got +disconnected. + +For consistency, follow-up changes will use the cached max lane count +value on other platforms as well and will also cache the pin assignment +value in a similar way. + +Cc: stable@vger.kernel.org # v6.8+ +Reported-by: Charlton Lin +Tested-by: Khaled Almahallawy +Reviewed-by: Mika Kahola +Signed-off-by: Imre Deak +Link: https://lore.kernel.org/r/20250811080152.906216-5-imre.deak@intel.com +(cherry picked from commit afc4e84388079f4d5ba05271632b7a4d8d85165c) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_tc.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/display/intel_tc.c ++++ b/drivers/gpu/drm/i915/display/intel_tc.c +@@ -394,12 +394,16 @@ static void read_pin_configuration(struc + + int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port) + { ++ struct intel_display *display = to_intel_display(dig_port); + struct intel_tc_port *tc = to_tc_port(dig_port); + + if (!intel_encoder_is_tc(&dig_port->base)) + return 4; + +- return get_max_lane_count(tc); ++ if (DISPLAY_VER(display) < 20) ++ return get_max_lane_count(tc); ++ ++ return tc->max_lane_count; + } + + void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port, diff --git a/queue-6.16/drm-i915-silence-rpm-wakeref-asserts-on-gen11_gu_misc_iir-access.patch b/queue-6.16/drm-i915-silence-rpm-wakeref-asserts-on-gen11_gu_misc_iir-access.patch new file mode 100644 index 0000000000..bda197414f --- /dev/null +++ b/queue-6.16/drm-i915-silence-rpm-wakeref-asserts-on-gen11_gu_misc_iir-access.patch @@ -0,0 +1,49 @@ +From ff646d033783068cc5b38924873cab4a536b17c1 Mon Sep 17 00:00:00 2001 +From: Jani Nikula +Date: Tue, 5 Aug 2025 14:56:56 +0300 +Subject: drm/i915: silence rpm wakeref asserts on GEN11_GU_MISC_IIR access +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Jani Nikula + +commit ff646d033783068cc5b38924873cab4a536b17c1 upstream. + +Commit 8d9908e8fe9c ("drm/i915/display: remove small micro-optimizations +in irq handling") not only removed the optimizations, it also enabled +wakeref asserts for the GEN11_GU_MISC_IIR access. Silence the asserts by +wrapping the access inside intel_display_rpm_assert_{block,unblock}(). + +Reported-by: "Jason A. Donenfeld" +Closes: https://lore.kernel.org/r/aG0tWkfmxWtxl_xc@zx2c4.com +Fixes: 8d9908e8fe9c ("drm/i915/display: remove small micro-optimizations in irq handling") +Cc: stable@vger.kernel.org # v6.13+ +Suggested-by: Ville Syrjälä +Reviewed-by: Jouni Högander +Link: https://lore.kernel.org/r/20250805115656.832235-1-jani.nikula@intel.com +Signed-off-by: Jani Nikula +(cherry picked from commit cbd3baeffbc08052ce7dc53f11bf5524b4411056) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_display_irq.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/gpu/drm/i915/display/intel_display_irq.c ++++ b/drivers/gpu/drm/i915/display/intel_display_irq.c +@@ -1492,10 +1492,14 @@ u32 gen11_gu_misc_irq_ack(struct intel_d + if (!(master_ctl & GEN11_GU_MISC_IRQ)) + return 0; + ++ intel_display_rpm_assert_block(display); ++ + iir = intel_de_read(display, GEN11_GU_MISC_IIR); + if (likely(iir)) + intel_de_write(display, GEN11_GU_MISC_IIR, iir); + ++ intel_display_rpm_assert_unblock(display); ++ + return iir; + } + diff --git a/queue-6.16/drm-nouveau-gsp-fix-mismatched-alloc-free-for-kvmalloc.patch b/queue-6.16/drm-nouveau-gsp-fix-mismatched-alloc-free-for-kvmalloc.patch new file mode 100644 index 0000000000..f8680cdc43 --- /dev/null +++ b/queue-6.16/drm-nouveau-gsp-fix-mismatched-alloc-free-for-kvmalloc.patch @@ -0,0 +1,50 @@ +From 989fe6771266bdb82a815d78802c5aa7c918fdfd Mon Sep 17 00:00:00 2001 +From: Qianfeng Rong +Date: Wed, 13 Aug 2025 20:54:04 +0800 +Subject: drm/nouveau/gsp: fix mismatched alloc/free for kvmalloc() + +From: Qianfeng Rong + +commit 989fe6771266bdb82a815d78802c5aa7c918fdfd upstream. + +Replace kfree() with kvfree() for memory allocated by kvmalloc(). + +Compile-tested only. + +Cc: stable@vger.kernel.org +Fixes: 8a8b1ec5261f ("drm/nouveau/gsp: split rpc handling out on its own") +Signed-off-by: Qianfeng Rong +Reviewed-by: Timur Tabi +Acked-by: Zhi Wang +Link: https://lore.kernel.org/r/20250813125412.96178-1-rongqianfeng@vivo.com +Signed-off-by: Danilo Krummrich +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/rpc.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/rpc.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/rpc.c +index 9d06ff722fea..0dc4782df8c0 100644 +--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/rpc.c ++++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/rpc.c +@@ -325,7 +325,7 @@ r535_gsp_msgq_recv(struct nvkm_gsp *gsp, u32 gsp_rpc_len, int *retries) + + rpc = r535_gsp_msgq_peek(gsp, sizeof(*rpc), info.retries); + if (IS_ERR_OR_NULL(rpc)) { +- kfree(buf); ++ kvfree(buf); + return rpc; + } + +@@ -334,7 +334,7 @@ r535_gsp_msgq_recv(struct nvkm_gsp *gsp, u32 gsp_rpc_len, int *retries) + + rpc = r535_gsp_msgq_recv_one_elem(gsp, &info); + if (IS_ERR_OR_NULL(rpc)) { +- kfree(buf); ++ kvfree(buf); + return rpc; + } + +-- +2.50.1 + diff --git a/queue-6.16/series b/queue-6.16/series index 4ca7d62c83..cc2be03f35 100644 --- a/queue-6.16/series +++ b/queue-6.16/series @@ -253,3 +253,20 @@ rdma-rxe-flush-delayed-skbs-while-releasing-rxe-resources.patch s390-sclp-fix-sccb-present-check.patch platform-x86-intel-uncore-freq-check-write-blocked-for-elc.patch compiler-remove-__addressable_asm-_str-again.patch +accel-habanalabs-gaudi2-use-kvfree-for-memory-allocated-with-kvcalloc.patch +drm-amdgpu-swm14-update-power-limit-logic.patch +drm-i915-silence-rpm-wakeref-asserts-on-gen11_gu_misc_iir-access.patch +drm-nouveau-gsp-fix-mismatched-alloc-free-for-kvmalloc.patch +drm-i915-gt-relocate-compression-repacking-wa-for-jsl-ehl.patch +drm-i915-lnl-tc-fix-handling-of-an-enabled-disconnected-dp-alt-sink.patch +drm-i915-icl-tc-cache-the-max-lane-count-value.patch +drm-i915-lnl-tc-fix-max-lane-count-hw-readout.patch +drm-i915-lnl-tc-use-the-cached-max-lane-count-value.patch +drm-i915-icl-tc-convert-aux-powered-warn-to-a-debug-message.patch +drm-amd-display-avoid-a-null-pointer-dereference.patch +drm-amd-display-don-t-overclock-dce-6-by-15.patch +drm-amd-display-fix-fractional-fb-divider-in-set_pixel_clock_v3.patch +drm-amd-display-fix-xorg-desktop-unresponsive-on-replay-panel.patch +drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch +drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch +drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch -- 2.47.3