From 16d70a116d62ad87d2af692b27667ac0e857702b Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 17 Apr 2025 16:12:27 +0200 Subject: [PATCH] 6.6-stable patches added patches: arm64-errata-add-newer-arm-cores-to-the-spectre_bhb_loop_affected-lists.patch --- ...-the-spectre_bhb_loop_affected-lists.patch | 68 +++++++++++++++++++ queue-6.6/series | 1 + 2 files changed, 69 insertions(+) create mode 100644 queue-6.6/arm64-errata-add-newer-arm-cores-to-the-spectre_bhb_loop_affected-lists.patch diff --git a/queue-6.6/arm64-errata-add-newer-arm-cores-to-the-spectre_bhb_loop_affected-lists.patch b/queue-6.6/arm64-errata-add-newer-arm-cores-to-the-spectre_bhb_loop_affected-lists.patch new file mode 100644 index 0000000000..6bd64209af --- /dev/null +++ b/queue-6.6/arm64-errata-add-newer-arm-cores-to-the-spectre_bhb_loop_affected-lists.patch @@ -0,0 +1,68 @@ +From a5951389e58d2e816eed3dbec5877de9327fd881 Mon Sep 17 00:00:00 2001 +From: Douglas Anderson +Date: Tue, 7 Jan 2025 12:06:02 -0800 +Subject: arm64: errata: Add newer ARM cores to the spectre_bhb_loop_affected() lists + +From: Douglas Anderson + +commit a5951389e58d2e816eed3dbec5877de9327fd881 upstream. + +When comparing to the ARM list [1], it appears that several ARM cores +were missing from the lists in spectre_bhb_loop_affected(). Add them. + +NOTE: for some of these cores it may not matter since other ways of +clearing the BHB may be used (like the CLRBHB instruction or ECBHB), +but it still seems good to have all the info from ARM's whitepaper +included. + +[1] https://developer.arm.com/Arm%20Security%20Center/Spectre-BHB + +Fixes: 558c303c9734 ("arm64: Mitigate spectre style branch history side channels") +Cc: stable@vger.kernel.org +Signed-off-by: Douglas Anderson +Reviewed-by: James Morse +Link: https://lore.kernel.org/r/20250107120555.v4.5.I4a9a527e03f663040721c5401c41de587d015c82@changeid +Signed-off-by: Catalin Marinas +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/kernel/proton-pack.c | 15 ++++++++++++++- + 1 file changed, 14 insertions(+), 1 deletion(-) + +--- a/arch/arm64/kernel/proton-pack.c ++++ b/arch/arm64/kernel/proton-pack.c +@@ -876,6 +876,14 @@ static u8 spectre_bhb_loop_affected(void + { + u8 k = 0; + ++ static const struct midr_range spectre_bhb_k132_list[] = { ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_X3), ++ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2), ++ }; ++ static const struct midr_range spectre_bhb_k38_list[] = { ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A720), ++ }; + static const struct midr_range spectre_bhb_k32_list[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A78AE), +@@ -889,6 +897,7 @@ static u8 spectre_bhb_loop_affected(void + }; + static const struct midr_range spectre_bhb_k24_list[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), ++ MIDR_ALL_VERSIONS(MIDR_CORTEX_A76AE), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), + MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_GOLD), +@@ -904,7 +913,11 @@ static u8 spectre_bhb_loop_affected(void + {}, + }; + +- if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k32_list)) ++ if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k132_list)) ++ k = 132; ++ else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k38_list)) ++ k = 38; ++ else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k32_list)) + k = 32; + else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list)) + k = 24; diff --git a/queue-6.6/series b/queue-6.6/series index 70133ae5f1..f134e2c349 100644 --- a/queue-6.6/series +++ b/queue-6.6/series @@ -230,3 +230,4 @@ phy-freescale-imx8m-pcie-assert-phy-reset-and-perst-in-power-off.patch pinctrl-qcom-clear-latched-interrupt-status-when-changing-irq-type.patch selftests-mptcp-close-fd_in-before-returning-in-main_loop.patch selftests-mptcp-fix-incorrect-fd-checks-in-main_loop.patch +arm64-errata-add-newer-arm-cores-to-the-spectre_bhb_loop_affected-lists.patch -- 2.47.3