From 17d066fc5db1a6f137e5b3113d918e14b1bd0230 Mon Sep 17 00:00:00 2001 From: Ashish Kumar Date: Thu, 31 Aug 2017 16:37:31 +0530 Subject: [PATCH] armv8: fsl-layerscape: Support to add RGMII for ls1088aqds This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Amrita Kumari Signed-off-by: Ashish Kumar Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 21 +++++++++++++++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 +++ .../asm/arch-fsl-layerscape/fsl_serdes.h | 1 + .../asm/arch-fsl-layerscape/immap_lsch3.h | 6 +++++ board/freescale/ls1088a/eth_ls1088aqds.c | 1 - drivers/net/ldpaa_eth/ldpaa_wriop.c | 9 +++++++ drivers/net/ldpaa_eth/ls1088a.c | 27 +++++++++++++++++++ include/fsl-mc/ldpaa_wriop.h | 2 ++ 8 files changed, 70 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index ca8cdd8f37..82d61600e1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -57,6 +57,8 @@ config ARCH_LS1088A select SYS_FSL_DDR select SYS_FSL_DDR_LE select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 select SYS_FSL_ERRATUM_A009803 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 @@ -64,6 +66,7 @@ config ARCH_LS1088A select SYS_FSL_ERRATUM_A008850 select SYS_FSL_HAS_CCI400 select SYS_FSL_HAS_DDR4 + select SYS_FSL_HAS_RGMII select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE @@ -407,6 +410,18 @@ config RESV_RAM be at the high end of physical memory. The reserve RAM may be excluded from memory bank(s) passed to OS, or marked as reserved. +config SYS_FSL_EC1 + bool + help + Ethernet controller 1, this is connected to MAC3. + Provides DPAA2 capabilities + +config SYS_FSL_EC2 + bool + help + Ethernet controller 2, this is connected to MAC4. + Provides DPAA2 capabilities + config SYS_FSL_ERRATUM_A008336 bool @@ -431,6 +446,12 @@ config SYS_FSL_ERRATUM_A009660 config SYS_FSL_ERRATUM_A009929 bool + +config SYS_FSL_HAS_RGMII + bool + depends on SYS_FSL_EC1 || SYS_FSL_EC2 + + config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index ec5806517a..3c9a5edc8b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -517,6 +517,10 @@ int arch_early_init_r(void) printf("Did not wake secondary cores\n"); } +#ifdef CONFIG_SYS_FSL_HAS_RGMII + fsl_rgmii_init(); +#endif + #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index a2c7578311..12fd6b8bdf 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -159,6 +159,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device); enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); int is_serdes_prtcl_valid(int serdes, u32 prtcl); int serdes_get_number(int serdes, int cfg); +void fsl_rgmii_init(void); #ifdef CONFIG_FSL_LSCH2 const char *serdes_clock_to_string(u32 clock); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 99a7413611..ffc5fa2636 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -247,6 +247,12 @@ struct ccsr_gur { #define FSL_CHASSIS3_SRDS1_REGSR 29 #define FSL_CHASSIS3_SRDS2_REGSR 29 #elif defined(CONFIG_ARCH_LS1088A) +#define FSL_CHASSIS3_EC1_REGSR 26 +#define FSL_CHASSIS3_EC2_REGSR 26 +#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007 +#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0 +#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038 +#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index a912ff7330..a973457ea7 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -597,7 +597,6 @@ int board_eth_init(bd_t *bis) /* Register the real MDIO1 bus */ fm_memac_mdio_init(bis, memac_mdio0_info); - /* Register the muxing front-ends to the MDIO buses */ ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1); ls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2); diff --git a/drivers/net/ldpaa_eth/ldpaa_wriop.c b/drivers/net/ldpaa_eth/ldpaa_wriop.c index f7f26c275d..831a330070 100644 --- a/drivers/net/ldpaa_eth/ldpaa_wriop.c +++ b/drivers/net/ldpaa_eth/ldpaa_wriop.c @@ -37,6 +37,15 @@ void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl) } } +void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if) +{ + dpmac_info[dpmac_id].enabled = 1; + dpmac_info[dpmac_id].id = dpmac_id; + dpmac_info[dpmac_id].phy_addr = -1; + dpmac_info[dpmac_id].enet_if = enet_if; +} + + /*TODO what it do */ static int wriop_dpmac_to_index(int dpmac_id) { diff --git a/drivers/net/ldpaa_eth/ls1088a.c b/drivers/net/ldpaa_eth/ls1088a.c index 703945cec3..061935e51c 100644 --- a/drivers/net/ldpaa_eth/ls1088a.c +++ b/drivers/net/ldpaa_eth/ls1088a.c @@ -8,6 +8,7 @@ #include #include #include +#include u32 dpmac_to_devdisr[] = { [WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1, @@ -85,3 +86,29 @@ void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) break; } } + +#ifdef CONFIG_SYS_FSL_HAS_RGMII +void fsl_rgmii_init(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 ec; + +#ifdef CONFIG_SYS_FSL_EC1 + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1]) + & FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK; + ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT; + + if (!ec) + wriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII); +#endif + +#ifdef CONFIG_SYS_FSL_EC2 + ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1]) + & FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK; + ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT; + + if (!ec) + wriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII); +#endif +} +#endif diff --git a/include/fsl-mc/ldpaa_wriop.h b/include/fsl-mc/ldpaa_wriop.h index 8ae0fc071e..0ca49564a9 100644 --- a/include/fsl-mc/ldpaa_wriop.h +++ b/include/fsl-mc/ldpaa_wriop.h @@ -69,4 +69,6 @@ void wriop_dpmac_disable(int); void wriop_dpmac_enable(int); phy_interface_t wriop_dpmac_enet_if(int, int); void wriop_init_dpmac_qsgmii(int, int); +void wriop_init_rgmii(void); +void wriop_init_dpmac_enet_if(int , phy_interface_t); #endif /* __LDPAA_WRIOP_H */ -- 2.39.2