From 1a0f175dd76526d94996cafb539a976bcba9971c Mon Sep 17 00:00:00 2001 From: Ruan Beihong Date: Thu, 13 Nov 2008 22:48:39 +0000 Subject: [PATCH] loongson.md (div3, [...]): New patterns. gcc/ 2008-11-13 Ruan Beihong * config/mips/loongson.md (div3, mod3): New patterns. * config/mips/loongson2ef.md (ls2_imult): Handle imul3nc. (ls2_idiv): Likewise idiv3. (ls2_prefetch): New reservation. * config/mips/mips.h (ISA_HAS_PREFETCH): Add TARGET_LOONGSON_2EF. * config/mips/mips.md (type): Add imul3nc and idiv3. (length): Handle idiv3. (any_mod): New code_iterator. (u): Handle MOD and UMOD. (mul3): Generate mul3_mul3_ls2ef on Loongson targets. (prefetch): Handle TARGET_LOONGSON_2EF. From-SVN: r141835 --- gcc/ChangeLog | 14 ++++++++++++++ gcc/config/mips/loongson.md | 20 ++++++++++++++++++++ gcc/config/mips/loongson2ef.md | 9 +++++++-- gcc/config/mips/mips.h | 1 + gcc/config/mips/mips.md | 34 ++++++++++++++++++++++++++++------ 5 files changed, 70 insertions(+), 8 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7698bddd1153..ece73ea4ca09 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,17 @@ +2008-11-13 Ruan Beihong + + * config/mips/loongson.md (div3, mod3): New patterns. + * config/mips/loongson2ef.md (ls2_imult): Handle imul3nc. + (ls2_idiv): Likewise idiv3. + (ls2_prefetch): New reservation. + * config/mips/mips.h (ISA_HAS_PREFETCH): Add TARGET_LOONGSON_2EF. + * config/mips/mips.md (type): Add imul3nc and idiv3. + (length): Handle idiv3. + (any_mod): New code_iterator. + (u): Handle MOD and UMOD. + (mul3): Generate mul3_mul3_ls2ef on Loongson targets. + (prefetch): Handle TARGET_LOONGSON_2EF. + 2008-11-13 Jakub Jelinek PR c++/27017 diff --git a/gcc/config/mips/loongson.md b/gcc/config/mips/loongson.md index 98b5113fbb56..8cdb5f466e9c 100644 --- a/gcc/config/mips/loongson.md +++ b/gcc/config/mips/loongson.md @@ -473,3 +473,23 @@ "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS" "punpckl\t%0,%1,%2" [(set_attr "type" "fdiv")]) + +;; Integer division and modulus. + +(define_insn "div3" + [(set (match_operand:GPR 0 "register_operand" "=&d") + (any_div:GPR (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "register_operand" "d")))] + "TARGET_LOONGSON_2EF" + { return mips_output_division ("div.g\t%0,%1,%2", operands); } + [(set_attr "type" "idiv3") + (set_attr "mode" "")]) + +(define_insn "mod3" + [(set (match_operand:GPR 0 "register_operand" "=&d") + (any_mod:GPR (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "register_operand" "d")))] + "TARGET_LOONGSON_2EF" + { return mips_output_division ("mod.g\t%0,%1,%2", operands); } + [(set_attr "type" "idiv3") + (set_attr "mode" "")]) diff --git a/gcc/config/mips/loongson2ef.md b/gcc/config/mips/loongson2ef.md index 8d2948221022..df3de33f809f 100644 --- a/gcc/config/mips/loongson2ef.md +++ b/gcc/config/mips/loongson2ef.md @@ -160,14 +160,14 @@ ;; Reservation for integer multiplication instructions. (define_insn_reservation "ls2_imult" 5 (and (eq_attr "cpu" "loongson_2e,loongson_2f") - (eq_attr "type" "imul,imul3")) + (eq_attr "type" "imul,imul3nc")) "ls2_alu2,ls2_alu2_core") ;; Reservation for integer division / remainder instructions. ;; These instructions use the SRT algorithm and hence take 2-38 cycles. (define_insn_reservation "ls2_idiv" 20 (and (eq_attr "cpu" "loongson_2e,loongson_2f") - (eq_attr "type" "idiv")) + (eq_attr "type" "idiv,idiv3")) "ls2_alu2,ls2_alu2_core*18") ;; Reservation for memory load instructions. @@ -176,6 +176,11 @@ (eq_attr "type" "load,fpload,mfc,mtc")) "ls2_mem") +(define_insn_reservation "ls2_prefetch" 0 + (and (eq_attr "cpu" "loongson_2e,loongson_2f") + (eq_attr "type" "prefetch,prefetchx")) + "ls2_mem") + ;; Reservation for memory store instructions. ;; With stores we assume they don't alias with dependent loads. ;; Therefore we set the latency to zero. diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index bf2e0d0fae7b..354c4c5f1c37 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -919,6 +919,7 @@ enum mips_code_readable_setting { /* ISA has data prefetch instructions. This controls use of 'pref'. */ #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ + || TARGET_LOONGSON_2EF \ || ISA_MIPS32 \ || ISA_MIPS32R2 \ || ISA_MIPS64 \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 3f56feb2ee9f..222e41d7369a 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -351,8 +351,10 @@ ;; trap trap if instructions ;; imul integer multiply 2 operands ;; imul3 integer multiply 3 operands +;; imul3nc integer multiply 3 operands without clobbering HI/LO ;; imadd integer multiply-add -;; idiv integer divide +;; idiv integer divide 2 operands +;; idiv3 integer divide 3 operands ;; move integer register move ({,D}ADD{,U} with rt = 0) ;; fmove floating point register move ;; fadd floating point add/subtract @@ -376,9 +378,9 @@ (define_attr "type" "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore, prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical, - shift,slt,signext,clz,pop,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul, - fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1, - frsqrt2,multi,nop,ghost" + shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move, + fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt, + frsqrt,frsqrt1,frsqrt2,multi,nop,ghost" (cond [(eq_attr "jal" "!unset") (const_string "call") (eq_attr "got" "load") (const_string "load") @@ -553,7 +555,7 @@ (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))) (const_int 8) - (eq_attr "type" "idiv") + (eq_attr "type" "idiv,idiv3") (symbol_ref "mips_idiv_insns () * 4") ] (const_int 4))) @@ -787,6 +789,10 @@ ;; from the same template. (define_code_iterator any_div [div udiv]) +;; This code iterator allows unsigned and signed modulus to be generated +;; from the same template. +(define_code_iterator any_mod [mod umod]) + ;; This code iterator allows all native floating-point comparisons to be ;; generated from the same template. (define_code_iterator fcond [unordered uneq unlt unle eq lt le]) @@ -809,6 +815,7 @@ ;; "u" when doing an unsigned operation. (define_code_attr u [(sign_extend "") (zero_extend "u") (div "") (udiv "u") + (mod "") (umod "u") (gt "") (gtu "u") (ge "") (geu "u") (lt "") (ltu "u") @@ -1357,7 +1364,10 @@ (match_operand:GPR 2 "register_operand")))] "" { - if (ISA_HAS_MUL3) + if (TARGET_LOONGSON_2EF) + emit_insn (gen_mul3_mul3_ls2ef (operands[0], operands[1], + operands[2])); + else if (ISA_HAS_MUL3) emit_insn (gen_mul3_mul3 (operands[0], operands[1], operands[2])); else if (TARGET_FIX_R4000) emit_insn (gen_mul3_r4000 (operands[0], operands[1], operands[2])); @@ -1367,6 +1377,15 @@ DONE; }) +(define_insn "mul3_mul3_ls2ef" + [(set (match_operand:GPR 0 "register_operand" "=d") + (mult:GPR (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "register_operand" "d")))] + "TARGET_LOONGSON_2EF" + "multu.g\t%0,%1,%2" + [(set_attr "type" "imul3nc") + (set_attr "mode" "")]) + (define_insn "mul3_mul3" [(set (match_operand:GPR 0 "register_operand" "=d,l") (mult:GPR (match_operand:GPR 1 "register_operand" "d,d") @@ -6128,6 +6147,9 @@ (match_operand 2 "const_int_operand" "n"))] "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS" { + if (TARGET_LOONGSON_2EF) + /* Loongson 2[ef] use load to $0 to perform prefetching. */ + return "ld\t$0,%a0"; operands[1] = mips_prefetch_cookie (operands[1], operands[2]); return "pref\t%1,%a0"; } -- 2.39.2