From 222e938f5ef516f3a7dc2cac6bb3a73342635fa7 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 10 Mar 2023 11:32:39 +0100 Subject: [PATCH] drop mtd patch from 5.4 and 5.10 --- ...elbc-propagate-hw-ecc-settings-to-hw.patch | 69 ------------------- queue-5.10/series | 1 - ...elbc-propagate-hw-ecc-settings-to-hw.patch | 69 ------------------- queue-5.4/series | 1 - 4 files changed, 140 deletions(-) delete mode 100644 queue-5.10/mtd-rawnand-fsl_elbc-propagate-hw-ecc-settings-to-hw.patch delete mode 100644 queue-5.4/mtd-rawnand-fsl_elbc-propagate-hw-ecc-settings-to-hw.patch diff --git a/queue-5.10/mtd-rawnand-fsl_elbc-propagate-hw-ecc-settings-to-hw.patch b/queue-5.10/mtd-rawnand-fsl_elbc-propagate-hw-ecc-settings-to-hw.patch deleted file mode 100644 index d101e2e5d7b..00000000000 --- a/queue-5.10/mtd-rawnand-fsl_elbc-propagate-hw-ecc-settings-to-hw.patch +++ /dev/null @@ -1,69 +0,0 @@ -From a59c0b490c3923e0c00dc591654709641cf9e4a1 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Sat, 28 Jan 2023 14:41:11 +0100 -Subject: mtd: rawnand: fsl_elbc: Propagate HW ECC settings to HW -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -From: Pali Rohár - -[ Upstream commit b56265257d38af5abf43bd5461ca166b401c35a5 ] - -It is possible that current chip->ecc.engine_type value does not match to -configured HW value (if HW ECC checking and generating is enabled or not). - -This can happen with old U-Boot bootloader version which either does not -initialize NAND (and let it in some default unusable state) or initialize -NAND with different parameters than what is specified in kernel DTS file. - -So if kernel chose to use some chip->ecc.engine_type settings (e.g. from -DTS file) then do not depend on bootloader HW configuration and configures -HW ECC settings according to chip->ecc.engine_type value. - -BR_DECC must be set to BR_DECC_CHK_GEN when HW is doing ECC (both -generating and checking), or to BR_DECC_OFF when HW is not doing ECC. - -This change fixes usage of SW ECC support in case bootloader explicitly -enabled HW ECC support and kernel DTS file has specified to use SW ECC. -(Of course this works only in case when NAND is not a boot device and both -bootloader and kernel are loaded from different location, e.g. FLASH NOR.) - -Fixes: f6424c22aa36 ("mtd: rawnand: fsl_elbc: Make SW ECC work") -Signed-off-by: Pali Rohár -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20230128134111.32559-1-pali@kernel.org -Signed-off-by: Sasha Levin ---- - drivers/mtd/nand/raw/fsl_elbc_nand.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c -index c174b6dc3c6ba..093019455f5b0 100644 ---- a/drivers/mtd/nand/raw/fsl_elbc_nand.c -+++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c -@@ -726,6 +726,7 @@ static int fsl_elbc_attach_chip(struct nand_chip *chip) - struct fsl_lbc_ctrl *ctrl = priv->ctrl; - struct fsl_lbc_regs __iomem *lbc = ctrl->regs; - unsigned int al; -+ u32 br; - - /* - * if ECC was not chosen in DT, decide whether to use HW or SW ECC from -@@ -765,6 +766,13 @@ static int fsl_elbc_attach_chip(struct nand_chip *chip) - return -EINVAL; - } - -+ /* enable/disable HW ECC checking and generating based on if HW ECC was chosen */ -+ br = in_be32(&lbc->bank[priv->bank].br) & ~BR_DECC; -+ if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) -+ out_be32(&lbc->bank[priv->bank].br, br | BR_DECC_CHK_GEN); -+ else -+ out_be32(&lbc->bank[priv->bank].br, br | BR_DECC_OFF); -+ - /* calculate FMR Address Length field */ - al = 0; - if (chip->pagemask & 0xffff0000) --- -2.39.2 - diff --git a/queue-5.10/series b/queue-5.10/series index d3a65958aed..f17ae4421bc 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -244,7 +244,6 @@ input-ads7846-convert-to-full-duplex.patch input-ads7846-convert-to-one-message.patch input-ads7846-always-set-last-command-to-pwrdown.patch input-ads7846-don-t-check-penirq-immediately-for-784.patch -mtd-rawnand-fsl_elbc-propagate-hw-ecc-settings-to-hw.patch clk-qcom-gpucc-sc7180-fix-clk_dis_wait-being-program.patch clk-qcom-gpucc-sdm845-fix-clk_dis_wait-being-program.patch powerpc-powernv-ioda-skip-unallocated-resources-when.patch diff --git a/queue-5.4/mtd-rawnand-fsl_elbc-propagate-hw-ecc-settings-to-hw.patch b/queue-5.4/mtd-rawnand-fsl_elbc-propagate-hw-ecc-settings-to-hw.patch deleted file mode 100644 index c8b0d3e5071..00000000000 --- a/queue-5.4/mtd-rawnand-fsl_elbc-propagate-hw-ecc-settings-to-hw.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 839c09472742b383f65eb7c1f7e576ebfb6a1f62 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Sat, 28 Jan 2023 14:41:11 +0100 -Subject: mtd: rawnand: fsl_elbc: Propagate HW ECC settings to HW -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -From: Pali Rohár - -[ Upstream commit b56265257d38af5abf43bd5461ca166b401c35a5 ] - -It is possible that current chip->ecc.engine_type value does not match to -configured HW value (if HW ECC checking and generating is enabled or not). - -This can happen with old U-Boot bootloader version which either does not -initialize NAND (and let it in some default unusable state) or initialize -NAND with different parameters than what is specified in kernel DTS file. - -So if kernel chose to use some chip->ecc.engine_type settings (e.g. from -DTS file) then do not depend on bootloader HW configuration and configures -HW ECC settings according to chip->ecc.engine_type value. - -BR_DECC must be set to BR_DECC_CHK_GEN when HW is doing ECC (both -generating and checking), or to BR_DECC_OFF when HW is not doing ECC. - -This change fixes usage of SW ECC support in case bootloader explicitly -enabled HW ECC support and kernel DTS file has specified to use SW ECC. -(Of course this works only in case when NAND is not a boot device and both -bootloader and kernel are loaded from different location, e.g. FLASH NOR.) - -Fixes: f6424c22aa36 ("mtd: rawnand: fsl_elbc: Make SW ECC work") -Signed-off-by: Pali Rohár -Signed-off-by: Miquel Raynal -Link: https://lore.kernel.org/linux-mtd/20230128134111.32559-1-pali@kernel.org -Signed-off-by: Sasha Levin ---- - drivers/mtd/nand/raw/fsl_elbc_nand.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c -index 634c550db13a7..e900c0eddc21d 100644 ---- a/drivers/mtd/nand/raw/fsl_elbc_nand.c -+++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c -@@ -727,6 +727,7 @@ static int fsl_elbc_attach_chip(struct nand_chip *chip) - struct fsl_lbc_ctrl *ctrl = priv->ctrl; - struct fsl_lbc_regs __iomem *lbc = ctrl->regs; - unsigned int al; -+ u32 br; - - switch (chip->ecc.mode) { - /* -@@ -762,6 +763,13 @@ static int fsl_elbc_attach_chip(struct nand_chip *chip) - return -EINVAL; - } - -+ /* enable/disable HW ECC checking and generating based on if HW ECC was chosen */ -+ br = in_be32(&lbc->bank[priv->bank].br) & ~BR_DECC; -+ if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) -+ out_be32(&lbc->bank[priv->bank].br, br | BR_DECC_CHK_GEN); -+ else -+ out_be32(&lbc->bank[priv->bank].br, br | BR_DECC_OFF); -+ - /* calculate FMR Address Length field */ - al = 0; - if (chip->pagemask & 0xffff0000) --- -2.39.2 - diff --git a/queue-5.4/series b/queue-5.4/series index 120296a2245..66fb7933bee 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -153,7 +153,6 @@ clk-renesas-cpg-mssr-use-enum-clk_reg_layout-instead.patch clk-renesas-cpg-mssr-remove-superfluous-check-in-res.patch input-ads7846-don-t-report-pressure-for-ads7845.patch input-ads7846-don-t-check-penirq-immediately-for-784.patch -mtd-rawnand-fsl_elbc-propagate-hw-ecc-settings-to-hw.patch clk-qcom-gpucc-sdm845-fix-clk_dis_wait-being-program.patch powerpc-powernv-ioda-skip-unallocated-resources-when.patch clk-honor-clk_ops_parent_enable-in-clk_core_is_enabl.patch -- 2.47.3