From 234174ad4080ac5a66cd532780c33850b2a7c100 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 22 Apr 2025 09:16:58 +0200 Subject: [PATCH] 6.12-stable patches added patches: arm64-boot-enable-el2-requirements-for-feat_pmuv3p9.patch arm64-sysreg-add-register-fields-for-hdfgrtr2_el2.patch arm64-sysreg-add-register-fields-for-hdfgwtr2_el2.patch arm64-sysreg-add-register-fields-for-hfgitr2_el2.patch arm64-sysreg-add-register-fields-for-hfgrtr2_el2.patch arm64-sysreg-add-register-fields-for-hfgwtr2_el2.patch arm64-sysreg-update-register-fields-for-id_aa64mmfr0_el1.patch --- ...le-el2-requirements-for-feat_pmuv3p9.patch | 139 ++++++++++++++++++ ...add-register-fields-for-hdfgrtr2_el2.patch | 68 +++++++++ ...add-register-fields-for-hdfgwtr2_el2.patch | 67 +++++++++ ...-add-register-fields-for-hfgitr2_el2.patch | 45 ++++++ ...-add-register-fields-for-hfgrtr2_el2.patch | 58 ++++++++ ...-add-register-fields-for-hfgwtr2_el2.patch | 58 ++++++++ ...register-fields-for-id_aa64mmfr0_el1.patch | 48 ++++++ queue-6.12/series | 7 + 8 files changed, 490 insertions(+) create mode 100644 queue-6.12/arm64-boot-enable-el2-requirements-for-feat_pmuv3p9.patch create mode 100644 queue-6.12/arm64-sysreg-add-register-fields-for-hdfgrtr2_el2.patch create mode 100644 queue-6.12/arm64-sysreg-add-register-fields-for-hdfgwtr2_el2.patch create mode 100644 queue-6.12/arm64-sysreg-add-register-fields-for-hfgitr2_el2.patch create mode 100644 queue-6.12/arm64-sysreg-add-register-fields-for-hfgrtr2_el2.patch create mode 100644 queue-6.12/arm64-sysreg-add-register-fields-for-hfgwtr2_el2.patch create mode 100644 queue-6.12/arm64-sysreg-update-register-fields-for-id_aa64mmfr0_el1.patch diff --git a/queue-6.12/arm64-boot-enable-el2-requirements-for-feat_pmuv3p9.patch b/queue-6.12/arm64-boot-enable-el2-requirements-for-feat_pmuv3p9.patch new file mode 100644 index 0000000000..a4978f882f --- /dev/null +++ b/queue-6.12/arm64-boot-enable-el2-requirements-for-feat_pmuv3p9.patch @@ -0,0 +1,139 @@ +From stable+bounces-132691-greg=kroah.com@vger.kernel.org Tue Apr 15 06:58:05 2025 +From: Anshuman Khandual +Date: Tue, 15 Apr 2025 10:27:28 +0530 +Subject: arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9 +To: stable@vger.kernel.org, gregkh@linuxfoundation.org +Cc: catalin.marinas@arm.com, will@kernel.org, robh@kernel.org, mark.rutland@arm.com, anshuman.khandual@arm.com +Message-ID: <20250415045728.2248935-8-anshuman.khandual@arm.com> + +From: Anshuman Khandual + +commit 858c7bfcb35e1100b58bb63c9f562d86e09418d9 upstream. + +FEAT_PMUv3p9 registers such as PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 +access from EL1 requires appropriate EL2 fine grained trap configuration +via FEAT_FGT2 based trap control registers HDFGRTR2_EL2 and HDFGWTR2_EL2. +Otherwise such register accesses will result in traps into EL2. + +Add a new helper __init_el2_fgt2() which initializes FEAT_FGT2 based fine +grained trap control registers HDFGRTR2_EL2 and HDFGWTR2_EL2 (setting the +bits nPMICNTR_EL0, nPMICFILTR_EL0 and nPMUACR_EL1) to enable access into +PMICNTR_EL0, PMICFILTR_EL0, and PMUACR_EL1 registers. + +Also update booting.rst with SCR_EL3.FGTEn2 requirement for all FEAT_FGT2 +based registers to be accessible in EL2. + +Cc: Will Deacon +Cc: Mark Rutland +Cc: Rob Herring +Cc: Jonathan Corbet +Cc: Marc Zyngier +Cc: Oliver Upton +Cc: linux-arm-kernel@lists.infradead.org +Cc: linux-doc@vger.kernel.org +Cc: linux-kernel@vger.kernel.org +Cc: kvmarm@lists.linux.dev +Fixes: 0bbff9ed8165 ("perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control") +Fixes: d8226d8cfbaf ("perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counter") +Tested-by: Rob Herring (Arm) +Reviewed-by: Rob Herring (Arm) +Signed-off-by: Anshuman Khandual +Link: https://lore.kernel.org/r/20250227035119.2025171-1-anshuman.khandual@arm.com +Signed-off-by: Catalin Marinas +Signed-off-by: Anshuman Khandual +Signed-off-by: Greg Kroah-Hartman +--- + Documentation/arch/arm64/booting.rst | 22 ++++++++++++++++++++++ + arch/arm64/include/asm/el2_setup.h | 25 +++++++++++++++++++++++++ + arch/arm64/tools/sysreg | 1 + + 3 files changed, 48 insertions(+) + +--- a/Documentation/arch/arm64/booting.rst ++++ b/Documentation/arch/arm64/booting.rst +@@ -285,6 +285,12 @@ Before jumping into the kernel, the foll + + - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1. + ++ For CPUs with the Fine Grained Traps 2 (FEAT_FGT2) extension present: ++ ++ - If EL3 is present and the kernel is entered at EL2: ++ ++ - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1. ++ + For CPUs with support for HCRX_EL2 (FEAT_HCX) present: + + - If EL3 is present and the kernel is entered at EL2: +@@ -379,6 +385,22 @@ Before jumping into the kernel, the foll + + - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1. + ++ For CPUs with the Performance Monitors Extension (FEAT_PMUv3p9): ++ ++ - If EL3 is present: ++ ++ - MDCR_EL3.EnPM2 (bit 7) must be initialised to 0b1. ++ ++ - If the kernel is entered at EL1 and EL2 is present: ++ ++ - HDFGRTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1. ++ - HDFGRTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1. ++ - HDFGRTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1. ++ ++ - HDFGWTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1. ++ - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1. ++ - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1. ++ + For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS): + + - If the kernel is entered at EL1 and EL2 is present: +--- a/arch/arm64/include/asm/el2_setup.h ++++ b/arch/arm64/include/asm/el2_setup.h +@@ -215,6 +215,30 @@ + .Lskip_fgt_\@: + .endm + ++.macro __init_el2_fgt2 ++ mrs x1, id_aa64mmfr0_el1 ++ ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 ++ cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2 ++ b.lt .Lskip_fgt2_\@ ++ ++ mov x0, xzr ++ mrs x1, id_aa64dfr0_el1 ++ ubfx x1, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 ++ cmp x1, #ID_AA64DFR0_EL1_PMUVer_V3P9 ++ b.lt .Lskip_pmuv3p9_\@ ++ ++ orr x0, x0, #HDFGRTR2_EL2_nPMICNTR_EL0 ++ orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0 ++ orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1 ++.Lskip_pmuv3p9_\@: ++ msr_s SYS_HDFGRTR2_EL2, x0 ++ msr_s SYS_HDFGWTR2_EL2, x0 ++ msr_s SYS_HFGRTR2_EL2, xzr ++ msr_s SYS_HFGWTR2_EL2, xzr ++ msr_s SYS_HFGITR2_EL2, xzr ++.Lskip_fgt2_\@: ++.endm ++ + .macro __init_el2_nvhe_prepare_eret + mov x0, #INIT_PSTATE_EL1 + msr spsr_el2, x0 +@@ -240,6 +264,7 @@ + __init_el2_nvhe_idregs + __init_el2_cptr + __init_el2_fgt ++ __init_el2_fgt2 + .endm + + #ifndef __KVM_NVHE_HYPERVISOR__ +--- a/arch/arm64/tools/sysreg ++++ b/arch/arm64/tools/sysreg +@@ -1238,6 +1238,7 @@ UnsignedEnum 11:8 PMUVer + 0b0110 V3P5 + 0b0111 V3P7 + 0b1000 V3P8 ++ 0b1001 V3P9 + 0b1111 IMP_DEF + EndEnum + UnsignedEnum 7:4 TraceVer diff --git a/queue-6.12/arm64-sysreg-add-register-fields-for-hdfgrtr2_el2.patch b/queue-6.12/arm64-sysreg-add-register-fields-for-hdfgrtr2_el2.patch new file mode 100644 index 0000000000..5bd1c17c7a --- /dev/null +++ b/queue-6.12/arm64-sysreg-add-register-fields-for-hdfgrtr2_el2.patch @@ -0,0 +1,68 @@ +From stable+bounces-132686-greg=kroah.com@vger.kernel.org Tue Apr 15 06:57:48 2025 +From: Anshuman Khandual +Date: Tue, 15 Apr 2025 10:27:23 +0530 +Subject: arm64/sysreg: Add register fields for HDFGRTR2_EL2 +To: stable@vger.kernel.org, gregkh@linuxfoundation.org +Cc: catalin.marinas@arm.com, will@kernel.org, robh@kernel.org, mark.rutland@arm.com, anshuman.khandual@arm.com +Message-ID: <20250415045728.2248935-3-anshuman.khandual@arm.com> + +From: Anshuman Khandual + +commit 44844551670cff70a8aa5c1cde27ad1e0367e009 upstream. + +This adds register fields for HDFGRTR2_EL2 as per the definitions based +on DDI0601 2024-12. + +Cc: Will Deacon +Cc: Mark Brown +Cc: linux-arm-kernel@lists.infradead.org +Cc: linux-kernel@vger.kernel.org +Reviewed-by: Eric Auger +Reviewed-by: Mark Brown +Signed-off-by: Anshuman Khandual +Link: https://lore.kernel.org/r/20250203050828.1049370-3-anshuman.khandual@arm.com +Signed-off-by: Catalin Marinas +Signed-off-by: Anshuman Khandual +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/tools/sysreg | 29 +++++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +--- a/arch/arm64/tools/sysreg ++++ b/arch/arm64/tools/sysreg +@@ -2465,6 +2465,35 @@ Field 1 ICIALLU + Field 0 ICIALLUIS + EndSysreg + ++Sysreg HDFGRTR2_EL2 3 4 3 1 0 ++Res0 63:25 ++Field 24 nPMBMAR_EL1 ++Field 23 nMDSTEPOP_EL1 ++Field 22 nTRBMPAM_EL1 ++Res0 21 ++Field 20 nTRCITECR_EL1 ++Field 19 nPMSDSFR_EL1 ++Field 18 nSPMDEVAFF_EL1 ++Field 17 nSPMID ++Field 16 nSPMSCR_EL1 ++Field 15 nSPMACCESSR_EL1 ++Field 14 nSPMCR_EL0 ++Field 13 nSPMOVS ++Field 12 nSPMINTEN ++Field 11 nSPMCNTEN ++Field 10 nSPMSELR_EL0 ++Field 9 nSPMEVTYPERn_EL0 ++Field 8 nSPMEVCNTRn_EL0 ++Field 7 nPMSSCR_EL1 ++Field 6 nPMSSDATA ++Field 5 nMDSELR_EL1 ++Field 4 nPMUACR_EL1 ++Field 3 nPMICFILTR_EL0 ++Field 2 nPMICNTR_EL0 ++Field 1 nPMIAR_EL1 ++Field 0 nPMECR_EL1 ++EndSysreg ++ + Sysreg HDFGRTR_EL2 3 4 3 1 4 + Field 63 PMBIDR_EL1 + Field 62 nPMSNEVFR_EL1 diff --git a/queue-6.12/arm64-sysreg-add-register-fields-for-hdfgwtr2_el2.patch b/queue-6.12/arm64-sysreg-add-register-fields-for-hdfgwtr2_el2.patch new file mode 100644 index 0000000000..5b330ede00 --- /dev/null +++ b/queue-6.12/arm64-sysreg-add-register-fields-for-hdfgwtr2_el2.patch @@ -0,0 +1,67 @@ +From stable+bounces-132687-greg=kroah.com@vger.kernel.org Tue Apr 15 06:57:51 2025 +From: Anshuman Khandual +Date: Tue, 15 Apr 2025 10:27:24 +0530 +Subject: arm64/sysreg: Add register fields for HDFGWTR2_EL2 +To: stable@vger.kernel.org, gregkh@linuxfoundation.org +Cc: catalin.marinas@arm.com, will@kernel.org, robh@kernel.org, mark.rutland@arm.com, anshuman.khandual@arm.com +Message-ID: <20250415045728.2248935-4-anshuman.khandual@arm.com> + +From: Anshuman Khandual + +commit 2f1f62a1257b9d5eb98a8e161ea7d11f1678f7ad upstream. + +This adds register fields for HDFGWTR2_EL2 as per the definitions based +on DDI0601 2024-12. + +Cc: Will Deacon +Cc: Mark Brown +Cc: linux-arm-kernel@lists.infradead.org +Cc: linux-kernel@vger.kernel.org +Reviewed-by: Eric Auger +Reviewed-by: Mark Brown +Signed-off-by: Anshuman Khandual +Link: https://lore.kernel.org/r/20250203050828.1049370-4-anshuman.khandual@arm.com +Signed-off-by: Catalin Marinas +Signed-off-by: Anshuman Khandual +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ + 1 file changed, 28 insertions(+) + +--- a/arch/arm64/tools/sysreg ++++ b/arch/arm64/tools/sysreg +@@ -2494,6 +2494,34 @@ Field 1 nPMIAR_EL1 + Field 0 nPMECR_EL1 + EndSysreg + ++Sysreg HDFGWTR2_EL2 3 4 3 1 1 ++Res0 63:25 ++Field 24 nPMBMAR_EL1 ++Field 23 nMDSTEPOP_EL1 ++Field 22 nTRBMPAM_EL1 ++Field 21 nPMZR_EL0 ++Field 20 nTRCITECR_EL1 ++Field 19 nPMSDSFR_EL1 ++Res0 18:17 ++Field 16 nSPMSCR_EL1 ++Field 15 nSPMACCESSR_EL1 ++Field 14 nSPMCR_EL0 ++Field 13 nSPMOVS ++Field 12 nSPMINTEN ++Field 11 nSPMCNTEN ++Field 10 nSPMSELR_EL0 ++Field 9 nSPMEVTYPERn_EL0 ++Field 8 nSPMEVCNTRn_EL0 ++Field 7 nPMSSCR_EL1 ++Res0 6 ++Field 5 nMDSELR_EL1 ++Field 4 nPMUACR_EL1 ++Field 3 nPMICFILTR_EL0 ++Field 2 nPMICNTR_EL0 ++Field 1 nPMIAR_EL1 ++Field 0 nPMECR_EL1 ++EndSysreg ++ + Sysreg HDFGRTR_EL2 3 4 3 1 4 + Field 63 PMBIDR_EL1 + Field 62 nPMSNEVFR_EL1 diff --git a/queue-6.12/arm64-sysreg-add-register-fields-for-hfgitr2_el2.patch b/queue-6.12/arm64-sysreg-add-register-fields-for-hfgitr2_el2.patch new file mode 100644 index 0000000000..e667567616 --- /dev/null +++ b/queue-6.12/arm64-sysreg-add-register-fields-for-hfgitr2_el2.patch @@ -0,0 +1,45 @@ +From stable+bounces-132688-greg=kroah.com@vger.kernel.org Tue Apr 15 06:57:56 2025 +From: Anshuman Khandual +Date: Tue, 15 Apr 2025 10:27:25 +0530 +Subject: arm64/sysreg: Add register fields for HFGITR2_EL2 +To: stable@vger.kernel.org, gregkh@linuxfoundation.org +Cc: catalin.marinas@arm.com, will@kernel.org, robh@kernel.org, mark.rutland@arm.com, anshuman.khandual@arm.com +Message-ID: <20250415045728.2248935-5-anshuman.khandual@arm.com> + +From: Anshuman Khandual + +commit 9401476f17747586a8bfb29abfdf5ade7a8bceef upstream. + +This adds register fields for HFGITR2_EL2 as per the definitions based +on DDI0601 2024-12. + +Cc: Will Deacon +Cc: Mark Brown +Cc: linux-arm-kernel@lists.infradead.org +Cc: linux-kernel@vger.kernel.org +Reviewed-by: Eric Auger +Reviewed-by: Mark Brown +Signed-off-by: Anshuman Khandual +Link: https://lore.kernel.org/r/20250203050828.1049370-5-anshuman.khandual@arm.com +Signed-off-by: Catalin Marinas +Signed-off-by: Anshuman Khandual +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/tools/sysreg | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/arch/arm64/tools/sysreg ++++ b/arch/arm64/tools/sysreg +@@ -2694,6 +2694,12 @@ Field 1 AMEVCNTR00_EL0 + Field 0 AMCNTEN0 + EndSysreg + ++Sysreg HFGITR2_EL2 3 4 3 1 7 ++Res0 63:2 ++Field 1 nDCCIVAPS ++Field 0 TSBCSYNC ++EndSysreg ++ + Sysreg ZCR_EL2 3 4 1 2 0 + Fields ZCR_ELx + EndSysreg diff --git a/queue-6.12/arm64-sysreg-add-register-fields-for-hfgrtr2_el2.patch b/queue-6.12/arm64-sysreg-add-register-fields-for-hfgrtr2_el2.patch new file mode 100644 index 0000000000..4724756181 --- /dev/null +++ b/queue-6.12/arm64-sysreg-add-register-fields-for-hfgrtr2_el2.patch @@ -0,0 +1,58 @@ +From stable+bounces-132689-greg=kroah.com@vger.kernel.org Tue Apr 15 06:57:57 2025 +From: Anshuman Khandual +Date: Tue, 15 Apr 2025 10:27:26 +0530 +Subject: arm64/sysreg: Add register fields for HFGRTR2_EL2 +To: stable@vger.kernel.org, gregkh@linuxfoundation.org +Cc: catalin.marinas@arm.com, will@kernel.org, robh@kernel.org, mark.rutland@arm.com, anshuman.khandual@arm.com +Message-ID: <20250415045728.2248935-6-anshuman.khandual@arm.com> + +From: Anshuman Khandual + +commit 59236089ad5243377b6905d78e39ba4183dc35f5 upstream. + +This adds register fields for HFGRTR2_EL2 as per the definitions based +on DDI0601 2024-12. + +Cc: Will Deacon +Cc: Mark Brown +Cc: linux-arm-kernel@lists.infradead.org +Cc: linux-kernel@vger.kernel.org +Reviewed-by: Eric Auger +Reviewed-by: Mark Brown +Signed-off-by: Anshuman Khandual +Link: https://lore.kernel.org/r/20250203050828.1049370-6-anshuman.khandual@arm.com +Signed-off-by: Catalin Marinas +Signed-off-by: Anshuman Khandual +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/tools/sysreg | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/arch/arm64/tools/sysreg ++++ b/arch/arm64/tools/sysreg +@@ -2522,6 +2522,25 @@ Field 1 nPMIAR_EL1 + Field 0 nPMECR_EL1 + EndSysreg + ++Sysreg HFGRTR2_EL2 3 4 3 1 2 ++Res0 63:15 ++Field 14 nACTLRALIAS_EL1 ++Field 13 nACTLRMASK_EL1 ++Field 12 nTCR2ALIAS_EL1 ++Field 11 nTCRALIAS_EL1 ++Field 10 nSCTLRALIAS2_EL1 ++Field 9 nSCTLRALIAS_EL1 ++Field 8 nCPACRALIAS_EL1 ++Field 7 nTCR2MASK_EL1 ++Field 6 nTCRMASK_EL1 ++Field 5 nSCTLR2MASK_EL1 ++Field 4 nSCTLRMASK_EL1 ++Field 3 nCPACRMASK_EL1 ++Field 2 nRCWSMASK_EL1 ++Field 1 nERXGSR_EL1 ++Field 0 nPFAR_EL1 ++EndSysreg ++ + Sysreg HDFGRTR_EL2 3 4 3 1 4 + Field 63 PMBIDR_EL1 + Field 62 nPMSNEVFR_EL1 diff --git a/queue-6.12/arm64-sysreg-add-register-fields-for-hfgwtr2_el2.patch b/queue-6.12/arm64-sysreg-add-register-fields-for-hfgwtr2_el2.patch new file mode 100644 index 0000000000..b8d527573a --- /dev/null +++ b/queue-6.12/arm64-sysreg-add-register-fields-for-hfgwtr2_el2.patch @@ -0,0 +1,58 @@ +From stable+bounces-132690-greg=kroah.com@vger.kernel.org Tue Apr 15 06:58:04 2025 +From: Anshuman Khandual +Date: Tue, 15 Apr 2025 10:27:27 +0530 +Subject: arm64/sysreg: Add register fields for HFGWTR2_EL2 +To: stable@vger.kernel.org, gregkh@linuxfoundation.org +Cc: catalin.marinas@arm.com, will@kernel.org, robh@kernel.org, mark.rutland@arm.com, anshuman.khandual@arm.com +Message-ID: <20250415045728.2248935-7-anshuman.khandual@arm.com> + +From: Anshuman Khandual + +commit ea37be0773f04420515b8db49e50abedbaa97e23 upstream. + +This adds register fields for HFGWTR2_EL2 as per the definitions based +on DDI0601 2024-12. + +Cc: Will Deacon +Cc: Mark Brown +Cc: linux-arm-kernel@lists.infradead.org +Cc: linux-kernel@vger.kernel.org +Reviewed-by: Eric Auger +Reviewed-by: Mark Brown +Signed-off-by: Anshuman Khandual +Link: https://lore.kernel.org/r/20250203050828.1049370-7-anshuman.khandual@arm.com +Signed-off-by: Catalin Marinas +Signed-off-by: Anshuman Khandual +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/tools/sysreg | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/arch/arm64/tools/sysreg ++++ b/arch/arm64/tools/sysreg +@@ -2541,6 +2541,25 @@ Field 1 nERXGSR_EL1 + Field 0 nPFAR_EL1 + EndSysreg + ++Sysreg HFGWTR2_EL2 3 4 3 1 3 ++Res0 63:15 ++Field 14 nACTLRALIAS_EL1 ++Field 13 nACTLRMASK_EL1 ++Field 12 nTCR2ALIAS_EL1 ++Field 11 nTCRALIAS_EL1 ++Field 10 nSCTLRALIAS2_EL1 ++Field 9 nSCTLRALIAS_EL1 ++Field 8 nCPACRALIAS_EL1 ++Field 7 nTCR2MASK_EL1 ++Field 6 nTCRMASK_EL1 ++Field 5 nSCTLR2MASK_EL1 ++Field 4 nSCTLRMASK_EL1 ++Field 3 nCPACRMASK_EL1 ++Field 2 nRCWSMASK_EL1 ++Res0 1 ++Field 0 nPFAR_EL1 ++EndSysreg ++ + Sysreg HDFGRTR_EL2 3 4 3 1 4 + Field 63 PMBIDR_EL1 + Field 62 nPMSNEVFR_EL1 diff --git a/queue-6.12/arm64-sysreg-update-register-fields-for-id_aa64mmfr0_el1.patch b/queue-6.12/arm64-sysreg-update-register-fields-for-id_aa64mmfr0_el1.patch new file mode 100644 index 0000000000..aae5900d24 --- /dev/null +++ b/queue-6.12/arm64-sysreg-update-register-fields-for-id_aa64mmfr0_el1.patch @@ -0,0 +1,48 @@ +From stable+bounces-132685-greg=kroah.com@vger.kernel.org Tue Apr 15 06:57:44 2025 +From: Anshuman Khandual +Date: Tue, 15 Apr 2025 10:27:22 +0530 +Subject: arm64/sysreg: Update register fields for ID_AA64MMFR0_EL1 +To: stable@vger.kernel.org, gregkh@linuxfoundation.org +Cc: catalin.marinas@arm.com, will@kernel.org, robh@kernel.org, mark.rutland@arm.com, anshuman.khandual@arm.com +Message-ID: <20250415045728.2248935-2-anshuman.khandual@arm.com> + +From: Anshuman Khandual + +commit cc15f548cc77574bcd68425ae01a796659bd3705 upstream. + +This updates ID_AA64MMFR0_EL1 register fields as per the definitions based +on DDI0601 2024-12. + +Cc: Will Deacon +Cc: Mark Brown +Cc: linux-arm-kernel@lists.infradead.org +Cc: linux-kernel@vger.kernel.org +Reviewed-by: Eric Auger +Reviewed-by: Mark Brown +Signed-off-by: Anshuman Khandual +Link: https://lore.kernel.org/r/20250203050828.1049370-2-anshuman.khandual@arm.com +Signed-off-by: Catalin Marinas +Signed-off-by: Anshuman Khandual +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/tools/sysreg | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/tools/sysreg ++++ b/arch/arm64/tools/sysreg +@@ -1556,6 +1556,7 @@ EndEnum + UnsignedEnum 59:56 FGT + 0b0000 NI + 0b0001 IMP ++ 0b0010 FGT2 + EndEnum + Res0 55:48 + UnsignedEnum 47:44 EXS +@@ -1617,6 +1618,7 @@ Enum 3:0 PARANGE + 0b0100 44 + 0b0101 48 + 0b0110 52 ++ 0b0111 56 + EndEnum + EndSysreg + diff --git a/queue-6.12/series b/queue-6.12/series index 04273dfd35..eb574ee29c 100644 --- a/queue-6.12/series +++ b/queue-6.12/series @@ -183,3 +183,10 @@ drm-xe-userptr-fix-notifier-vs-folio-deadlock.patch drm-xe-set-lrc-addresses-before-guc-load.patch drm-amdgpu-fix-warning-of-drm_mm_clean.patch drm-mgag200-fix-value-in-vblkstr-register.patch +arm64-sysreg-update-register-fields-for-id_aa64mmfr0_el1.patch +arm64-sysreg-add-register-fields-for-hdfgrtr2_el2.patch +arm64-sysreg-add-register-fields-for-hdfgwtr2_el2.patch +arm64-sysreg-add-register-fields-for-hfgitr2_el2.patch +arm64-sysreg-add-register-fields-for-hfgrtr2_el2.patch +arm64-sysreg-add-register-fields-for-hfgwtr2_el2.patch +arm64-boot-enable-el2-requirements-for-feat_pmuv3p9.patch -- 2.47.3