From 27623e121cf05ca62f8869d7ca79b182e5741a11 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 25 Jul 2015 20:51:47 -0700 Subject: [PATCH] 3.10-stable patches added patches: pinctrl-mvebu-armada-370-fix-spi0-pin-description.patch pinctrl-mvebu-armada-xp-fix-functions-of-mpp48.patch pinctrl-mvebu-armada-xp-remove-non-existing-nand-pins.patch pinctrl-mvebu-armada-xp-remove-non-existing-vdd-cpu_pd-functions.patch --- ...-armada-370-fix-spi0-pin-description.patch | 50 +++++ ...ebu-armada-xp-fix-functions-of-mpp48.patch | 44 +++++ ...ada-xp-remove-non-existing-nand-pins.patch | 53 ++++++ ...ve-non-existing-vdd-cpu_pd-functions.patch | 178 ++++++++++++++++++ queue-3.10/series | 4 + queue-4.1/series | 11 ++ 6 files changed, 340 insertions(+) create mode 100644 queue-3.10/pinctrl-mvebu-armada-370-fix-spi0-pin-description.patch create mode 100644 queue-3.10/pinctrl-mvebu-armada-xp-fix-functions-of-mpp48.patch create mode 100644 queue-3.10/pinctrl-mvebu-armada-xp-remove-non-existing-nand-pins.patch create mode 100644 queue-3.10/pinctrl-mvebu-armada-xp-remove-non-existing-vdd-cpu_pd-functions.patch create mode 100644 queue-4.1/series diff --git a/queue-3.10/pinctrl-mvebu-armada-370-fix-spi0-pin-description.patch b/queue-3.10/pinctrl-mvebu-armada-370-fix-spi0-pin-description.patch new file mode 100644 index 00000000000..cf0918b4330 --- /dev/null +++ b/queue-3.10/pinctrl-mvebu-armada-370-fix-spi0-pin-description.patch @@ -0,0 +1,50 @@ +From 438881dfddb9107ef0eb30b49368e91e092f0b3e Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Tue, 9 Jun 2015 18:46:54 +0200 +Subject: pinctrl: mvebu: armada-370: fix spi0 pin description + +From: Thomas Petazzoni + +commit 438881dfddb9107ef0eb30b49368e91e092f0b3e upstream. + +Due to a mistake, the CS0 and CS1 SPI0 functions were incorrectly +named "spi0-1" instead of just "spi0". This commit fixes that. + +This DT binding change does not affect any of the in-tree users. + +Signed-off-by: Thomas Petazzoni +Fixes: 5f597bb2be57 ("pinctrl: mvebu: add pinctrl driver for Armada 370") +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt | 4 ++-- + drivers/pinctrl/mvebu/pinctrl-armada-370.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt ++++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt +@@ -91,5 +91,5 @@ mpp61 61 gpo, dev(wen1), u + mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), + audio(mclk), uart0(cts) + mpp63 63 gpo, spi0(sck), tclk +-mpp64 64 gpio, spi0(miso), spi0-1(cs1) +-mpp65 65 gpio, spi0(mosi), spi0-1(cs2) ++mpp64 64 gpio, spi0(miso), spi0(cs1) ++mpp65 65 gpio, spi0(mosi), spi0(cs2) +--- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c ++++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c +@@ -358,11 +358,11 @@ static struct mvebu_mpp_mode mv88f6710_m + MPP_MODE(64, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "spi0", "miso"), +- MPP_FUNCTION(0x2, "spi0-1", "cs1")), ++ MPP_FUNCTION(0x2, "spi0", "cs1")), + MPP_MODE(65, + MPP_FUNCTION(0x0, "gpio", NULL), + MPP_FUNCTION(0x1, "spi0", "mosi"), +- MPP_FUNCTION(0x2, "spi0-1", "cs2")), ++ MPP_FUNCTION(0x2, "spi0", "cs2")), + }; + + static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info; diff --git a/queue-3.10/pinctrl-mvebu-armada-xp-fix-functions-of-mpp48.patch b/queue-3.10/pinctrl-mvebu-armada-xp-fix-functions-of-mpp48.patch new file mode 100644 index 00000000000..b3184bf08f6 --- /dev/null +++ b/queue-3.10/pinctrl-mvebu-armada-xp-fix-functions-of-mpp48.patch @@ -0,0 +1,44 @@ +From ea78b9511a54d0de026e04b5da86b30515072f31 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Tue, 9 Jun 2015 18:46:58 +0200 +Subject: pinctrl: mvebu: armada-xp: fix functions of MPP48 + +From: Thomas Petazzoni + +commit ea78b9511a54d0de026e04b5da86b30515072f31 upstream. + +There was a mistake in the definition of the functions for MPP48 on +Marvell Armada XP. The second function is dev(clkout), and not tclk. + +Signed-off-by: Thomas Petazzoni +Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP") +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 2 +- + drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt ++++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +@@ -68,7 +68,7 @@ mpp45 45 gpio, uart2(rts), + mpp46 46 gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt) + mpp47 47 gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3), + ref(clkout) +-mpp48 48 gpio, tclk, dev(burst/last) ++mpp48 48 gpio, dev(clkout), dev(burst/last) + + * Marvell Armada XP (mv78260 and mv78460 only) + +--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c ++++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +@@ -274,7 +274,7 @@ static struct mvebu_mpp_mode armada_xp_m + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3", V_MV78230_PLUS)), + MPP_MODE(48, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x1, "tclk", NULL, V_MV78230_PLUS), ++ MPP_VAR_FUNCTION(0x1, "dev", "clkout", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS)), + MPP_MODE(49, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), diff --git a/queue-3.10/pinctrl-mvebu-armada-xp-remove-non-existing-nand-pins.patch b/queue-3.10/pinctrl-mvebu-armada-xp-remove-non-existing-nand-pins.patch new file mode 100644 index 00000000000..389b0df1489 --- /dev/null +++ b/queue-3.10/pinctrl-mvebu-armada-xp-remove-non-existing-nand-pins.patch @@ -0,0 +1,53 @@ +From bc99357f3690c11817756adfee0ece811a3db2e7 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Tue, 9 Jun 2015 18:46:56 +0200 +Subject: pinctrl: mvebu: armada-xp: remove non-existing NAND pins + +From: Thomas Petazzoni + +commit bc99357f3690c11817756adfee0ece811a3db2e7 upstream. + +After updating to a more recent version of the Armada XP datasheet, we +realized that some of the pins documented as having a NAND-related +functionality in fact did not have such functionality. This commit +updates the pinctrl driver accordingly. + +Signed-off-by: Thomas Petazzoni +Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP") +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 4 ++-- + drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 2 -- + 2 files changed, 2 insertions(+), 4 deletions(-) + +--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt ++++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +@@ -41,8 +41,8 @@ mpp20 20 gpio, ge0(rxd4), + mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat) + mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) + mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) +-mpp24 24 gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst) +-mpp25 25 gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk) ++mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) ++mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk) + mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd) + mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) + mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq) +--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c ++++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +@@ -159,13 +159,11 @@ static struct mvebu_mpp_mode armada_xp_m + MPP_MODE(24, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "sata1", "prsnt", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x2, "nf", "bootcs-re", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "tdm", "rst", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x4, "lcd", "hsync", V_MV78230_PLUS)), + MPP_MODE(25, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "sata0", "prsnt", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x2, "nf", "bootcs-we", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "tdm", "pclk", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x4, "lcd", "vsync", V_MV78230_PLUS)), + MPP_MODE(26, diff --git a/queue-3.10/pinctrl-mvebu-armada-xp-remove-non-existing-vdd-cpu_pd-functions.patch b/queue-3.10/pinctrl-mvebu-armada-xp-remove-non-existing-vdd-cpu_pd-functions.patch new file mode 100644 index 00000000000..a9ab9c1d6ee --- /dev/null +++ b/queue-3.10/pinctrl-mvebu-armada-xp-remove-non-existing-vdd-cpu_pd-functions.patch @@ -0,0 +1,178 @@ +From 80b3d04feab5e69d51cb2375eb989a7165e43e3b Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Tue, 9 Jun 2015 18:46:57 +0200 +Subject: pinctrl: mvebu: armada-xp: remove non-existing VDD cpu_pd functions + +From: Thomas Petazzoni + +commit 80b3d04feab5e69d51cb2375eb989a7165e43e3b upstream. + +The latest version of the Armada XP datasheet no longer documents the +VDD cpu_pd functions, which might indicate they are not working and/or +not supported. This commit ensures the pinctrl driver matches the +datasheet. + +Signed-off-by: Thomas Petazzoni +Fixes: 463e270f766a ("pinctrl: mvebu: add pinctrl driver for Armada XP") +Signed-off-by: Linus Walleij +Signed-off-by: Greg Kroah-Hartman + +--- + Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 26 +++---- + drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 33 +++------- + 2 files changed, 20 insertions(+), 39 deletions(-) + +--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt ++++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt +@@ -43,13 +43,13 @@ mpp22 22 gpio, ge0(rxd6), + mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) + mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) + mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk) +-mpp26 26 gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd) ++mpp26 26 gpio, lcd(clk), tdm(fsync) + mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) + mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq) +-mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd) ++mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) + mpp30 30 gpio, tdm(int1), sd0(clk) +-mpp31 31 gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd) +-mpp32 32 gpio, tdm(int3), sd0(d0), vdd(cpu1-pd) ++mpp31 31 gpio, tdm(int2), sd0(cmd) ++mpp32 32 gpio, tdm(int3), sd0(d0) + mpp33 33 gpio, tdm(int4), sd0(d1), mem(bat) + mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt) + mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) +@@ -57,14 +57,11 @@ mpp36 36 gpio, spi(mosi) + mpp37 37 gpio, spi(miso) + mpp38 38 gpio, spi(sck) + mpp39 39 gpio, spi(cs0) +-mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd), +- pcie(clkreq0) ++mpp40 40 gpio, spi(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0) + mpp41 41 gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), + pcie(clkreq1) +-mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer), +- vdd(cpu0-pd) +-mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout), +- vdd(cpu2-3-pd){1} ++mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer) ++mpp43 43 gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout) + mpp44 44 gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2), + mem(bat) + mpp45 45 gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt) +@@ -83,9 +80,9 @@ mpp51 51 gpio, dev(ad16) + mpp52 52 gpio, dev(ad17) + mpp53 53 gpio, dev(ad18) + mpp54 54 gpio, dev(ad19) +-mpp55 55 gpio, dev(ad20), vdd(cpu0-pd) +-mpp56 56 gpio, dev(ad21), vdd(cpu1-pd) +-mpp57 57 gpio, dev(ad22), vdd(cpu2-3-pd){1} ++mpp55 55 gpio, dev(ad20) ++mpp56 56 gpio, dev(ad21) ++mpp57 57 gpio, dev(ad22) + mpp58 58 gpio, dev(ad23) + mpp59 59 gpio, dev(ad24) + mpp60 60 gpio, dev(ad25) +@@ -95,6 +92,3 @@ mpp63 63 gpio, dev(ad28) + mpp64 64 gpio, dev(ad29) + mpp65 65 gpio, dev(ad30) + mpp66 66 gpio, dev(ad31) +- +-Notes: +-* {1} vdd(cpu2-3-pd) only available on mv78460. +--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c ++++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +@@ -14,10 +14,7 @@ + * available: mv78230, mv78260 and mv78460. From a pin muxing + * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460 + * both have 67 MPP pins (more GPIOs and address lines for the memory +- * bus mainly). The only difference between the mv78260 and the +- * mv78460 in terms of pin muxing is the addition of two functions on +- * pins 43 and 56 to access the VDD of the CPU2 and 3 (mv78260 has two +- * cores, mv78460 has four cores). ++ * bus mainly). + */ + + #include +@@ -169,8 +166,7 @@ static struct mvebu_mpp_mode armada_xp_m + MPP_MODE(26, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "tdm", "fsync", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)), ++ MPP_VAR_FUNCTION(0x4, "lcd", "clk", V_MV78230_PLUS)), + MPP_MODE(27, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "ptp", "trig", V_MV78230_PLUS), +@@ -185,8 +181,7 @@ static struct mvebu_mpp_mode armada_xp_m + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "ptp", "clk", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "tdm", "int0", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), ++ MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk", V_MV78230_PLUS)), + MPP_MODE(30, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "sd0", "clk", V_MV78230_PLUS), +@@ -194,13 +189,11 @@ static struct mvebu_mpp_mode armada_xp_m + MPP_MODE(31, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "sd0", "cmd", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), ++ MPP_VAR_FUNCTION(0x3, "tdm", "int2", V_MV78230_PLUS)), + MPP_MODE(32, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "sd0", "d0", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd", V_MV78230_PLUS)), ++ MPP_VAR_FUNCTION(0x3, "tdm", "int3", V_MV78230_PLUS)), + MPP_MODE(33, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "sd0", "d1", V_MV78230_PLUS), +@@ -232,7 +225,6 @@ static struct mvebu_mpp_mode armada_xp_m + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "spi", "cs1", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x2, "uart2", "cts", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x3, "vdd", "cpu1-pd", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0", V_MV78230_PLUS)), + MPP_MODE(41, +@@ -247,15 +239,13 @@ static struct mvebu_mpp_mode armada_xp_m + MPP_VAR_FUNCTION(0x1, "uart2", "rxd", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x2, "uart0", "cts", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "tdm", "int7", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd", V_MV78230_PLUS)), ++ MPP_VAR_FUNCTION(0x4, "tdm-1", "timer", V_MV78230_PLUS)), + MPP_MODE(43, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "uart2", "txd", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x2, "uart0", "rts", V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x3, "spi", "cs3", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS), +- MPP_VAR_FUNCTION(0x5, "vdd", "cpu2-3-pd", V_MV78460)), ++ MPP_VAR_FUNCTION(0x4, "pcie", "rstout", V_MV78230_PLUS)), + MPP_MODE(44, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78230_PLUS), + MPP_VAR_FUNCTION(0x1, "uart2", "cts", V_MV78230_PLUS), +@@ -306,16 +296,13 @@ static struct mvebu_mpp_mode armada_xp_m + MPP_VAR_FUNCTION(0x1, "dev", "ad19", V_MV78260_PLUS)), + MPP_MODE(55, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), +- MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS), +- MPP_VAR_FUNCTION(0x2, "vdd", "cpu0-pd", V_MV78260_PLUS)), ++ MPP_VAR_FUNCTION(0x1, "dev", "ad20", V_MV78260_PLUS)), + MPP_MODE(56, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), +- MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS), +- MPP_VAR_FUNCTION(0x2, "vdd", "cpu1-pd", V_MV78260_PLUS)), ++ MPP_VAR_FUNCTION(0x1, "dev", "ad21", V_MV78260_PLUS)), + MPP_MODE(57, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), +- MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS), +- MPP_VAR_FUNCTION(0x2, "vdd", "cpu2-3-pd", V_MV78460)), ++ MPP_VAR_FUNCTION(0x1, "dev", "ad22", V_MV78260_PLUS)), + MPP_MODE(58, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_MV78260_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad23", V_MV78260_PLUS)), diff --git a/queue-3.10/series b/queue-3.10/series index fd5a324ec4a..675f41ca90c 100644 --- a/queue-3.10/series +++ b/queue-3.10/series @@ -12,3 +12,7 @@ regulator-core-fix-constraints-output-buffer.patch spi-pl022-specify-num-cs-property-as-required-in-devicetree-binding.patch mtd-fix-avoid-race-condition-when-accessing-mtd-usecount.patch mtd-dc21285-use-raw-spinlock-functions-for-nw_gpio_lock.patch +pinctrl-mvebu-armada-370-fix-spi0-pin-description.patch +pinctrl-mvebu-armada-xp-remove-non-existing-nand-pins.patch +pinctrl-mvebu-armada-xp-remove-non-existing-vdd-cpu_pd-functions.patch +pinctrl-mvebu-armada-xp-fix-functions-of-mpp48.patch diff --git a/queue-4.1/series b/queue-4.1/series new file mode 100644 index 00000000000..ed966487639 --- /dev/null +++ b/queue-4.1/series @@ -0,0 +1,11 @@ +pinctrl-zynq-fix-define_zynq_pinmux_function_mux-macro.patch +pinctrl-zynq-fix-offset-address-for-sd0-sd1-_wp_cd_sel.patch +pinctrl-mvebu-armada-370-fix-spi0-pin-description.patch +pinctrl-mvebu-armada-375-remove-incorrect-space-in-pin-description.patch +pinctrl-mvebu-armada-375-remove-non-existing-nand-re-we-pins.patch +pinctrl-mvebu-armada-38x-fix-pcie-functions.patch +pinctrl-mvebu-armada-38x-fix-incorrect-total-number-of-gpios.patch +pinctrl-mvebu-armada-39x-fix-incorrect-total-number-of-gpios.patch +pinctrl-mvebu-armada-xp-remove-non-existing-nand-pins.patch +pinctrl-mvebu-armada-xp-remove-non-existing-vdd-cpu_pd-functions.patch +pinctrl-mvebu-armada-xp-fix-functions-of-mpp48.patch -- 2.47.3