From 323c38c915f34883439e9e53b9eac5fe07cb8378 Mon Sep 17 00:00:00 2001
From: =?utf8?q?Torbj=C3=B6rn=20SVENSSON?= <torbjorn.svensson@foss.st.com>
Date: Fri, 23 Sep 2022 20:38:45 +0200
Subject: [PATCH] Fix typo in chapter level for RISC-V attributes
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The "RISC-V specific attributes" section should be at the same level
as "PowerPC-specific attributes".

gcc/ChangeLog:

	* doc/sourcebuild.texi: Fix chapter level.

Signed-off-by: Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
---
 gcc/doc/sourcebuild.texi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 760ff9559a65..52357cc7aee9 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2447,7 +2447,7 @@ PowerPC target pre-defines macro _ARCH_PWR9 which means the @code{-mcpu}
 setting is Power9 or later.
 @end table
 
-@subsection RISC-V specific attributes
+@subsubsection RISC-V specific attributes
 
 @table @code
 
-- 
2.47.2