From 351f1d1bb18ee69a5a15003dde9d756fea85c4fc Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 15 Feb 2021 15:34:37 +0100 Subject: [PATCH] 4.19-stable patches added patches: usb-dwc3-ulpi-fix-checkpatch-warning.patch usb-dwc3-ulpi-replace-cpu-based-busyloop-with-protocol-based-one.patch --- queue-4.19/series | 2 + ...usb-dwc3-ulpi-fix-checkpatch-warning.patch | 29 ++++++ ...sed-busyloop-with-protocol-based-one.patch | 95 +++++++++++++++++++ 3 files changed, 126 insertions(+) create mode 100644 queue-4.19/usb-dwc3-ulpi-fix-checkpatch-warning.patch create mode 100644 queue-4.19/usb-dwc3-ulpi-replace-cpu-based-busyloop-with-protocol-based-one.patch diff --git a/queue-4.19/series b/queue-4.19/series index cb97236d926..e88799d0aaf 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -24,3 +24,5 @@ net-hns3-add-a-check-for-queue_id-in-hclge_reset_vf_.patch firmware_loader-align-.builtin_fw-to-8.patch i2c-stm32f7-fix-configuration-of-the-digital-filter.patch h8300-fix-preemption-build-ti_pre_count-undefined.patch +usb-dwc3-ulpi-fix-checkpatch-warning.patch +usb-dwc3-ulpi-replace-cpu-based-busyloop-with-protocol-based-one.patch diff --git a/queue-4.19/usb-dwc3-ulpi-fix-checkpatch-warning.patch b/queue-4.19/usb-dwc3-ulpi-fix-checkpatch-warning.patch new file mode 100644 index 00000000000..f37f42ca87f --- /dev/null +++ b/queue-4.19/usb-dwc3-ulpi-fix-checkpatch-warning.patch @@ -0,0 +1,29 @@ +From foo@baz Mon Feb 15 03:28:19 PM CET 2021 +From: Felipe Balbi +Date: Thu, 13 Aug 2020 08:30:38 +0300 +Subject: usb: dwc3: ulpi: fix checkpatch warning + +From: Felipe Balbi + +commit 2a499b45295206e7f3dc76edadde891c06cc4447 upstream + +no functional changes. + +Signed-off-by: Felipe Balbi +Signed-off-by: Sudip Mukherjee +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/dwc3/ulpi.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/usb/dwc3/ulpi.c ++++ b/drivers/usb/dwc3/ulpi.c +@@ -19,7 +19,7 @@ + + static int dwc3_ulpi_busyloop(struct dwc3 *dwc) + { +- unsigned count = 1000; ++ unsigned int count = 1000; + u32 reg; + + while (count--) { diff --git a/queue-4.19/usb-dwc3-ulpi-replace-cpu-based-busyloop-with-protocol-based-one.patch b/queue-4.19/usb-dwc3-ulpi-replace-cpu-based-busyloop-with-protocol-based-one.patch new file mode 100644 index 00000000000..74e805d25da --- /dev/null +++ b/queue-4.19/usb-dwc3-ulpi-replace-cpu-based-busyloop-with-protocol-based-one.patch @@ -0,0 +1,95 @@ +From foo@baz Mon Feb 15 03:28:24 PM CET 2021 +From: Serge Semin +Date: Thu, 10 Dec 2020 11:50:07 +0300 +Subject: usb: dwc3: ulpi: Replace CPU-based busyloop with Protocol-based one + +From: Serge Semin + +commit fca3f138105727c3a22edda32d02f91ce1bf11c9 upstream + +Originally the procedure of the ULPI transaction finish detection has been +developed as a simple busy-loop with just decrementing counter and no +delays. It's wrong since on different systems the loop will take a +different time to complete. So if the system bus and CPU are fast enough +to overtake the ULPI bus and the companion PHY reaction, then we'll get to +take a false timeout error. Fix this by converting the busy-loop procedure +to take the standard bus speed, address value and the registers access +mode into account for the busy-loop delay calculation. + +Here is the way the fix works. It's known that the ULPI bus is clocked +with 60MHz signal. In accordance with [1] the ULPI bus protocol is created +so to spend 5 and 6 clock periods for immediate register write and read +operations respectively, and 6 and 7 clock periods - for the extended +register writes and reads. Based on that we can easily pre-calculate the +time which will be needed for the controller to perform a requested IO +operation. Note we'll still preserve the attempts counter in case if the +DWC USB3 controller has got some internals delays. + +[1] UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, + October 20, 2004, pp. 30 - 36. + +Fixes: 88bc9d194ff6 ("usb: dwc3: add ULPI interface support") +Acked-by: Heikki Krogerus +Signed-off-by: Serge Semin +Link: https://lore.kernel.org/r/20201210085008.13264-3-Sergey.Semin@baikalelectronics.ru +Cc: stable +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sudip Mukherjee +Signed-off-by: Greg Kroah-Hartman +--- + drivers/usb/dwc3/ulpi.c | 18 +++++++++++++++--- + 1 file changed, 15 insertions(+), 3 deletions(-) + +--- a/drivers/usb/dwc3/ulpi.c ++++ b/drivers/usb/dwc3/ulpi.c +@@ -7,6 +7,8 @@ + * Author: Heikki Krogerus + */ + ++#include ++#include + #include + + #include "core.h" +@@ -17,12 +19,22 @@ + DWC3_GUSB2PHYACC_ADDR(ULPI_ACCESS_EXTENDED) | \ + DWC3_GUSB2PHYACC_EXTEND_ADDR(a) : DWC3_GUSB2PHYACC_ADDR(a)) + +-static int dwc3_ulpi_busyloop(struct dwc3 *dwc) ++#define DWC3_ULPI_BASE_DELAY DIV_ROUND_UP(NSEC_PER_SEC, 60000000L) ++ ++static int dwc3_ulpi_busyloop(struct dwc3 *dwc, u8 addr, bool read) + { ++ unsigned long ns = 5L * DWC3_ULPI_BASE_DELAY; + unsigned int count = 1000; + u32 reg; + ++ if (addr >= ULPI_EXT_VENDOR_SPECIFIC) ++ ns += DWC3_ULPI_BASE_DELAY; ++ ++ if (read) ++ ns += DWC3_ULPI_BASE_DELAY; ++ + while (count--) { ++ ndelay(ns); + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0)); + if (reg & DWC3_GUSB2PHYACC_DONE) + return 0; +@@ -47,7 +59,7 @@ static int dwc3_ulpi_read(struct device + reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr); + dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg); + +- ret = dwc3_ulpi_busyloop(dwc); ++ ret = dwc3_ulpi_busyloop(dwc, addr, true); + if (ret) + return ret; + +@@ -71,7 +83,7 @@ static int dwc3_ulpi_write(struct device + reg |= DWC3_GUSB2PHYACC_WRITE | val; + dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg); + +- return dwc3_ulpi_busyloop(dwc); ++ return dwc3_ulpi_busyloop(dwc, addr, false); + } + + static const struct ulpi_ops dwc3_ulpi_ops = { -- 2.47.2