From 37ab6b320eb5dad2c328d86244bc6f0231eaccc8 Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Sun, 24 Mar 2024 13:48:32 -0400 Subject: [PATCH] Drop clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch Signed-off-by: Sasha Levin --- ...-sc8180x-add-missing-ufs-qref-clocks.patch | 84 ------------------- queue-5.15/series | 1 - ...-sc8180x-add-missing-ufs-qref-clocks.patch | 84 ------------------- queue-6.1/series | 1 - ...-sc8180x-add-missing-ufs-qref-clocks.patch | 84 ------------------- queue-6.6/series | 1 - ...-sc8180x-add-missing-ufs-qref-clocks.patch | 84 ------------------- queue-6.7/series | 1 - 8 files changed, 340 deletions(-) delete mode 100644 queue-5.15/clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch delete mode 100644 queue-6.1/clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch delete mode 100644 queue-6.6/clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch delete mode 100644 queue-6.7/clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch diff --git a/queue-5.15/clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch b/queue-5.15/clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch deleted file mode 100644 index 0d7f6b4d22a..00000000000 --- a/queue-5.15/clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 91c3f74ccf62e25656e556f75f436041e6e90838 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Wed, 31 Jan 2024 12:37:27 +0530 -Subject: clk: qcom: gcc-sc8180x: Add missing UFS QREF clocks - -From: Manivannan Sadhasivam - -[ Upstream commit bb5c0229285fb12a5f433b2b8c5fd0ec2e4795e2 ] - -Add missing QREF clocks for UFS MEM and UFS CARD controllers. - -Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x") -Acked-by: Konrad Dybcio -Signed-off-by: Manivannan Sadhasivam -Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-4-58a49d2f4605@linaro.org -Signed-off-by: Bjorn Andersson -Signed-off-by: Sasha Levin ---- - drivers/clk/qcom/gcc-sc8180x.c | 28 ++++++++++++++++++++++++++++ - 1 file changed, 28 insertions(+) - -diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c -index c41b9f0105853..b421f67221dc1 100644 ---- a/drivers/clk/qcom/gcc-sc8180x.c -+++ b/drivers/clk/qcom/gcc-sc8180x.c -@@ -3348,6 +3348,19 @@ static struct clk_branch gcc_ufs_card_2_unipro_core_clk = { - }, - }; - -+static struct clk_branch gcc_ufs_card_clkref_en = { -+ .halt_reg = 0x8c004, -+ .halt_check = BRANCH_HALT, -+ .clkr = { -+ .enable_reg = 0x8c004, -+ .enable_mask = BIT(0), -+ .hw.init = &(const struct clk_init_data) { -+ .name = "gcc_ufs_card_clkref_en", -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ - static struct clk_branch gcc_ufs_card_ahb_clk = { - .halt_reg = 0x75014, - .halt_check = BRANCH_HALT, -@@ -3562,6 +3575,19 @@ static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { - }, - }; - -+static struct clk_branch gcc_ufs_mem_clkref_en = { -+ .halt_reg = 0x8c000, -+ .halt_check = BRANCH_HALT, -+ .clkr = { -+ .enable_reg = 0x8c000, -+ .enable_mask = BIT(0), -+ .hw.init = &(const struct clk_init_data) { -+ .name = "gcc_ufs_mem_clkref_en", -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ - static struct clk_branch gcc_ufs_phy_ahb_clk = { - .halt_reg = 0x77014, - .halt_check = BRANCH_HALT, -@@ -4414,6 +4440,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = { - [GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = &gcc_ufs_card_2_tx_symbol_0_clk.clkr, - [GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = &gcc_ufs_card_2_unipro_core_clk.clkr, - [GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_2_unipro_core_clk_src.clkr, -+ [GCC_UFS_CARD_CLKREF_EN] = &gcc_ufs_card_clkref_en.clkr, - [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, - [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, - [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, -@@ -4430,6 +4457,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = { - [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, -+ [GCC_UFS_MEM_CLKREF_EN] = &gcc_ufs_mem_clkref_en.clkr, - [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, - [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, - [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, --- -2.43.0 - diff --git a/queue-5.15/series b/queue-5.15/series index 8f82abc81fc..b661d427d71 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -188,7 +188,6 @@ pinctrl-mediatek-drop-bogus-slew-rate-register-range.patch clk-qcom-reset-commonize-the-de-assert-functions.patch clk-qcom-reset-ensure-write-completion-on-reset-de-a.patch dt-bindings-clock-qcom-add-missing-ufs-qref-clocks.patch -clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch quota-simplify-drop_dquot_ref.patch quota-fix-potential-null-pointer-dereference.patch quota-fix-rcu-annotations-of-inode-dquot-pointers.patch diff --git a/queue-6.1/clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch b/queue-6.1/clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch deleted file mode 100644 index 7f6412e3d0c..00000000000 --- a/queue-6.1/clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch +++ /dev/null @@ -1,84 +0,0 @@ -From e6ed421454ac4a68547d7115314ee8b412fff350 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Wed, 31 Jan 2024 12:37:27 +0530 -Subject: clk: qcom: gcc-sc8180x: Add missing UFS QREF clocks - -From: Manivannan Sadhasivam - -[ Upstream commit bb5c0229285fb12a5f433b2b8c5fd0ec2e4795e2 ] - -Add missing QREF clocks for UFS MEM and UFS CARD controllers. - -Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x") -Acked-by: Konrad Dybcio -Signed-off-by: Manivannan Sadhasivam -Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-4-58a49d2f4605@linaro.org -Signed-off-by: Bjorn Andersson -Signed-off-by: Sasha Levin ---- - drivers/clk/qcom/gcc-sc8180x.c | 28 ++++++++++++++++++++++++++++ - 1 file changed, 28 insertions(+) - -diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c -index c41b9f0105853..b421f67221dc1 100644 ---- a/drivers/clk/qcom/gcc-sc8180x.c -+++ b/drivers/clk/qcom/gcc-sc8180x.c -@@ -3348,6 +3348,19 @@ static struct clk_branch gcc_ufs_card_2_unipro_core_clk = { - }, - }; - -+static struct clk_branch gcc_ufs_card_clkref_en = { -+ .halt_reg = 0x8c004, -+ .halt_check = BRANCH_HALT, -+ .clkr = { -+ .enable_reg = 0x8c004, -+ .enable_mask = BIT(0), -+ .hw.init = &(const struct clk_init_data) { -+ .name = "gcc_ufs_card_clkref_en", -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ - static struct clk_branch gcc_ufs_card_ahb_clk = { - .halt_reg = 0x75014, - .halt_check = BRANCH_HALT, -@@ -3562,6 +3575,19 @@ static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { - }, - }; - -+static struct clk_branch gcc_ufs_mem_clkref_en = { -+ .halt_reg = 0x8c000, -+ .halt_check = BRANCH_HALT, -+ .clkr = { -+ .enable_reg = 0x8c000, -+ .enable_mask = BIT(0), -+ .hw.init = &(const struct clk_init_data) { -+ .name = "gcc_ufs_mem_clkref_en", -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ - static struct clk_branch gcc_ufs_phy_ahb_clk = { - .halt_reg = 0x77014, - .halt_check = BRANCH_HALT, -@@ -4414,6 +4440,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = { - [GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = &gcc_ufs_card_2_tx_symbol_0_clk.clkr, - [GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = &gcc_ufs_card_2_unipro_core_clk.clkr, - [GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_2_unipro_core_clk_src.clkr, -+ [GCC_UFS_CARD_CLKREF_EN] = &gcc_ufs_card_clkref_en.clkr, - [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, - [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, - [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, -@@ -4430,6 +4457,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = { - [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, -+ [GCC_UFS_MEM_CLKREF_EN] = &gcc_ufs_mem_clkref_en.clkr, - [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, - [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, - [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, --- -2.43.0 - diff --git a/queue-6.1/series b/queue-6.1/series index 0d07b031c7e..33f1f8ab9da 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -271,7 +271,6 @@ pinctrl-mediatek-drop-bogus-slew-rate-register-range.patch-28108 clk-qcom-reset-commonize-the-de-assert-functions.patch clk-qcom-reset-ensure-write-completion-on-reset-de-a.patch dt-bindings-clock-qcom-add-missing-ufs-qref-clocks.patch -clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch quota-simplify-drop_dquot_ref.patch quota-fix-potential-null-pointer-dereference.patch quota-fix-rcu-annotations-of-inode-dquot-pointers.patch diff --git a/queue-6.6/clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch b/queue-6.6/clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch deleted file mode 100644 index 8f2dcfa6bff..00000000000 --- a/queue-6.6/clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 680f379067b8ddb940269d8a3e77b632eb4499d3 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Wed, 31 Jan 2024 12:37:27 +0530 -Subject: clk: qcom: gcc-sc8180x: Add missing UFS QREF clocks - -From: Manivannan Sadhasivam - -[ Upstream commit bb5c0229285fb12a5f433b2b8c5fd0ec2e4795e2 ] - -Add missing QREF clocks for UFS MEM and UFS CARD controllers. - -Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x") -Acked-by: Konrad Dybcio -Signed-off-by: Manivannan Sadhasivam -Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-4-58a49d2f4605@linaro.org -Signed-off-by: Bjorn Andersson -Signed-off-by: Sasha Levin ---- - drivers/clk/qcom/gcc-sc8180x.c | 28 ++++++++++++++++++++++++++++ - 1 file changed, 28 insertions(+) - -diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c -index ae21473815596..544567db45f1f 100644 ---- a/drivers/clk/qcom/gcc-sc8180x.c -+++ b/drivers/clk/qcom/gcc-sc8180x.c -@@ -3347,6 +3347,19 @@ static struct clk_branch gcc_ufs_card_2_unipro_core_clk = { - }, - }; - -+static struct clk_branch gcc_ufs_card_clkref_en = { -+ .halt_reg = 0x8c004, -+ .halt_check = BRANCH_HALT, -+ .clkr = { -+ .enable_reg = 0x8c004, -+ .enable_mask = BIT(0), -+ .hw.init = &(const struct clk_init_data) { -+ .name = "gcc_ufs_card_clkref_en", -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ - static struct clk_branch gcc_ufs_card_ahb_clk = { - .halt_reg = 0x75014, - .halt_check = BRANCH_HALT, -@@ -3561,6 +3574,19 @@ static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { - }, - }; - -+static struct clk_branch gcc_ufs_mem_clkref_en = { -+ .halt_reg = 0x8c000, -+ .halt_check = BRANCH_HALT, -+ .clkr = { -+ .enable_reg = 0x8c000, -+ .enable_mask = BIT(0), -+ .hw.init = &(const struct clk_init_data) { -+ .name = "gcc_ufs_mem_clkref_en", -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ - static struct clk_branch gcc_ufs_phy_ahb_clk = { - .halt_reg = 0x77014, - .halt_check = BRANCH_HALT, -@@ -4413,6 +4439,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = { - [GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = &gcc_ufs_card_2_tx_symbol_0_clk.clkr, - [GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = &gcc_ufs_card_2_unipro_core_clk.clkr, - [GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_2_unipro_core_clk_src.clkr, -+ [GCC_UFS_CARD_CLKREF_EN] = &gcc_ufs_card_clkref_en.clkr, - [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, - [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, - [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, -@@ -4429,6 +4456,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = { - [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, -+ [GCC_UFS_MEM_CLKREF_EN] = &gcc_ufs_mem_clkref_en.clkr, - [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, - [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, - [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, --- -2.43.0 - diff --git a/queue-6.6/series b/queue-6.6/series index 1344ad1ea8c..0d879ab6c8d 100644 --- a/queue-6.6/series +++ b/queue-6.6/series @@ -389,7 +389,6 @@ drm-amdgpu-fix-potential-out-of-bounds-access-in-amd.patch clk-qcom-reset-commonize-the-de-assert-functions.patch clk-qcom-reset-ensure-write-completion-on-reset-de-a.patch dt-bindings-clock-qcom-add-missing-ufs-qref-clocks.patch -clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch quota-fix-potential-null-pointer-dereference.patch quota-fix-rcu-annotations-of-inode-dquot-pointers.patch quota-properly-annotate-i_dquot-arrays-with-__rcu.patch diff --git a/queue-6.7/clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch b/queue-6.7/clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch deleted file mode 100644 index 834ec8b59b2..00000000000 --- a/queue-6.7/clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch +++ /dev/null @@ -1,84 +0,0 @@ -From ecbaf6397de4dd0dfdc834621a407cf0d8d990b5 Mon Sep 17 00:00:00 2001 -From: Sasha Levin -Date: Wed, 31 Jan 2024 12:37:27 +0530 -Subject: clk: qcom: gcc-sc8180x: Add missing UFS QREF clocks - -From: Manivannan Sadhasivam - -[ Upstream commit bb5c0229285fb12a5f433b2b8c5fd0ec2e4795e2 ] - -Add missing QREF clocks for UFS MEM and UFS CARD controllers. - -Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x") -Acked-by: Konrad Dybcio -Signed-off-by: Manivannan Sadhasivam -Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-4-58a49d2f4605@linaro.org -Signed-off-by: Bjorn Andersson -Signed-off-by: Sasha Levin ---- - drivers/clk/qcom/gcc-sc8180x.c | 28 ++++++++++++++++++++++++++++ - 1 file changed, 28 insertions(+) - -diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c -index ae21473815596..544567db45f1f 100644 ---- a/drivers/clk/qcom/gcc-sc8180x.c -+++ b/drivers/clk/qcom/gcc-sc8180x.c -@@ -3347,6 +3347,19 @@ static struct clk_branch gcc_ufs_card_2_unipro_core_clk = { - }, - }; - -+static struct clk_branch gcc_ufs_card_clkref_en = { -+ .halt_reg = 0x8c004, -+ .halt_check = BRANCH_HALT, -+ .clkr = { -+ .enable_reg = 0x8c004, -+ .enable_mask = BIT(0), -+ .hw.init = &(const struct clk_init_data) { -+ .name = "gcc_ufs_card_clkref_en", -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ - static struct clk_branch gcc_ufs_card_ahb_clk = { - .halt_reg = 0x75014, - .halt_check = BRANCH_HALT, -@@ -3561,6 +3574,19 @@ static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = { - }, - }; - -+static struct clk_branch gcc_ufs_mem_clkref_en = { -+ .halt_reg = 0x8c000, -+ .halt_check = BRANCH_HALT, -+ .clkr = { -+ .enable_reg = 0x8c000, -+ .enable_mask = BIT(0), -+ .hw.init = &(const struct clk_init_data) { -+ .name = "gcc_ufs_mem_clkref_en", -+ .ops = &clk_branch2_ops, -+ }, -+ }, -+}; -+ - static struct clk_branch gcc_ufs_phy_ahb_clk = { - .halt_reg = 0x77014, - .halt_check = BRANCH_HALT, -@@ -4413,6 +4439,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = { - [GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = &gcc_ufs_card_2_tx_symbol_0_clk.clkr, - [GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = &gcc_ufs_card_2_unipro_core_clk.clkr, - [GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_2_unipro_core_clk_src.clkr, -+ [GCC_UFS_CARD_CLKREF_EN] = &gcc_ufs_card_clkref_en.clkr, - [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr, - [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr, - [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr, -@@ -4429,6 +4456,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = { - [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr, - [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr, -+ [GCC_UFS_MEM_CLKREF_EN] = &gcc_ufs_mem_clkref_en.clkr, - [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, - [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, - [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, --- -2.43.0 - diff --git a/queue-6.7/series b/queue-6.7/series index 8a8e328a4ed..91a2a61ec5b 100644 --- a/queue-6.7/series +++ b/queue-6.7/series @@ -436,7 +436,6 @@ drm-amdgpu-fix-potential-out-of-bounds-access-in-amd.patch clk-qcom-reset-commonize-the-de-assert-functions.patch clk-qcom-reset-ensure-write-completion-on-reset-de-a.patch dt-bindings-clock-qcom-add-missing-ufs-qref-clocks.patch -clk-qcom-gcc-sc8180x-add-missing-ufs-qref-clocks.patch quota-fix-potential-null-pointer-dereference.patch quota-fix-rcu-annotations-of-inode-dquot-pointers.patch quota-properly-annotate-i_dquot-arrays-with-__rcu.patch -- 2.47.2