From 396e589a72dc51c624c54772d0b52980eded2bcc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 12 Feb 2021 17:37:29 +0100 Subject: [PATCH] arm64: dts: exynos: re-order Slim SSS clocks to match dtschema The dtschema expects pclk (APB clock) followed by aclk (AXI/AHB clock): arch/arm64/boot/dts/exynos/exynos5433-tm2.dt.yaml: slim-sss@11140000: clock-names:0: 'pclk' was expected arch/arm64/boot/dts/exynos/exynos5433-tm2.dt.yaml: slim-sss@11140000: clock-names:1: 'aclk' was expected Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210212163729.69882-1-krzk@kernel.org --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 6433f9ee35e19..18a912eee3605 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -564,9 +564,9 @@ compatible = "samsung,exynos5433-slim-sss"; reg = <0x11140000 0x1000>; interrupts = ; - clock-names = "aclk", "pclk"; - clocks = <&cmu_imem CLK_ACLK_SLIMSSS>, - <&cmu_imem CLK_PCLK_SLIMSSS>; + clock-names = "pclk", "aclk"; + clocks = <&cmu_imem CLK_PCLK_SLIMSSS>, + <&cmu_imem CLK_ACLK_SLIMSSS>; }; pd_gscl: power-domain@105c4000 { -- 2.47.2