From 3a5cb240e72b941bb9ade4dc4cb523108f9e41f1 Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Sat, 11 May 2024 19:37:41 -0400 Subject: [PATCH] Fixes for 5.15 Signed-off-by: Sasha Levin --- ...-access-width-used-for-pcc-registers.patch | 134 ++++++++++++++++++ ...x-bit_offset-shift-in-mask_val-macro.patch | 48 +++++++ ...atom-integrated-system-info-v2_2-for.patch | 42 ++++++ ...pi-cppc-use-access_width-over-bit_wi.patch | 105 ++++++++++++++ queue-5.15/series | 4 + 5 files changed, 333 insertions(+) create mode 100644 queue-5.15/acpi-cppc-fix-access-width-used-for-pcc-registers.patch create mode 100644 queue-5.15/acpi-cppc-fix-bit_offset-shift-in-mask_val-macro.patch create mode 100644 queue-5.15/drm-amd-display-atom-integrated-system-info-v2_2-for.patch create mode 100644 queue-5.15/revert-revert-acpi-cppc-use-access_width-over-bit_wi.patch diff --git a/queue-5.15/acpi-cppc-fix-access-width-used-for-pcc-registers.patch b/queue-5.15/acpi-cppc-fix-access-width-used-for-pcc-registers.patch new file mode 100644 index 00000000000..d181fdb7ea2 --- /dev/null +++ b/queue-5.15/acpi-cppc-fix-access-width-used-for-pcc-registers.patch @@ -0,0 +1,134 @@ +From 77fb952ae0fe9f7a53f258c57a71ceb83b0a2cf7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 May 2024 19:41:26 +0000 +Subject: ACPI: CPPC: Fix access width used for PCC registers + +From: Vanshidhar Konda + +commit f489c948028b69cea235d9c0de1cc10eeb26a172 upstream + +commit 2f4a4d63a193 ("ACPI: CPPC: Use access_width over bit_width for system +memory accesses") modified cpc_read()/cpc_write() to use access_width to +read CPC registers. + +However, for PCC registers the access width field in the ACPI register +macro specifies the PCC subspace ID. For non-zero PCC subspace ID it is +incorrectly treated as access width. This causes errors when reading +from PCC registers in the CPPC driver. + +For PCC registers, base the size of read/write on the bit width field. +The debug message in cpc_read()/cpc_write() is updated to print relevant +information for the address space type used to read the register. + +Fixes: 2f4a4d63a193 ("ACPI: CPPC: Use access_width over bit_width for system memory accesses") +Signed-off-by: Vanshidhar Konda +Tested-by: Jarred White +Reviewed-by: Jarred White +Reviewed-by: Easwar Hariharan +Cc: 5.15+ # 5.15+ +Signed-off-by: Rafael J. Wysocki +[ eahariha: Backport to v5.15 by dropping SystemIO bits as commit + a2c8f92bea5f is not present ] +Signed-off-by: Easwar Hariharan +Signed-off-by: Sasha Levin +--- + drivers/acpi/cppc_acpi.c | 48 ++++++++++++++++++++++++++++++---------- + 1 file changed, 36 insertions(+), 12 deletions(-) + +diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c +index 6aa456cda0ed9..6dcce036adb9c 100644 +--- a/drivers/acpi/cppc_acpi.c ++++ b/drivers/acpi/cppc_acpi.c +@@ -955,17 +955,24 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) + } + + *val = 0; +- if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) ++ size = GET_BIT_WIDTH(reg); ++ ++ if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) { ++ /* ++ * For registers in PCC space, the register size is determined ++ * by the bit width field; the access size is used to indicate ++ * the PCC subspace id. ++ */ ++ size = reg->bit_width; + vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); ++ } + else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) + vaddr = reg_res->sys_mem_vaddr; + else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) + return cpc_read_ffh(cpu, reg, val); + else + return acpi_os_read_memory((acpi_physical_address)reg->address, +- val, reg->bit_width); +- +- size = GET_BIT_WIDTH(reg); ++ val, size); + + switch (size) { + case 8: +@@ -981,8 +988,13 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) + *val = readq_relaxed(vaddr); + break; + default: +- pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n", +- reg->bit_width, pcc_ss_id); ++ if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { ++ pr_debug("Error: Cannot read %u bit width from system memory: 0x%llx\n", ++ size, reg->address); ++ } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { ++ pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n", ++ size, pcc_ss_id); ++ } + ret_val = -EFAULT; + } + +@@ -1000,17 +1012,24 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_reg *reg = ®_res->cpc_entry.reg; + +- if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) ++ size = GET_BIT_WIDTH(reg); ++ ++ if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) { ++ /* ++ * For registers in PCC space, the register size is determined ++ * by the bit width field; the access size is used to indicate ++ * the PCC subspace id. ++ */ ++ size = reg->bit_width; + vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id); ++ } + else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) + vaddr = reg_res->sys_mem_vaddr; + else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) + return cpc_write_ffh(cpu, reg, val); + else + return acpi_os_write_memory((acpi_physical_address)reg->address, +- val, reg->bit_width); +- +- size = GET_BIT_WIDTH(reg); ++ val, size); + + if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) + val = MASK_VAL(reg, val); +@@ -1029,8 +1048,13 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) + writeq_relaxed(val, vaddr); + break; + default: +- pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n", +- reg->bit_width, pcc_ss_id); ++ if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { ++ pr_debug("Error: Cannot write %u bit width to system memory: 0x%llx\n", ++ size, reg->address); ++ } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) { ++ pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n", ++ size, pcc_ss_id); ++ } + ret_val = -EFAULT; + break; + } +-- +2.43.0 + diff --git a/queue-5.15/acpi-cppc-fix-bit_offset-shift-in-mask_val-macro.patch b/queue-5.15/acpi-cppc-fix-bit_offset-shift-in-mask_val-macro.patch new file mode 100644 index 00000000000..fc4edf23fba --- /dev/null +++ b/queue-5.15/acpi-cppc-fix-bit_offset-shift-in-mask_val-macro.patch @@ -0,0 +1,48 @@ +From 725de4f2dfd5637d19bd9f04cff11f24da241807 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 May 2024 19:41:25 +0000 +Subject: ACPI: CPPC: Fix bit_offset shift in MASK_VAL() macro + +From: Jarred White + +commit 05d92ee782eeb7b939bdd0189e6efcab9195bf95 upstream + +Commit 2f4a4d63a193 ("ACPI: CPPC: Use access_width over bit_width for +system memory accesses") neglected to properly wrap the bit_offset shift +when it comes to applying the mask. This may cause incorrect values to be +read and may cause the cpufreq module not be loaded. + +[ 11.059751] cpu_capacity: CPU0 missing/invalid highest performance. +[ 11.066005] cpu_capacity: partial information: fallback to 1024 for all CPUs + +Also, corrected the bitmask generation in GENMASK (extra bit being added). + +Fixes: 2f4a4d63a193 ("ACPI: CPPC: Use access_width over bit_width for system memory accesses") +Signed-off-by: Jarred White +Cc: 5.15+ # 5.15+ +Reviewed-by: Vanshidhar Konda +Signed-off-by: Rafael J. Wysocki +Signed-off-by: Easwar Hariharan +Signed-off-by: Sasha Levin +--- + drivers/acpi/cppc_acpi.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c +index 408b1fda5702d..6aa456cda0ed9 100644 +--- a/drivers/acpi/cppc_acpi.c ++++ b/drivers/acpi/cppc_acpi.c +@@ -165,8 +165,8 @@ show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); + #define GET_BIT_WIDTH(reg) ((reg)->access_width ? (8 << ((reg)->access_width - 1)) : (reg)->bit_width) + + /* Shift and apply the mask for CPC reads/writes */ +-#define MASK_VAL(reg, val) ((val) >> ((reg)->bit_offset & \ +- GENMASK(((reg)->bit_width), 0))) ++#define MASK_VAL(reg, val) (((val) >> (reg)->bit_offset) & \ ++ GENMASK(((reg)->bit_width) - 1, 0)) + + static ssize_t show_feedback_ctrs(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +-- +2.43.0 + diff --git a/queue-5.15/drm-amd-display-atom-integrated-system-info-v2_2-for.patch b/queue-5.15/drm-amd-display-atom-integrated-system-info-v2_2-for.patch new file mode 100644 index 00000000000..f492b4ffa1f --- /dev/null +++ b/queue-5.15/drm-amd-display-atom-integrated-system-info-v2_2-for.patch @@ -0,0 +1,42 @@ +From 46849470804fc516ad840a2779f5b53aafe9b6b2 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 9 Apr 2024 10:38:58 -0400 +Subject: drm/amd/display: Atom Integrated System Info v2_2 for DCN35 + +From: Gabe Teeger + +[ Upstream commit 9a35d205f466501dcfe5625ca313d944d0ac2d60 ] + +New request from KMD/VBIOS in order to support new UMA carveout +model. This fixes a null dereference from accessing +Ctx->dc_bios->integrated_info while it was NULL. + +DAL parses through the BIOS and extracts the necessary +integrated_info but was missing a case for the new BIOS +version 2.3. + +Reviewed-by: Nicholas Kazlauskas +Acked-by: Aurabindo Pillai +Signed-off-by: Gabe Teeger +Tested-by: Daniel Wheeler +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +index 228f098e5d88f..6bc8c6bee411e 100644 +--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c ++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +@@ -2303,6 +2303,7 @@ static enum bp_result construct_integrated_info( + result = get_integrated_info_v2_1(bp, info); + break; + case 2: ++ case 3: + result = get_integrated_info_v2_2(bp, info); + break; + default: +-- +2.43.0 + diff --git a/queue-5.15/revert-revert-acpi-cppc-use-access_width-over-bit_wi.patch b/queue-5.15/revert-revert-acpi-cppc-use-access_width-over-bit_wi.patch new file mode 100644 index 00000000000..9367cc6b478 --- /dev/null +++ b/queue-5.15/revert-revert-acpi-cppc-use-access_width-over-bit_wi.patch @@ -0,0 +1,105 @@ +From 202e859aa0c1e9d484761bed97d7a447f184c863 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 9 May 2024 19:41:24 +0000 +Subject: Revert "Revert "ACPI: CPPC: Use access_width over bit_width for + system memory accesses"" + +From: Easwar Hariharan + +This reverts commit b54c4632946ae42f2b39ed38abd909bbf78cbcc2 which was a +revert of a backport of commit 2f4a4d63a193be6fd530d180bb13c3592052904c +upstream to 5.15.y. + +Cc: Jarred White +Cc: Rafael J. Wysocki +Cc: Vanshidhar Konda +Cc: Greg Kroah-Hartman +Signed-off-by: Easwar Hariharan +Signed-off-by: Sasha Levin +--- + drivers/acpi/cppc_acpi.c | 27 ++++++++++++++++++++++++--- + 1 file changed, 24 insertions(+), 3 deletions(-) + +diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c +index 7cc9183c8dc8e..408b1fda5702d 100644 +--- a/drivers/acpi/cppc_acpi.c ++++ b/drivers/acpi/cppc_acpi.c +@@ -161,6 +161,13 @@ show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); + show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); + show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); + ++/* Check for valid access_width, otherwise, fallback to using bit_width */ ++#define GET_BIT_WIDTH(reg) ((reg)->access_width ? (8 << ((reg)->access_width - 1)) : (reg)->bit_width) ++ ++/* Shift and apply the mask for CPC reads/writes */ ++#define MASK_VAL(reg, val) ((val) >> ((reg)->bit_offset & \ ++ GENMASK(((reg)->bit_width), 0))) ++ + static ssize_t show_feedback_ctrs(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) + { +@@ -762,8 +769,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr) + } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { + if (gas_t->address) { + void __iomem *addr; ++ size_t access_width; + +- addr = ioremap(gas_t->address, gas_t->bit_width/8); ++ access_width = GET_BIT_WIDTH(gas_t) / 8; ++ addr = ioremap(gas_t->address, access_width); + if (!addr) + goto out_free; + cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr; +@@ -936,6 +945,7 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) + { + int ret_val = 0; + void __iomem *vaddr = NULL; ++ int size; + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_reg *reg = ®_res->cpc_entry.reg; + +@@ -955,7 +965,9 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) + return acpi_os_read_memory((acpi_physical_address)reg->address, + val, reg->bit_width); + +- switch (reg->bit_width) { ++ size = GET_BIT_WIDTH(reg); ++ ++ switch (size) { + case 8: + *val = readb_relaxed(vaddr); + break; +@@ -974,12 +986,16 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val) + ret_val = -EFAULT; + } + ++ if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) ++ *val = MASK_VAL(reg, *val); ++ + return ret_val; + } + + static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) + { + int ret_val = 0; ++ int size; + void __iomem *vaddr = NULL; + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_reg *reg = ®_res->cpc_entry.reg; +@@ -994,7 +1010,12 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val) + return acpi_os_write_memory((acpi_physical_address)reg->address, + val, reg->bit_width); + +- switch (reg->bit_width) { ++ size = GET_BIT_WIDTH(reg); ++ ++ if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) ++ val = MASK_VAL(reg, val); ++ ++ switch (size) { + case 8: + writeb_relaxed(val, vaddr); + break; +-- +2.43.0 + diff --git a/queue-5.15/series b/queue-5.15/series index 4d8b4b628f8..9f5ebbd92ea 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -136,3 +136,7 @@ net-hns3-fix-port-vlan-filter-not-disabled-issue.patch drm-meson-dw-hdmi-power-up-phy-on-device-init.patch drm-meson-dw-hdmi-add-bandgap-setting-for-g12.patch drm-connector-add-n-to-message-about-demoting-connec.patch +drm-amd-display-atom-integrated-system-info-v2_2-for.patch +revert-revert-acpi-cppc-use-access_width-over-bit_wi.patch +acpi-cppc-fix-bit_offset-shift-in-mask_val-macro.patch +acpi-cppc-fix-access-width-used-for-pcc-registers.patch -- 2.47.2