From 3ef3a1f5a19eefbe6ce5b7e0fc143d982214f1c1 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 19 Jan 2015 21:27:56 +0800 Subject: [PATCH] 3.10-stable patches added patches: arc-move-peripherals-to-match-model-to-fpga.patch drm-i915-force-the-cs-stall-for-invalidate-flushes.patch drm-i915-invalidate-media-caches-on-gen7.patch --- ...e-peripherals-to-match-model-to-fpga.patch | 69 +++++++++++++++++++ ...-the-cs-stall-for-invalidate-flushes.patch | 40 +++++++++++ ...i915-invalidate-media-caches-on-gen7.patch | 50 ++++++++++++++ queue-3.10/series | 3 + 4 files changed, 162 insertions(+) create mode 100644 queue-3.10/arc-move-peripherals-to-match-model-to-fpga.patch create mode 100644 queue-3.10/drm-i915-force-the-cs-stall-for-invalidate-flushes.patch create mode 100644 queue-3.10/drm-i915-invalidate-media-caches-on-gen7.patch diff --git a/queue-3.10/arc-move-peripherals-to-match-model-to-fpga.patch b/queue-3.10/arc-move-peripherals-to-match-model-to-fpga.patch new file mode 100644 index 00000000000..cf2b41464c3 --- /dev/null +++ b/queue-3.10/arc-move-peripherals-to-match-model-to-fpga.patch @@ -0,0 +1,69 @@ +From e8ef060b37c2d3cc5fd0c0edbe4e42ec1cb9768b Mon Sep 17 00:00:00 2001 +From: Vineet Gupta +Date: Wed, 1 Oct 2014 14:28:36 +0530 +Subject: ARC: [nsimosci] move peripherals to match model to FPGA + +From: Vineet Gupta + +commit e8ef060b37c2d3cc5fd0c0edbe4e42ec1cb9768b upstream. + +This allows the sdplite/Zebu images to run on OSCI simulation platform + +Signed-off-by: Vineet Gupta +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arc/boot/dts/nsimosci.dts | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +--- a/arch/arc/boot/dts/nsimosci.dts ++++ b/arch/arc/boot/dts/nsimosci.dts +@@ -20,7 +20,7 @@ + /* this is for console on PGU */ + /* bootargs = "console=tty0 consoleblank=0"; */ + /* this is for console on serial */ +- bootargs = "earlycon=uart8250,mmio32,0xc0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug"; ++ bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug"; + }; + + aliases { +@@ -46,9 +46,9 @@ + #interrupt-cells = <1>; + }; + +- uart0: serial@c0000000 { ++ uart0: serial@f0000000 { + compatible = "ns8250"; +- reg = <0xc0000000 0x2000>; ++ reg = <0xf0000000 0x2000>; + interrupts = <11>; + clock-frequency = <3686400>; + baud = <115200>; +@@ -57,21 +57,21 @@ + no-loopback-test = <1>; + }; + +- pgu0: pgu@c9000000 { ++ pgu0: pgu@f9000000 { + compatible = "snps,arcpgufb"; +- reg = <0xc9000000 0x400>; ++ reg = <0xf9000000 0x400>; + }; + +- ps2: ps2@c9001000 { ++ ps2: ps2@f9001000 { + compatible = "snps,arc_ps2"; +- reg = <0xc9000400 0x14>; ++ reg = <0xf9000400 0x14>; + interrupts = <13>; + interrupt-names = "arc_ps2_irq"; + }; + +- eth0: ethernet@c0003000 { ++ eth0: ethernet@f0003000 { + compatible = "snps,oscilan"; +- reg = <0xc0003000 0x44>; ++ reg = <0xf0003000 0x44>; + interrupts = <7>, <8>; + interrupt-names = "rx", "tx"; + }; diff --git a/queue-3.10/drm-i915-force-the-cs-stall-for-invalidate-flushes.patch b/queue-3.10/drm-i915-force-the-cs-stall-for-invalidate-flushes.patch new file mode 100644 index 00000000000..bf7d92f88a0 --- /dev/null +++ b/queue-3.10/drm-i915-force-the-cs-stall-for-invalidate-flushes.patch @@ -0,0 +1,40 @@ +From add284a3a2481e759d6bec35f6444c32c8ddc383 Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Tue, 16 Dec 2014 08:44:32 +0000 +Subject: drm/i915: Force the CS stall for invalidate flushes +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Chris Wilson + +commit add284a3a2481e759d6bec35f6444c32c8ddc383 upstream. + +In order to act as a full command barrier by itself, we need to tell the +pipecontrol to actually stall the command streamer while the flush runs. +We require the full command barrier before operations like +MI_SET_CONTEXT, which currently rely on a prior invalidate flush. + +References: https://bugs.freedesktop.org/show_bug.cgi?id=83677 +Cc: Simon Farnsworth +Cc: Daniel Vetter +Cc: Ville Syrjälä +Signed-off-by: Chris Wilson +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/gpu/drm/i915/intel_ringbuffer.c ++++ b/drivers/gpu/drm/i915/intel_ringbuffer.c +@@ -321,6 +321,8 @@ gen7_render_ring_flush(struct intel_ring + flags |= PIPE_CONTROL_QW_WRITE; + flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; + ++ flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; ++ + /* Workaround: we must issue a pipe_control with CS-stall bit + * set before a pipe_control command that has the state cache + * invalidate bit set. */ diff --git a/queue-3.10/drm-i915-invalidate-media-caches-on-gen7.patch b/queue-3.10/drm-i915-invalidate-media-caches-on-gen7.patch new file mode 100644 index 00000000000..8934ac68648 --- /dev/null +++ b/queue-3.10/drm-i915-invalidate-media-caches-on-gen7.patch @@ -0,0 +1,50 @@ +From 148b83d0815a3778c8949e6a97cb798cbaa0efb3 Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Tue, 16 Dec 2014 08:44:31 +0000 +Subject: drm/i915: Invalidate media caches on gen7 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Chris Wilson + +commit 148b83d0815a3778c8949e6a97cb798cbaa0efb3 upstream. + +In the gen7 pipe control there is an extra bit to flush the media +caches, so let's set it during cache invalidation flushes. + +v2: Rename to MEDIA_STATE_CLEAR to be more inline with spec. + +Cc: Simon Farnsworth +Cc: Ville Syrjälä +Cc: Daniel Vetter +Signed-off-by: Chris Wilson +Reviewed-by: Daniel Vetter +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_reg.h | 1 + + drivers/gpu/drm/i915/intel_ringbuffer.c | 1 + + 2 files changed, 2 insertions(+) + +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -317,6 +317,7 @@ + #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ + #define PIPE_CONTROL_CS_STALL (1<<20) + #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) ++#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16) + #define PIPE_CONTROL_QW_WRITE (1<<14) + #define PIPE_CONTROL_DEPTH_STALL (1<<13) + #define PIPE_CONTROL_WRITE_FLUSH (1<<12) +--- a/drivers/gpu/drm/i915/intel_ringbuffer.c ++++ b/drivers/gpu/drm/i915/intel_ringbuffer.c +@@ -314,6 +314,7 @@ gen7_render_ring_flush(struct intel_ring + flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; ++ flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; + /* + * TLB invalidate requires a post-sync write. + */ diff --git a/queue-3.10/series b/queue-3.10/series index 05e999c9b40..c5bde00f93e 100644 --- a/queue-3.10/series +++ b/queue-3.10/series @@ -7,3 +7,6 @@ enic-fix-rx-skb-checksum.patch drm-vmwgfx-fix-fence-event-code.patch drm-radeon-check-the-right-ring-in-radeon_evict_flags.patch drm-radeon-properly-filter-dp1.2-4k-modes-on-non-dp1.2-hw.patch +drm-i915-invalidate-media-caches-on-gen7.patch +drm-i915-force-the-cs-stall-for-invalidate-flushes.patch +arc-move-peripherals-to-match-model-to-fpga.patch -- 2.47.3