From 3fbb46409f012aea9c1443ae4bd9f49d4fcabd75 Mon Sep 17 00:00:00 2001 From: Fabiano Rosas Date: Fri, 28 Jan 2022 13:15:06 +0100 Subject: [PATCH] target/ppc: 74xx: Machine Check exception cleanup MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The 74xx don't have an MSR_HV. Also remove 40x and BookE code. Signed-off-by: Fabiano Rosas Message-Id: <20220127201116.1154733-4-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater --- target/ppc/excp_helper.c | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 13e5cb3ddcd..0d8c66b98fd 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -612,34 +612,10 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) cs->halted = 1; cpu_interrupt_exittb(cs); } - if (env->msr_mask & MSR_HVB) { - /* - * ISA specifies HV, but can be delivered to guest with HV - * clear (e.g., see FWNMI in PAPR). - */ - new_msr |= (target_ulong)MSR_HVB; - } /* machine check exceptions don't have ME set */ new_msr &= ~((target_ulong)1 << MSR_ME); - /* XXX: should also have something loaded in DAR / DSISR */ - switch (excp_model) { - case POWERPC_EXCP_40x: - srr0 = SPR_40x_SRR2; - srr1 = SPR_40x_SRR3; - break; - case POWERPC_EXCP_BOOKE: - /* FIXME: choose one or the other based on CPU type */ - srr0 = SPR_BOOKE_MCSRR0; - srr1 = SPR_BOOKE_MCSRR1; - - env->spr[SPR_BOOKE_CSRR0] = env->nip; - env->spr[SPR_BOOKE_CSRR1] = msr; - break; - default: - break; - } break; case POWERPC_EXCP_DSI: /* Data storage exception */ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); -- 2.39.5